Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor fox amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A memory sense amplifier includes a latch formed for interconnected CMOS gates with an input gate connected to one node of the latch and a reference gate connected to the other node of the latch the reference gate has an input connected to a source of reference voltage and the reference gate and input gate are activated in response to common enable signal. When the input signal, e.g., a data signal from a memory, has a signal value lower than the reference signal value when the two gates are enabled, the reference gate will discharge the node to which it is connected more rapidly than the input gate will discharge the other node. Due to the internal cross connections of the latch, the latch will rapidly change state so as to further discharge the node to which the reference is connected and further charge the other node.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a memory array. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A current sense amplifier circuit for a semiconductor memory device includes a differential amplifier which senses the signal currents input to first and second input nodes, amplifies the difference between the two signals and outputs the sense-amplified signals to first and second output nodes. A first feedback circuit is connected between the second input node and a current controlling node and has a controlling terminal connected to the first output node. A second feedback circuit is connected between the first input node and the current controlling node and has a controlling terminal connected to the second output node. By feeding back voltages from the counterpart output nodes through the cross-connected feedback circuits, the difference between low level input signals can be efficiently detected and a stable sense-amplified output is obtained.

Abstract: An asymmetric switch which minimizes transistor exposure to high voltage includes one pair of P-channel transistors with both N-wells coupled back to the programming voltage source and one, pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit are also included to provide complementary input voltages to the switch. The P-channel and N-channel transistors used as guard devices may be biased by the same voltage or separate voltages.

Abstract: A circuit and method for sensing and limiting current. An output driving transistor (M1) is coupled between a circuit output terminal and a power supply terminal. A replicator circuit is formed in a cross-coupled quad configuration from bipolar transistors (Q11, Q12, Q13 and Q14) and is coupled to a second transistor (M2) which generals a voltage proportional to the current flowing in the output driving transistor (M1). The current sensing circuit generates an output current which is proportional to the current flowing in the output driving transistor multiplied by a ratio of the sizes of the second transistor and the output driving transistor. In a current limiting configuration, the output of the cross-coupled quad is used to reset a flip-flop (FF1) that drives the gate terminal of the output transistor (M1), thus shutting down the output transistor before it is damaged due to excess current. The circuitry of the invention may be applied to a high side driver or a low side driver output circuit.

Abstract: A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only whi

Abstract: A differential sense amplifier is provided wherein a first amplifier stage is biased to minimize current consumption of all stages of the amplifier and to provide outputs of the first stage that are high enough in voltage to allow proper operation of a second stage of the amplifier, yet low enough in voltage to allow a current mirror to be integrated into the second stage of the amplifier. The integration of the third stage current mirror into the second stage amplifier reduces capacitive loading on the outputs of the second stage increasing speed while eliminating the extra power normally associated with a separate current mirror. This combination results in a very fast, yet very low power amplifier.

Abstract: A circuit connects a circuit node to a voltage source selected between two alternative power supply voltage sources. The circuit includes two transistors, specifically a first transistor selectively connecting the circuit node to a first power supply voltage source of the two alternative power supply voltage sources and a second transistor selectively connecting the circuit node to the second power supply voltage source. The first transistor has a gate connected to the second power supply voltage source. The second transistor has a gate connected to the first power supply voltage source. The circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node. The circuit is useful, for example, in a voltage translation and overvoltage protection circuit.

Abstract: A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

Abstract: A latch-type current sense amplifier circuit generates complementary latched data outputs indicative of a difference between first and second input currents provided to the sense amplifier circuit respectively via first and second input data lines. Included in the sense amplifier circuit are a latch circuit formed from cross-coupled inverters, a transmission gate responsive to a first control signal for equalizing the outputs of the sense amplifier circuit, and three transistors. The first transistor is responsive to a second control signal, activated after a delay after deactivation of the first control signal, for connecting a reference voltage to the latch circuit.

Abstract: A serial differential cell includes complementary positive and negative pass gate networks coupled to a differential amplifier, which produces a valid logic output. The complementary pass gate networks can include one or more pass gate stages coupled in series. In a serial differential multiplexer, a stage includes first and second inputs, and a select input for controlling which input is passed to an output of the stage. For multiple stages, the output of a first stage is coupled to one of the inputs of a next stage. A number of stages can be coupled together in series to form networks, with a differential amplifier coupled between positive and negative networks where necessary to provide a valid logic output.

Abstract: A circuit array for amplifying and holding data with different supply voltages includes a first flip-flop being constructed in MOS technology for receiving a low supply voltage and data with a low supply voltage. The first flip-flop has output terminals. A second flip-flop being constructed in MOS technology receives a high supply voltage. The second flip-flop has a load segment and output terminals. At least one additional MOS transistor is connected in series with each of the output terminals of the second flip-flop between the load segment and ground. The at least one additional MOS transistor each has a gate terminal being connected to a respective one of the output terminals of the first flip-flip. A device for activating the first and second flip-flops is triggered for amplifying and holding the data to activate the first flip-flop and to activate the second flip-flop after a time delay.

Abstract: There is disclosed a sense amplifier for a semiconductor memory device comprising a cross coupled latch for sense-amplifying data signals on bit lines, a pull-up driver connected between the cross coupled latch and a supply voltage source for controlling an amount of current of a supply voltage being supplied to the cross coupled latch, a pull-down driver connected between the cross coupled latch and a ground voltage source for controlling an amount of current of a ground voltage being supplied no the cross coupled latch, and a voltage detector for detecting a difference between the supply voltage and the ground voltage and controlling the pull-up driver and the pull-down driver in accordance with the detected result. According to the present invention, when the voltage difference is high in level, the sense amplifier minimizes a noise component being generated. In the case where the voltage difference is low in level, the sense amplifier amplifies the data signals on the bit lines at a high speed.

Abstract: A flip-flop type amplifier circuit is adapted to amplify a voltage difference between a first voltage and a second voltage. This amplifier circuit includes a first power line supplying a first power supply voltage, a second power line supplying a second power supply voltage lower than the first power supply voltage, a flip-flop circuit including first through fourth nodes, and first and second inverters coupled in a ring. The first node couples an input of the first inverter and an output of the second inverter and receiving the first voltage, and the second node couples an output of the first inverter and an input of the second inverter and receives the second voltage. A first impedance element is coupled between the first power line and the third node of the flip-flop circuit, and a second impedance element is coupled between the second power line and the fourth node of the flip-flop circuit.

Abstract: A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

Abstract: A sense amplifier for detecting the difference in voltage between two bitlines of a memory circuit. The sense amplifier is comprised of a differential amplifier which is coupled to the two bitlines and generates an output signal based on voltage levels sensed in the bitlines. The differential amplifier is coupled to V.sub.CC and ground through an active load and a current source respectively. To address the problem of increased common mode voltage levels found in the bitlines, a pair of transistors are connected in parallel across the active load to V.sub.CC and the differential amplifier. The gate of one of the transistors is coupled to one of the bitlines and the gate of the other one of the transistors is coupled to the other one of the bitlines. With these two transistors coupled in parallel across the load as described, the differential amplifier has increased immunity to elevated common mode levels found in the bitlines.

Abstract: A data input/output line sensing circuit includes a latch sense circuit having the double functions of performing a latch operation and a sensing operation for data read from a memory cell. The latch sense circuit includes a first inverter having an input end connected to one of the data input/output lines, and an output end connected to the other of the data input/output lines; a first switching transistor provides the first inverter with a power supply voltage and a ground voltage only during a sensing operation in response to a sensing control signal; a second inverter having an input end connected to the output of the first inverter, and an output end connected to the input of the first inverter; and a second switching transistor provides the second inverter with the power supply voltage and the ground voltage only during the sensing operation in response to the sensing control signal.

Abstract: A differential latch sense amplifier for memories has (a) a first differential input circuit for detecting and shifting the voltage levels of the first and second input signals and coupled to first and second sense nodes, (b) a cross-coupled latch for providing gain to the first and second sense nodes, (c) a precharge circuit for precharging and equalizing the first and second sense nodes, (d) a first tristatable output driver for providing a first feedback, for outputting the voltage of the first sense node to a first output node, and for receiving data, (e) a second tristatable output driver for providing a second feedback, for outputting the voltage of the second sense node to a second output node, and for receiving data, and (f) a first feedback circuit for increasing the voltage gain and decreasing the sense output response time at the first and second sense nodes and for being controlled by the first and second tristatable output drivers.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a read-only memory. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A data sensing circuit for a semiconductor memory device having complementary bit lines, including a PMOS sense amplifier connected between the complementary bit lines, an NMOS sense amplifier connected between the complementary bit lines, a bit line equalization and precharge circuit connected between the complementary bit lines, a sense amplifier equalization and precharge circuit connected between sensing control nodes of the PMOS and NMOS sense amplifiers, a plurality of first capacitors, a plurality of second capacitors, a plurality of first fuses connected between the sensing control node of the PMOS sense amplifier and respective ones of the first capacitors, a plurality of second fuses connected between the sensing control node of the NMOS sense amplifier and respective ones of the second capacitors.

Abstract: In a semiconductor circuit device comprising a differential amplifier circuit, which is formed on a semiconductor substrate and which comprises first and second input terminals, and a circuit element formed on the semiconductor substrate and connected to one of the first and the second input terminals. A dummy circuit element is formed on the semiconductor substrate so as to adjoin the circuit element for forming between the dummy circuit element and the semiconductor substrate a dummy parasitic capacitor which is equivalent to a parasitic capacitor formed between the circuit element and the semiconductor substrate. The dummy circuit element is connected to another one of the first and the second input terminals.

Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

Abstract: Positive feedback increases switching speeds and negative feedback prevents the voltage at the inputs from varying too far in a sense amplifier used to sense voltage differentials on bit lines or data lines of semiconductor memories, or elsewhere. Switching speeds improve without increased current consumption.

Abstract: An improved, differential current-mode driver circuit with low common-mode noise and high output impedance. In this circuit both sink and source currents are controlled by two pairs of emitter coupled differential amplifiers operated as current switches. One of the pairs of current switches is comprised of PNP transistors and hence slower than the other pair of current switches which is comprises of NPN transistors. The input data is applied differentially to the slower pair of the current switches and simultaneously to auxiliary switches which act as inverting amplifiers and are cross-coupled to and drive the inputs of the two faster current switches. A fifth current switch and auxiliary switch inverting amplifier is used to as an inhibit circuit to shunt both source and sink currents to ground so that no circuit node will swing excessively while holding the output nodes of the current sink and source a constant voltage thus reducing common-mode noise.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a and additional pull-up circuits to enhance high speed pair of symmetrical transfer function output inverters operation. The outputs of all of the differential latching inverters may be directly connected to a pair of OR gates with the output of one OR gate signifying that a logical ONE has been read and the output of the second OR gate signifying that a logical ZERO has been read. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.

Abstract: A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may De internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers.

Abstract: A data input register for a random access memory includes a data input line which is coupled to TRUE and COMPLEMENT outputs. A first and a second Ring Segment Buffer is connected to a respective one of the TRUE and COMPLEMENT outputs. The Ring Segment Buffer produces TRUE and COMPLEMENT binary signals at relatively fast rise time compared to the relatively slow rise time binary input signal. The Ring Segment Buffer outputs are coupled to a write control circuit for writing data into a selected memory cell of a random access memory array. The data input circuit architecture can also be used to produce relatively fast rise time TRUE and COMPLEMENT binary signals from a relatively slow rise time binary input signal for other applications.