Abstract: The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting node between these two pairs is coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS, when triggered by a CMOS input clock.

Abstract: An asymmetric switch which minimizes transistor exposure to high voltage includes one pair of P-channel transistors with both N-wells coupled back to the programming voltage source and one pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit are also included to provide complementary input voltages to the switch. The P-channel and N-channel transistors used as guard devices may be biased by the same voltage or separate voltages.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a latching sense amp circuit. The latching sense amp circuit is configured in the integrated circuit so that the signals to produce and latch an output signal consist essentially of a precharge pulse and a capture pulse.

Abstract: A low power sense amplifier for semiconductor memory devices includes: a sense-amplifying part that senses and amplifies first and second input signals from first and second input terminals, and produces first and second output signals having different voltage levels from each other via the first and second output terminals; a charging part for charging the first and second output terminals of the sense-amplifying part prior to the sensing and amplifying operation of the sense-amplifying part; a control part for producing a control signal for disabling the sense amplifying part if the sense-amplifying part produces output signals having different voltage levels from each other.

Abstract: An asymmetric sense amplifier is disclosed for use with single-ended memory arrays. The sense amplifier has a bit input, a reference input, an enable input, and bistable output circuitry. The reference input may simply be tied to V.sub.DD. The bistable output circuitry includes first and second output nodes disposed between first and second pull-up/pull-down paths, respectively. The first pull-up and pull-down paths may include first pull-up and pull-down FET channels, respectively. The second pull-up and pull-down paths may include second pull-up and pull-down FET channels, respectively. The bistable output circuitry is operable to be stable in first and second states. In both states, the output nodes are at opposite potentials. The sense amplifier is asymmetrical in the following sense: Either the second pull-down FET channel is wider than the first pull-down FET channel, or the first pull-up FET channel is wider than the second pull-up FET channel, or both.

Abstract: A method for resolving differential signals is provided which quickly and efficiently recognizes signals by resolving differences between the signals using a resolving circuit which is powered by a clock signal. The resolving circuit operates with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A sense amplifier circuit is incorporated within a computer system and utilizes a latch coupled to an equalizing transistor that operates in the triode region and initially equalizes the sense amplifier circuit data outputs, the latch subsequently develops a voltage difference in response to a control signal, deactivation of the control signal then turns off the equalizing transistor thereby allowing the latch circuit to lock the developed voltage differential to full-swing across the sense amplifier data outputs.

Abstract: An amplifier circuit that maintains high speed and reduces power consumption while operating with reduced voltages is disclosed. Broadly, the amplifier circuit of the present invention includes a set-up circuit that performs a level shift on the input signal and applies it to the inputs of a sense amplifier in a cross-coupled fashion. The circuit operates such that one leg of the precharged sense amplifier output discharges in response to the input without a counteracting charging action by the other leg of the sense amplifier output. The amplifier circuit thus operates at higher speed and with no crowbar current even with input signals of smaller magnitude.

Abstract: In a level shift circuit having a bias circuit and an output circuit, the current consumption of the bias circuit can be suppressed, and further the delay of the output signal relative to the input signal can be reduced. The ratio circuit comprises a bias circuit block (5) composed of a transistor (1) connected to a high potential power source (7) and having a gate to which an input bias INBIAS is applied through a bias input terminal (11), a transistor (2) connected in series to the transistor (1) so as to function as a resistance, and a transistor (13) connected in series to the transistor (2) and a low potential power source (8); and an output circuit block (6) composed of a transistor (3) connected to the high potential power source (7) and having a gate to which an input signal IN is applied through an input terminal (10) and a drain from which an output signal OUT is derived to an output terminal (12), and a transistor (4) connected in series to the transistor (3) and a low potential power source (8).

Abstract: A sense amplifier (10) senses data by sensing a differential current signal comprised of a current (I.sub.1) flowing in an input terminal (12) and a current (I.sub.2) flowing in a complementary input terminal (22). During the sensing process, the sense amplifier (10) generates a first current flowing in a first FET (17) in accordance with the current (I.sub.1) flowing through the input terminal (12) and a second current flowing in a second FET (27) in accordance with the current (I.sub.2) flowing through the complementary input terminal (22). Two cross coupled inverters (16, 26) compare the first current (I.sub.1) with the second current (I.sub.2) and generate a differential output voltage signal, thereby sensing the data.

Abstract: A sense amplifier having an ingegrated latch with level shift is disclosed, in which a pair of cross-connected inverters are connected between the outputs of the sense amplifier to provide a single stage amplifier. The sense amplifier performs level shift, sense amplifier and latching functions within a single circuit, thus reducing layout area and simplifying chip design while at the same time providing full swing complementary outputs. In addition, the sense amplifier is turned on for only a portion of the cycle to enable the data to be latched, with virtually no constant current comsumption in the circuit for holding the data, thereby reducing power consumption. Alternative embodiments are disclosed using conventional and tri-state latches.

Abstract: A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure which has two output nodes and which includes equalization transistor of a first polarity which equalizes the two output nodes and is connected between a first branch and a second branch, in which the output nodes are arranged; the equalization transistor is driven by an equalization signal whose slope can be modulated as a function of conductivity of a memory cell of the memory device.

Abstract: Sense amplifiers for integrated circuit memory devices including a bipolar transistor voltage gain input buffer and a first effect transistor latch circuit. The bipolar transistor voltage gain input buffer is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals. The field effect transistor latch circuit is responsive to the bipolar transistor voltage gain input buffer, to latch the voltage differential so amplified, and thereby produce a pair of complementary output signals.

Abstract: Feedback control is performed on the potential of a bit line in accordance with a change in the potential. Meanwhile, the data which has been previously read on the bit line is temporarily latched in a D-type flip-flop. A reference voltage Vref determined by a bias circuit is offset by using an offset circuit while referring to the level of the previously read data latched in the D-type flip-flop. In this manner, a bias voltage is obtained from currently read data, and based on the bias voltage, the potential of the bit line is controlled. Thus, high-speed data determining operation is achieved, which has been previously hampered when the currently read data is reversed with respect to the data read in the previous cycle.

Abstract: A level conversion circuit comprises a first CMOS circuit connected between a high voltage (5 V: VDD) power supply and ground to receive an input signal IN1 having an amplitude between a low voltage (3 V: VCC) and a ground voltage (0 V), a second CMOS circuit connected between the 5 V power supply and ground to output an output signal OUT1 having an amplitude between 5 V and 0 V, and first and second intermediate circuits cross-connected between the first and second CMOS circuits. All MOS transistors constituting these circuits have the gate oxide films whose allowable breakdown voltage is lower than 5 V and higher than 3 V.

Abstract: An improved differential source follower with negligible input/output mismatch over a wide range of input signal magnitudes. A pair of FETs and current sources provides bias current control for each differential output that cancels the inherent body-source voltage variation of the source followers which acts to attenuate the unity gain output signal.

Abstract: An asymmetric switch which minimizes transistor exposure to high voltage includes one pair of P-channel transistors with both N-wells coupled back to the programming voltage source and one pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit are also included to provide complementary input voltages to the switch. The P-channel and N-channel transistors used as guard devices may be biased by the same voltage or separate voltages.

Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

Abstract: The invention relates to a voltage control means provided with a first and a second transistor T1 and T2 constituting a differential pair, the base of the first transistor T1 being intended to receive a reference voltage Vref, the base of the second transistor T2 being intended to receive a predetermined fraction Vs of a voltage applied to a power supply terminal VDD, and also provided with a first current mirror M1 and a second current mirror M2, each having its input connected to the collector of one of the transistors and its output connected to the collector of the other transistor, the output current of each mirror being K times larger than the input current.

Abstract: A high speed current sense amplifier useful in memory devices, which includes a current-to-voltage amplifier that is coupled to a voltage amplifier. The current-to-voltage amplifier has an input impedance that is lower than its output impedance. The voltage amplifier has an input impedance that is larger than the input impedance of the current-to-voltage amplifier. The current sense amplifier can sense the current relationship between two current inputs in about 200 pico-seconds. Embodiments of the current sense amplifier enable current sensing either near the power supply voltage or near ground, thus eliminating the need for intermediate voltages. Embodiments of the current sense amplifier draw current from the current inputs only during the 200 pico-second sensing time and does not require external latching circuitry.

Abstract: A signal transmission circuit which enables the distance of signal transmission as measured by the length of the wiring electrically connecting a driver circuit and a receiver circuit of the signal transmission circuit to be increased, while the signal delay and power consumption are reduced. The signal transmission circuit includes the driver circuit, the receiver circuit, an equalizer circuit that flattens the output of the driver circuit, and an intermediate amplifier circuit. The intermediate amplifier circuit is connected to input/output shared terminals in the wiring that connects the driver circuit and the receiver circuit. With the aid of the positive feedback of the intermediate amplifier circuit, a differential signal output from the driver circuit is amplified and then transmitted to the receiver circuit.

Abstract: An improved output circuit that provides an output signal having a predetermined high voltage level regardless of the voltage of a high-potential power supply is described. In one embodiment, the invention includes a first transistor and a second transistor connected in series between a high-potential power supply and a low-potential power supply, and a third transistor connected in parallel to the first transistor between the high-potential power supply and the node between the first and second transistors. The first and second transistors are n-type MOS transistors and the third transistor is a p-type MOS transistor. In another embodiment, the invention further includes a supply voltage detector for detecting a voltage of the high-potential power supply and supplying a voltage signal to the first and third transistors for selectively enabling one of the first and third transistors based on the voltage detected.

Abstract: A current differential amplifier circuit comprises first and second pMOS transistors (P11 and P12) connected between a power supply and a first node (W11 ); third and fourth pMOS transistors (P13 and P14) connected between the power supply and a second node (W12); a fifth pMOS transistor (P15) connected between gates of the second and the third pMOS transistors (P12 and P13), each of the gates connected to its opposite node (W11 or W12 ); a first nMOS transistor (N16) connected between the first node (W11 ) and a first current source (I11 ) and having its gate connected to the second node (W12); and a second nMOS transistor (N17) connected between the second node (W12) and a second current source (I12) and having its gate connected to the first node (W11). Pre-charge signal (/PC) is applied to the gates of the first, fourth and the fifth pMOS transistors (P11, P14 and P15) and comparison results are derived from either the first node (W11) or the second node (W12).

Abstract: A current mode driver capable of driving both 10 Base-T signalling and 100 Base-T signalling in a Local Area Network (LAN) includes two or four current sources. In a first embodiment, a differential signal generator drives four current sources. The generator outputs four signals, one of which is received by each current source. Using these signals, two of the current sources push or pull current across the load in one direction, while the other two current sources push or pull current across the load in the other direction, such that a full differential signal is generated across the load. In another embodiment, a signal generator drives two current sources which drive into the load one at a time. Two switches provide either high resistance or low resistance during half of a signal cycle such that current is pulled through the load in one direction, and prevented from flowing through the load in the other direction.

Abstract: A fast data transmission circuit for a semiconductor memory minimizes voltage variations of a data transmission line without the use of a separate data transmission voltage. The data transmission circuit includes a pair of input nodes, a data transmission line pair, a pair of sensing nodes, a pair of output nodes, and a control electrode. Prior to data transmission, the output nodes are pulled up to a high voltage state, the data transmission line pair is pulled down to a low voltage state, and the sensing nodes are held between the high and low voltage states. When the control pulse is applied to the control electrode, the sensing node voltage levels are transferred to the data transmission line pair by the sensing voltage transfer circuit. When one input node is pulled to a low voltage state, a corresponding one voltage level on one transmission line is changed, causing a corresponding change of voltage at one of the sensing nodes.

Abstract: A signal transfer circuit for enabling rapids transfer of differential electrical signals among multiple signal paths is provided. The circuit comprises first and second pairs of signal transfer terminals, a pair of internal nodes, first and second pairs of isolation devices, a differential signal amplifier, a gain-enhancing cross-coupled pair of devices, and a precharge circuit. The first and second pairs of isolation devices are of a single device type and are coupled between respective ones of the signal transfer terminal pairs and the internal node pair. The isolation devices each have a control terminal for receiving an isolation control signal. The differential signal amplifier circuit is coupled to the internal nodes, and is comprised of complementary device types. The amplifier circuit has a control terminal for receiving an amplifier control signal for enabling the amplifier circuit.

Abstract: A sense amplifier of a semiconductor memory device which increases a voltage difference between a bit line and a dummy line is disclosed. The sense amplifier includes: a sense amplifying unit which pre-charges voltages of a dummy line connected to a dummy cell and of a bit line connected to a memory cell by a first equalizing signal, and which senses and amplifies data from the memory cell by inputting the voltages of the dummy line and the bit line by a sense amplifier enable signal; and a voltage variable unit which adjusts the voltages of the dummy line and the bit line by a second equalizing signal, said voltage variable unit having a first voltage variable part which adjusts the voltage of the dummy line by the second equalizing signal and a second voltage variable part which adjusts the voltage of the bit line by the second equalizing signal.

Abstract: A sense amplifier has a pair of output terminals and a first pair of pull-up transistors. A second pair of transistors is connected between the output terminals and a pull-down node. The gate electrodes of the second pair are cross-coupled to the output terminals. A third pair of transistors is connected between the output terminals and the pull-down node and have gate electrodes coupled to input potentials. A fourth pair of transistors is connected between the output terminals and the pull-down node and also have gate electrodes coupled to input potentials.

Abstract: A recording apparatus including a magnetic write head and a write amplifier with capacitive current compensation. The write amplifier is made up of four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through the write head. The parasitic capacitances across the write head and/or the parasitic capacitances of the write amplifier at the write terminals are neutralized by means of neutralizing capacitors. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit.

Abstract: The present invention provides a sense amplifier with high speed and stable sensing capabilities under a low supplying voltage. In accordance with the present invention, there is disclosed a sense amplifier comprising: a voltage level shifter for shifting a voltage level of data from a memory cell in response to a sense amplifier enable signal; a current mirror type sense amplifying stage for amplifying the level-shifted data from the voltage level shifter to full range in response to the sense amplifier enable signal; and a driver means for driving the amplified data from the current mirror type sense amplifying stage.

Abstract: To read out a data bit stored in a memory cell including a programmable resistor memory element, a first voltage is developed on a first sense node due to initiation of current flow through the memory element and a second voltage is developed on a second sense node due to current flow through a reference resistor. The first and second voltages are separately detected to generate a trip signal in response to a leading edge of either of the first and second voltages achieving a threshold level. A flip-flop circuit is conditioned by the trip signal to produce opposite logic signal voltages on the first and second sense nodes indicative of the binary value of the stored data bit.

Abstract: The present invention provides a sense amplifier in a semiconductor device, comprising a detector for enabling the sense amplifier in response to the output thereof and disabling the sense amplifier in response to the increase of the output thereof, whereby the detecting means disables the sense amplifier when the output voltage from the sense amplifier increases up to a predetermined voltage level. The sense amplifier prevent data error from being generated and decrease power consumption by using the outputs thereof when the outputs thereof increases to a constant level.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: The comparator circuit comprises a first comparator circuit having a differential input stage composed of P-channel FETs; a second comparator circuit having a differential input stage composed of N-channel FETs; pull-up and pull-down resistances connected to the output terminals of the two comparator circuits, respectively; at least one skew adjusting circuit having a delay circuit and a selector; and a logical gate for obtaining the two output signals of the two comparator circuits. Since the two differential input signals can be received by the two comparator circuits and according to the potentials of the two differential input signals, even if the supply potential is low, the comparator circuit can compare the two differential input signals in a wide potential range from the ground potential and the supply potential, so that it is possible to provide a high speed interface circuit which can satisfy the LVDS standard at a low supply potential.

Abstract: A data value is passed from a bus (50) to a receiver (40) without a propagation delay. A data latch (10) stores the data value while the data value is being generated by the bus (50). The data latch (10) then holds the data value and provides the data value to the receiver (40) after the data value is no longer present on the bus (50). The data latch (10) has a data storage circuit (11), a diode clamping circuit (12), and a current sourcing circuit (13). The data value is stored by the data storage circuit (11) by a feed-back loop circuit.

Abstract: A circuit for a low voltage sense amplifier obtains a faster test time in designing a circuit because a conventional sense amplifier adopting voltage 3.3V can be applied to a semiconductor memory device requiring a potential of less than 1.0V, and prevents current leakage at a low threshold voltage by providing source voltage to a sense amplifier of a selected memory cell array in an active mode as well as in a standby mode.

Abstract: The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.

Abstract: A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

Abstract: An evaluation and amplifier circuit of the type of a keyed flipflop including at least two first transistors of a given channel type connected in series to each other disposed between first and second signal lines, has a connection from the gates of the first transistors to a respective one of the second and first signal lines. The first two transistors respectively form a first node common to the first two transistors for receiving a first control signal. A series circuit has at least two second transistors of the same channel type as the first transistors being connected in parallel to the first transistors, The gates of the first transistors are further connected with a respective one of the second and first signal lines.

Abstract: A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: Small voltage changes on a highly capacitive signal are sensed rapidly by placing a shielding impedance between the signal to be sensed and the input to a regenerative sense circuit. A regenerative sense circuit has a sense amplifier which controls a switching means that is connected to the input to the sense amplifier. When the output of the sense amplifier reaches a threshold value, it turns the switching means on. This switching means increases the rate of change on the input to the sense amplifier which causes the switching means to turn on even more. The input and output of the sense amplifier are able to switch more rapidly because the shielding impedance allows the switching means to change the state of the input to the sense amplifier without having to completely change the voltage level on the highly capacitive input signal. A small voltage difference between two signals is sensed by two cross-coupled, actively loaded, NMOS inverters.

Abstract: P channel MOS transistors P11 and P12 have their gates cross-connected to their drains. P channel MOS transistors P13 and P14 each having its gate and its drain diode-connected to each other are respectively connected in parallel to transistors P11 and P12. N channel MOS transistors N15 and N16 drive transistors P11 to P14 with current values corresponding to input signals IN and /IN. If transistors P11-P14 have the same gate length, transistors P11 and P12 have the same gate width, and transistors P13 and P14 have the same gate width, the DC amplification factor of an internal differential amplifying circuit 1100 of a first stage can be set to a desired value by the ratio of a gate width of P13 to a gate width of P11. Internal outputs from nodes to which the drains of P11 and P12 are respectively connected are input to an internal differential amplifying circuit 1200 of the following stage.

Abstract: A semiconductor memory device includes a memory cell, a word line, a bit line pair having a first bit line and a second bit line complementary to the first bit line, a p type well, first and second source lines, a source line precharge circuit for precharging the first and second source lines, a sense amplifier connected between the first and second bit lines, driven by the first and second source lines and including first and second n channel MOS transistors formed in the p type well and third and fourth p channel MOS transistors, a first sense amplifier enable transistor connected between a power supply potential node and the first source line, a second sense amplifier enable transistor connected between a ground potential node and the second source line, and a switching circuit connected between the first source line and the p type well, and turning on in response to a control signal when the sense amplifier is active.

Abstract: An apparatus for recording on a magnetic record carrier includes a write amplifier comprising four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through a write head. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit. The symmetrical structure further enables the parasitic capacitances at the write terminals to be neutralized by means of neutralizing capacitors.

Abstract: An integrated circuit pattern of a sense amplifier is disclosed. The sense amplifier includes a sense circuit connected to a memory array and a column gate. The sense circuit includes N-MOSFETs cross-coupled between paired bit lines. The column gate includes an N-MOSFET for connecting the bit line to a data line and an N-MOSFET for connecting the other bit line to another data line. The N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in one element region. Further, the N-MOSFET contained in the sense circuit and the N-MOSFET contained in the column gate are integrated in another element region.

Abstract: A negative power supply circuit is connected via an NMOS transistor to a node receiving ground potential in a sense amplifier. A one shot pulse generation circuit provides a one shot pulse signal to the gate of the NMOS transistor. The NMOS transistor is turned on when a one shot pulse signal is applied to connect the negative power supply circuit to the node. This causes the potential of the node to be lowered to a negative potential. As a result, increase in the potential at the ground side of the sense amplifier caused by an interconnection resistance in the ground interconnection is suppressed. Therefore, variation in the potential received by the sense amplifier due to interconnection resistance can be suppressed.

Abstract: A current sense amplifier for use in a semiconductor memory device having a pair of sub-I/O lines and a pair of I/O lines includes a first circuit leg having a first PMOS transistor in series with a second NMOS transistor. A second circuit leg has a third PMOS transistor in series with a fourth NMOS transistor. The gates of the PMOS transistors are each cross coupled to the drain of the other PMOS transistor. The gates of the NMOS transistor are each cross coupled to the source of the PMOS transistor in the other circuit leg. The source of each PMOS transistor comprises a sub-Input/Output line with an Input/Output line located between the transistors in each of the legs.

Abstract: In a voltage-level shifter, a P-channel MOS transistor (early cut-off circuit) is interposed between a voltage source of the voltage-level shifter and a source of a P-channel MOS transistor which tends to be turned on when a voltage of a voltage source of an input signal supplies a low voltage or a large potential difference exists between the voltage source of the input signal and the voltage source of the voltage-level shifter, and is supplied on its gate with the input signal of the voltage-level shifter. Accordingly, the interposed P-channel MOS transistor is turned off prior to the P-channel MOS transistor having a tendency of being turned on, so that the voltage level of the output signal of the voltage-level shifter can be rapidly fixed at the "L" level.