Abstract: One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

Abstract: A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor.

Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.

Abstract: A non-insulated DC-DC converter has a power MOS•FET for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.

Abstract: There is provided a high frequency semiconductor switch having an FET designed in consideration of characteristics required for a transmission terminal and a reception terminal. The high frequency semiconductor switch includes a plurality of field effect transistors that each include a source region and a drain region formed on a substrate to be spaced apart by a predetermined distance, a gate formed on the substrate to be disposed at the predetermined distance, a source contact formed on the substrate to be connected with the source region, and a drain contact formed on the substrate to be connected with the drain region. A distance between a source contact and a drain contact of a reception terminal side transistor is longer than a distance between a source contact and a drain contact of a transmission terminal side transistor.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: A layout for a semiconductor integrated circuit device can maintain a sufficient capacitance of a capacity cell even when a height of the cell is lowered. In this layout, power supply wiring extending along a first direction supplies a first supply voltage, power supply wiring and power supply wiring extending in parallel with the power-supply wiring supply a second and a third supply voltages respectively. Capacitive element is formed of a transistor that receives the first supply voltage at its source and drain, and receives the second or the third supply voltages at its gate. Capacitive element is disposed under power supply wiring such that it strides over a portion at power supply wiring side and a portion at power supply wiring side.

Abstract: An integrated circuit includes an analog circuit including a first transistor. At least one cascode transistor is electrically coupled with the first transistor in a series fashion. A drain and a gate of the cascode transistor are electrically coupled with a gate of the first transistor of the analog circuit. The at least one cascode transistor is operated in a saturation mode or a sub-threshold mode.

Abstract: A control circuit, which controls a transistor including a gate and a field plate, includes: a detecting circuit which detects a driving timing to drive the transistor; a timing controlling circuit which controls a first driving timing to drive the gate and a second driving timing to drive the field plate, in response to the driving timing; and a driving circuit which drives the gate in response to the first driving timing, and drives the field plate in response to the second driving timing.

Abstract: Disclosed herein are various methods and circuits for achieving rational fractional drive strengths in circuits employing FinFET devices. In one example, the device disclosed herein includes a semiconducting substrate, a first plurality of FinFET transistors formed in and above the substrate, wherein each of the first plurality of FinFET transistors is adapted to produce an individual drive current, and wherein the first plurality of FinFET transistors are configured in a series circuit. The drive current resulting from the series circuit is a rational fraction of the individual drive current.

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Abstract: There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

Abstract: A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type ca

Abstract: An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Abstract: A field effect transistor (FET) including a monolithically integrated gate control circuit element can be included in, for example, a radio frequency switch circuit. For example, the FET can be included as a series and/or shunt FET of a radio frequency coplanar waveguide circuit. The widths of the series and shunt FETs of a switch circuit can be selected to provide a target isolation and/or a target insertion loss for a target operating frequency.

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

Abstract: A semiconductor integrated circuit according to an embodiment includes a transfer transistor including a first gate electrode, the first gate electrode and a diffusion layer being diode-connected with a first wiring, and a clock signal line to which a clock signal is supplied, at least a portion of a first partial clock signal line, which is a portion of the clock signal line, being formed above the first gate electrode.

Abstract: An integrated circuit includes a bypass signal path exchanging, between transceivers which are included in the integrated circuit, a signal transmitted/received between a transceiver of the transceivers and an internal logic circuit which processes data being input/output by transceiver with bypassing the internal logic circuit, a switch switching a pathway of the bypass signal path, and a switch changeover controller transferring a switch control signal that performs a changeover of the switch.

Abstract: In a display device using a light-emitting element or the like, the power consumption is reduced without reducing the display quality. A first operation and a second operation are carried out. In the first operation, a threshold voltage of a transistor is held in a capacitor. In the second operation, a signal potential corresponding to an image signal and the threshold voltage are added with the use of a capacitive coupling by the capacitor and are input to a gate of the transistor, so that a drain current of the transistor flows into a load element. The first operation is carried out once in a plurality of frames. A switch that determines whether the capacitor is electrically connected to a wiring to which a power supply potential is input is provided. A transistor in which a channel is formed in an oxide semiconductor layer is used as the switch.

Abstract: An apparatus comprises at least one input connection, at least one output connection, at least one control connection, a voltage converter circuit having an input coupled to the control connection and an output, wherein the voltage converter circuit is configured to provide a voltage at its output that is greater than a voltage present at its input, and at least one switch circuit coupled to the input connection, the output connection, and the output of the voltage converter circuit. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by the voltage converter output. Power to the voltage converter circuit is provided via the control connection, and power to the switch circuit is provided via the output of the voltage converter circuit.

Abstract: To provide a protection circuit having a small area, redundancy, and small leak current. In the protection circuit, a plurality of nonlinear elements is provided so as to overlap with each other and so as to be electrically connected in series. At least one nonlinear element in the protection circuit is a diode-connected transistor including an oxide semiconductor in its channel formation region. The other nonlinear element is a diode-connected transistor including silicon in its channel formation region or a diode including silicon in its junction region.

Abstract: An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.

Abstract: A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.

Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

Abstract: An apparatus comprises at least one input connection, at least one output connection, and at least one control connection, and at least one switch circuit coupled to the input, the output, and the control connections. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by a control signal received at the control connection. Power to the switch circuit is provided via the control connection.

Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.

Abstract: A power switch includes a first power transistor having a first source electrode, a first gate electrode, and a first drain electrode, and a second power transistor having a second source electrode, a second gate electrode, and a second drain electrode. The power switch further includes a first pilot transistor which has a third source electrode, a third gate electrode, and a third drain electrode. The first, second and third drain electrodes are electrically connected together. The first and second source electrodes are electrically connected together. The first and third gate electrodes are electrically connected together and can be biased independently from the second gate electrode. The first power transistor is the same size as or smaller than the second power transistor and the first power transistor is larger than the first pilot transistor.

Abstract: A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.

Abstract: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.

Abstract: A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations.

Abstract: A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

Abstract: A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised.

Abstract: In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.

Abstract: An integrated circuit includes a transfer unit configured to transfer an input signal having a first swing width between a first voltage and a second voltage, a driving unit configured to drive an output terminal to output an output signal having a second swing width in response to the input signal transferred from the transfer unit, and a control unit configured to control the driving unit in response to the output signal.

Abstract: An integrated circuit includes a first pass gate and a first receiver electrically coupled with the first pass gate. The first receiver includes a first N-type transistor. A first gate of the first N-type transistor is electrically coupled with the first pass gate. A first P-type bulk of the first N-type transistor is surrounded by a first N-type doped region. The first N-type doped region is surrounded by a first N-type well. The first N-type doped region has a dopant concentration higher than that of the first N-type well.

Abstract: A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.

Abstract: In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly.

Abstract: Apparatus and methods for an integrated circuit, high-impedance network are provided. In an example, the network can include an anti-parallel diode pair coupled between first and second nodes. The anti-parallel diode pair can include a first diode including a P+/NWELL junction and a second diode including N+/PWELL junction. In an example, the first diode and the second diode can include a common substrate.

Abstract: A digitally controlled variable capacitance integrated electronic circuit module (100) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block (11) which can be switched between two individual capacitance values, a control block (12), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions (110, 120) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

Abstract: An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

Abstract: An object of this invention is to provide a semiconductor device (an RFID) with reduced loss of voltage/current corresponding to a threshold value of a transistor, and having a voltage/current rectification property. Another object of this invention is to simplify a fabrication process and a circuit configuration. A rectifier circuit is provided in an element included in a semiconductor device (RFID) capable of communicating data wirelessly. As compared to the case where only a diode is provided, coils are provided between gate terminals and drain terminals of transistors constituting the diode in a rectifier circuit, so that the coils overlap an antenna which receives a radio wave, whereby a voltage output by the rectifier circuit is increased using electromagnetic coupling between the antenna which receives a radio wave and the coils, so that the rectification efficiency is improved.