Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads.

Abstract: According to one embodiment, a semiconductor device provided with an input terminal and a resistor circuit is presented. The resistor circuit is provided with first and second transistors, a first resistor, a capacitor and a capacitor. A drain of the first transistor is connected to the input terminal. One end of the first resistor is connected to a gate of the first transistor. A drain of the second transistor is connected to a source of the first transistor. A gate of the second transistor is connected to the other end of the first resistor. A source of the second transistor is connected to a power supply of a source side. The capacitor is connected between the drain and the gate of the first transistor. The voltage supply circuit is connected to the other end of the first resistor and the gate of the second transistor.

Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.

Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

Abstract: An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received.

Abstract: An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.

Abstract: The present invention provides a data latch circuit which can operate stably with a low-amplitude signal, which consumes less electric power, and which is resistant against the variation in TFTs. When an analog switch is turned on, a data signal is inputted to a gate electrode of an n-channel TFT and, at this time, VDD is supplied to an input terminal of an inverter. When the analog switch in turned off, the n-channel TFT is turned on or off depending on a level of the data signal. When the data signal is at an H level, the n-channel TFT is turned on and VSS is supplied to the input terminal of the inverter. When the data signal is at an L level, VDD is supplied to an input terminal of the inverter. Therefore, only VDD and VSS levels are applied to the input terminal of the inverter.

Abstract: A quantum interference transistor may include a source; a drain; N channels (N?2), between the source and the drain, and having N?1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

Abstract: Embodiments relate generally to voltage converter structures including a diffused metal oxide semiconductor (DMOS) field effect transistors (FET). Embodiments include the combination of DMOS devices (e.g., FETs with isolated bodies from the substrate) with Schottky diodes on a single semiconductor die. The Schottky diode can be integrated into a cell of a DMOS device by forming an N-type area in the P-body region of the DMOS device.

Abstract: An analog switch configuration includes a gate control circuit coupled between an input of a switch and a gate of the switch. The gate control circuit passes voltage changes on the input of the switch to the gate of the switch to decrease the influence the inherent gate to input capacitance has on the bandwidth of the switch. By reducing the change in voltage across the inherent capacitance, the current through the capacitance in decreased as well as its influence on the bandwidth of the configuration.

Abstract: A semiconductor device is provided in which a transistor which supplies a current to a load (an EL pixel and a signal line) can supply an accurate current without being affected by a variation. A voltage of each terminal of a transistor is controlled by using a feedback circuit using an amplifier circuit. A current Idata is inputted from a current source circuit to a transistor and a gate-source voltage (a source potential) required for the transistor to flow the current Idata is set by using the feedback circuit. The feedback circuit is controlled to operate so that a drain potential of the transistor becomes a predetermined potential. Then, a gate voltage required to flow the current Idata is set. By using the set transistor, an accurate current can be supplied to the load (an EL element and a signal line). As a drain potential can be controlled, the kink effect can be reduced.

Abstract: According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.

Abstract: A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt1, and the gate electrode and the second dielectric layer form a third gate having a threshold voltage Vt2 different than Vt1.

Abstract: Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109).

Abstract: A traveling wave device employs an active Gallium Nitride FET. The Gallium Nitride FET has a plurality of gate feeding fingers connecting to an input gate transmission line. The FET has a drain electrode connected to an output drain transmission line with the source electrode connected to a point of reference potential. The input and output transmission lines are terminated with terminating impedances which are not matched to the gate and drain transmission lines. The use of Gallium Nitride enables the terminating impedance to be at much higher levels than in the prior art. The use of Gallium Nitride permits multiple devices to be employed, thus resulting in higher gain amplifiers with higher voltage operation and higher frequency operation. A cascode traveling wave amplifier employing GaN FETs is also described having high gain and bandwidth.

Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.

Abstract: This invention concerns interfacing to electronic circuits or systems operating at low temperature or ultra-low temperature using complementary metal-oxide semiconductor (CMOS) technology. Low temperature in this case refers to cryogenic temperatures in particular, but not exclusively, to the 4.2 K region. Ultra-low temperatures here refers to the sub-1 K range, usually accessed using dilution refrigerator systems. The electronic circuits comprise a controller (for writing and manipulation), an observer (for readout and measurement) circuits, or both, fabricated from ultra-thin silicon-on-insulator (SOI) CMOS technology.

Abstract: Signals are coupled to and from stacked semiconductor dies through first and second sets of external terminals. The external terminals in the second set are connected to respective conductive paths extending through each of the dies. Signals are coupled to and from the first die through the first set of external terminals. Signals are also coupled to and from the second die through the conductive paths in the first die and the second set of external terminals. The external terminals in first and second sets of each of a plurality of pairs are connected to an electrical circuit through respective multiplexers. The multiplexers in each of the dies are controlled by respective control circuits that sense whether a die in the first set is active. The multiplexers connect the external terminals in either the first set or the second set depending on whether the bonding pad in the first set is active.

Abstract: A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.

Abstract: A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.

Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.

Abstract: A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which the device of the multiple devices forming the first current mirror is disposed on the substrate; a second current mirror having a second current, formed of multiple devices disposed on the substrate, where, when the stress is present, a behavior of a device of the multiple devices forming the second current mirror depends on a direction in which the device of the multiple devices forming the second current mirror is disposed on the substrate; and a device for measuring a ratio of a difference between the first current and the second current to a sum of the first current and the second current.

Abstract: In one embodiment, a sensing circuit includes a sense transistor and a compensation circuit to improve the accuracy of a sensing signal formed by the sensing circuit.

Abstract: In the present invention, a decoupling capacitance circuit, a first output terminal and a second output terminal are provided. The decoupling capacitance circuit comprises a TDDB control circuit consisting of a first Tr and a second Tr, and a third Tr. Conductivity types of the first and second Trs are different from each other. A source of the first Tr is connected to a first power supply wiring, and a drain of the first Tr is connected to a gate of the second Tr. A source of the second Tr is connected to a second power supply wiring, and a drain of the second Tr is connected to a gate of the first Tr. The third and first Trs have the same conductivity type. A source and a drain of the third Tr are connected to the first power supply wiring, and a gate of the third Tr is connected to the drain of the second Tr. The first output terminal is connected to the drain of the first Tr, and the second output terminal is connected to the drain of the second Tr.

Abstract: Signals are coupled to and from stacked semiconductor dies through first and second sets of external terminals. The external terminals in the second set are connected to respective conductive paths extending through each of the dies. Signals are coupled to and from the first die through the first set of external terminals. Signals are also coupled to and from the second die through the conductive paths in the first die and the second set of external terminals. The external terminals in first and second sets of each of a plurality of pairs are connected to an electrical circuit through respective multiplexers. The multiplexers in each of the dies are controlled by respective control circuits that sense whether a die in the first set is active. The multiplexers connect the external terminals in either the first set or the second set depending on whether the bonding pad in the first set is active.

Abstract: Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide hand-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.

Abstract: A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.

Abstract: A system for reducing noise in a chip is disclosed and may include a substrate, a first well disposed on top of the substrate, a second well and a third well that are both disposed within the first well, a first transistor disposed in the second well, a positive potential of a voltage source connected to a body of the first transistor, and a second transistor disposed in the third well. The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well. The system may include a noisy voltage source, where a body and a source of the second transistor are both coupled to the noisy voltage source.

Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

Abstract: A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.

Abstract: The present invention describes systems and methods to for providing stable and programmable voltage and current reference devices. An exemplary embodiment of the present invention provides a voltage reference device having a first floating-gate transistor with a first source, a first drain, and a first gate. The first gate is provided coupled to a first programming capacitor and a first input capacitor. Furthermore, the voltage reference device includes a second floating-gate transistor having a second source, a second drain, and a second gate. The second gate is provided coupled to a second programming capacitor and a second input capacitor. Additionally, the charge difference between the first floating-gate transistor and the second floating-gate transistor is a reference voltage.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.

Abstract: An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die.

Abstract: The present invention provides a semiconductor integrated circuit capable of achieving high voltage. The proposed semiconductor integrated circuit includes a first node [VOUT] connected to a first potential node [VDD], and a first n-channel transistor [NT1] and a second n-channel transistor [NT2] serially connected between a first node [VOUT] and a second potential node [VSS] of a lower potential than the first potential node. One end of NT1 is connected to the second potential node [VSS], the other end thereof is connected to one end of the second n-channel transistor [NT2], a gate terminal thereof is connected to a second node [VIN], the other end of NT2 is connected to the first node [VOUT], and a gate terminal thereof is connected to a first intermediate range potential [VM1] positioned between the first potential node [VDD] and the second potential node [VSS].

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

Abstract: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.

Abstract: A readout circuit for reading from addressable nodes comprises first and second half-circuits of a differential amplifier. The first half-circuit comprises at least one source follower transistor adapted to receive an input signal from one of the addressable nodes, such as pixel readouts of an imaging system. The first half-circuit further comprises a row selector switch coupled to the source follower transistor to selectively activate the source follower transistor to receive the input signal. The second half-circuit comprises an output node for providing an output signal of a readout of a selected addressable node. The second half-circuit further comprises a source leader transistor coupled to the output node to provide a feedback signal based on the readout. A feedback loop is connected to the source leader transistor to provide feedback from the output node for utilization in a differential amplification of the input signal.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which the device of the multiple devices forming the first current mirror is disposed on the substrate; a second current mirror having a second current, formed of multiple devices disposed on the substrate, where, when the stress is present, a behavior of a device of the multiple devices forming the second current mirror depends on a direction in which the device of the multiple devices forming the second current mirror is disposed on the substrate; and a device for measuring a ratio of a difference between the first current and the second current to a sum of the first current and the second current.

Abstract: The semiconductor device of the present invention has a circuit block in which m (m is an integer of not smaller than two) sets of first through m-th transistor columns where two or more transistors are connected in series, one terminal of the first through m-th transistor columns is connected to a first output node, and the other terminal of the first through m-th transistor columns is connected to a second output node. A control signal for substantially simultaneously turning on and off all the transistors of the first through m-th transistor columns is inputted to the control input terminals of the transistors of the first through m-th transistor columns.

Abstract: A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

Abstract: A semiconductor device of the invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage lower than the power supply voltage, a ground voltage and a sub-ground voltage higher than the ground voltage are supplied; a main power supply line supplying the power supply voltage; and a main ground line supplying the ground voltage. A unit circuit constituting the logic circuit includes first to third PMOS transistors and first to third PMOS transistors. The third PMOS transistor is connected between sources of the first and second PMOS transistors, the main power supply line is connected to its one node, and the sub-power supply voltage is generated at its other node. The third NMOS transistor is connected between sources of the first and second NMOS transistors, the main ground line is connected to its one node, and the sub-ground voltage is generated at its other node.

Abstract: An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.

Abstract: A computer system includes a substrate on which a first current mirror and a second current mirror are disposed. When a stress is present, a behavior, e.g., carrier mobility, of at least one of the devices in each of the first current mirror and the second current mirror is dependent on a direction in which that device is disposed on the substrate. Further, one of the devices in the first current mirror is disposed in a non-parallel orientation with respect to one of the devices in the second current mirror.

Abstract: A current-limiting circuit for limiting rising of a current above a predetermined level. The circuit including forward- and reverse-conducting devices, each device including a MOS and a bipolar transistor, wherein ON-resistance of one of the devices is used instead of a current-sensing resistance for another of the devices; and a gate driver connected to the gates of the forward- and reverse-conducting devices for controlling the devices such that a channel of each of the devices simultaneously conducts a current.