Abstract: A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit 3, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit 3 are electrically connected by a bonding wire.

Abstract: A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.

Abstract: A driver package includes an integrated circuit (IC) comprising pull up circuitry capable of turning ON an associated switch and pull down circuitry capable of turning OFF the associated switch. The pull up circuitry may be coupled to a first bonding pad of the IC, and the pull down circuitry may be coupled to a second bonding pad of the IC. The driver package may further comprise a first conductive path coupled between the first bonding pad and a package pin of the driver package, where the package pin is coupled to the associated switch, and a second conductive path coupled between the second bonding pad and the package pin. The first conductive path may further provide a sensed signal representative of state of the associated switch to break before make control circuitry to assist in minimizing a break before make delay time interval.

Abstract: The invention provides a semiconductor integrated circuit of which malfunction caused by noise from outside is reduced. The semiconductor integrated circuit has a power supply terminal, a ground terminal, internal circuits supplied with a power supply potential and a ground potential from the power supply terminal and the ground terminal, output circuits, an exclusive ground wiring extending from the ground terminal, a first capacitor connected between the exclusive ground wiring and a power supply wiring, an exclusive power supply wiring extending from the power supply terminal, and a second capacitor connected between the exclusive power supply wiring and a ground wiring.

Abstract: An embodiment of the present invention is directed to a method of matching time-multiplexed resistors to a known ratio including generating a control signal from a control circuit, which includes a value that defines a configuration. The method also includes receiving the control signal at a switching circuit, detecting whether the value of the control signal has changed, and, provided the value has changed, switching a plurality of resistors from a first configuration to a second configuration. The first configuration produces a first resistance, and the second configuration produces a second resistance. The ratio of the first resistance and the second resistance are the aforementioned known ratio.

Abstract: A signal processing circuit comprising one or more ion sensitive field effect transistors, ISFETs, and a biasing circuit for biasing the or each ion sensitive field effect transistor to operate in the weak inversion region.

Abstract: On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Abstract: The invention provides a semiconductor device that power is stabilized by suppressing power consumption as much as possible. The semiconductor device of the invention includes a logic portion and a memory portion each including a plurality of transistors, a detecting portion for detecting one or both of operation frequencies of the logic portion and the memory portion, a Vth control for supplying a Vth control signal to one or both of the logic portion and the memory portion, and an antenna. Each of the plurality of transistors has a first gate electrode which is input with a logic signal, a second gate electrode which is input with the Vth control signal, and a semiconductor film such that the second gate electrode, the semiconductor film, and the first gate electrode are provided in this order from the bottom.

Abstract: An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N-MOS bypass transistor is coupled between the power output node and a reference node of the integrated circuit device. The gate driver circuit responds to a pulse-width-modulated (PWM) control signal by outputting an active-low drive-enable signal to a gate terminal of the P-MOS power transistor and an active-high bypass-enable signal to a gate terminal of the N-MOS bypass transistor during respective, non-overlapping intervals.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: A semiconductor integrated circuit according to an example of the present invention includes a semiconductor substrate, an element isolation insulating layer formed in a surface region of the semiconductor substrate, and first and second MIS type devices isolated from each other by the element isolation insulating layer and formed in adjacent first and second element regions in a second direction orthogonal to a first direction. Each of the first and second MIS type devices has a stack gate structure having a floating gate and a control gate electrode. The first MIS type device functions as an aging device, and the second MIS type device functions as a control device which controls an electric charge retention characteristic of the aging device.

Abstract: The invention relates to a current regulator having the following features: a first semiconductor body (1; 1?) having a first and second terminal contact (11, 12), a transistor (T) having a control terminal and a load path, which is integrated in the semiconductor body (1; 1?) and the load path of which runs between the terminal contacts (11, 12) of the semiconductor body, a current measuring resistor (22), which is at least partly formed by a section of the load path of the transistor, an evaluation and drive circuit (3), which is connected to the current measuring resistor (22) and which is designed to drive the transistor depending on a voltage across the measuring resistor (22).

Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.

Abstract: A semiconductor device has first, second, and third connecting leads (1, 2, 3), whose respective base points (1f, 2f, 3f) have centroids (1m, 2m, 3m). The connecting leads are arranged wherein an angle (?) between a first line drawn between the centroids (1m, 3m) of the base points (1f, 3f) of first lead (1) and third lead (3) and a second line drawn between the centroids (2m, 3m) of the base points (2f, 3f) of second lead (2) and third lead (3) is 20° maximum. In addition, a semiconductor module may incorporate two or more semiconductor devices which are connected electrically in parallel.

Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.

Abstract: A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.

Abstract: A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.

Abstract: A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, each with a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor communicates with the first terminal of the second transistor. The control terminals of the third and fourth transistors communicate with the second terminals of the first and second transistors, respectively. The first terminals of the third and fourth transistors communicate with the control terminals of the first and second transistors, respectively. First ends of first and second capacitances communicate with the second terminals of the first and second transistors, respectively. Second ends of the first and second capacitances communicate with the control terminals of the first and second transistors, respectively.

Abstract: A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i.e. it is programmed. Over time, the charge storage element then loses the electrostatic charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the electric potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell is able to measure an elapsed time period without a continuous power source.

Abstract: This invention provides a circuit and a method for generating a low-level current using semiconductor charge pumping. The invention provides a means of generating a range of current sources by varying the frequency of a repetitive voltage pulse input signal. Also, this invention utilizes one or many MOSFET devices in order to produce higher levels of current. The current source embodiments of this invention generate very stable current sources with high input impedances.

Abstract: The semiconductor booster circuit includes a plurality of stages, each of which has a MOS transistor and two capacitors. The MOS transistor, having a drain, a source and a gate, is formed in a well of a substrate portion. One capacitor has a terminal connected to the drain of the MOS transistor, while the other capacitor has a terminal connected to the gate of the MOS transistor. A first clock signal generating means generate a first clock signal via another terminal of one capacitor. A second clock signal generating mean s generate a second clock signal, with a larger amplitude than a power supply voltage, via another terminal of another capacitor. The plurality of stages are cascaded together, and in each of the stages the source of the MOS transistor is electrically connected to the well in which the transistor is formed, while the wells are electrically insulated from each other.

Abstract: An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

Abstract: A high voltage generator (GHT) incorporated in an integrated circuit (IC) and comprising a charge pump (1) whose input voltage is the supply voltage (VDD) of the integrated circuit (IC) and which is clocked by direct clock signals (?) and complemented clock signals ({overscore (?)}), characterized in that it comprises means (5) for re-injecting a fraction (VIN) of the voltage from said charge pump (VHV) into the input (6) to which said supply voltage (VDD) is applied.

Abstract: A voltage reference circuit includes storage, programming, and test floating gate transistors. The floating gates of the storage and programming transistors are shorted, while the floating and control gates of the test transistor are shorted. The test and storage transistors are connected between an input terminal and the inputs of a comparator, with the control gate of the test transistor also being connected to the input terminal. A reference voltage is programmed by applying the reference voltage to the input terminal and increasing the net positive charge on the floating gate of the storage transistor (via the programming transistor) until its source voltage matches the source voltage of the test transistor. Then, any test voltage at the input terminal can be compared to the programmed reference voltage by comparing the source voltages of the test and storage transistors.

Abstract: Since improvement measures are not taken in regard to the electrostatic breakdown voltage, electrostatic breakdown voltages, between the common input terminal IN—first control terminal Ctl-1, between the common input terminal IN—second control terminal Ctl-2, between the first control terminal Ctl-1—the first output terminal OUT1, and between the second control terminal Ctl-2—the second output terminal OUT2, where both ends of gate Schottky junctions of FETs are lead out to the exterior, are low. To solve the problem, the embodiment of the invention provides a switch circuit device, wherein protecting elements are connected by disposing two electrode pads, for connection to a single control terminal, on a chip and positioning the electrode pads near the common input terminal pad I and an output terminal pad O1 or O2.

Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.

Abstract: A composite rectifying charge storage device, consisting of a rectifier and a capacitor which share common elements, further includes a transistor.

Abstract: A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

Abstract: Voltage regulators use capacitors to compensate the voltage regulator and provide stable performance. Capacitors have an inherent equivalent series resistance (ESR) that changes over various operating conditions including signal frequency, operating temperature as well as others. An apparatus and method compensates for the low ESR of capacitors to increase the total equivalent series resistance of the capacitor. By providing an “on-chip” resistance between the capacitor and the circuit ground potential, minimum total ESR can be provided such that stable load regulation is achieved with capacitors that would otherwise be undesirable for such use. Increasing the value of the output capacitor's equivalent series resistance allows wider ranging values of capacitance to be used. The increased range of capacitance values allows capacitors of different material types to be used.

Abstract: A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.

Abstract: A differentail amplifier with input gate oxide breakdown avoidance amplifies a difference between two signals while maintaining voltage drops across transistor utilized in the differential amplifier to below a gate oxide breakdown level. A pull up structure added to a traditional differential amplifier allows the circuit to be utilized in IO pads of an integrated circuit and to be composed of thin oxide transistor normally only found in the core circuitry of the integrated circuit and. The pull up structure is composed of three thin oxide transistors, the first transistor is connected in series with the other two, and the other two connected in parallel with respect to each other.

Abstract: A semiconductor integrated circuit driven by an external power, comprises a change unit whose state changes with lapse of time without the external power, an output unit configured to output a signal in response to an instruction issued when the external power is supplied, the signal indicating a change of the state of the change unit, and an execution unit configured to execute a process in response to the signal. Therefore, the circuit is capable of utilizing time-point/time-period information even if they are not supplied with power.

Abstract: An integrated semiconductor device is provided that has pads with less input signal attenuation. When J-FET (2) is driven by an input signal, the current passing through it varies. The parasitic capacitance (4) is charged or discharged by the input/output signal of the buffer circuit (6) following the varying current. Thus, since the voltage across the parasitic capacitance (3) varies in phase and at the same level, the parasitic capacitance (3) can be ignored. This effect allows attenuation of an input signal due to the parasitic capacitance (3) to be prevented.

Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

Abstract: A semiconductor integrated circuit includes a first power supply line which supplies an external power supply voltage provided from an exterior of the circuit, a second power supply line which supply an internal power supply voltage to an interior circuit, a plurality of NMOS transistors which are situated at different locations, and have drain nodes thereof coupled to the first power supply line and source nodes thereof coupled to the second power supply line, and a regulator circuit which supplies a reference voltage to gate nodes of the plurality of NMOS transistors.

Abstract: A resistance division circuit disclosed herein has a first MIS transistor having a first gate terminal, a first source terminal, a first drain terminal and a first back gate terminal, wherein the first gate terminal is regarded as a first terminal, and the first source terminal, the first drain terminal and the first back gate terminal are regarded as a second terminal, and one of the first terminal and the second terminal is connected to a first node of a first voltage; and a second MIS transistor having a second gate terminal, a second source terminal, a second drain terminal and a second back gate terminal, wherein the second gate terminal is regarded as a third terminal, and the second source terminal, the second drain terminal and the second back gate terminal are regarded as a fourth terminal, and one of the third terminal and the fourth terminal is connected to the other of the first terminal and the second terminal and the other of the third terminal and the fourth terminal is connected to a second no

Abstract: A power switching stage architecture for a buck topology-based, DC—DC converter includes an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the switching driver, while a lower power switching is also an N-channel FET, but is external to the driver chip. Either of the two power switching FETs may be configured to include a pilot FET cell, to facilitate current sensing for the controller.

Abstract: An electrostatic discharge (ESD) device used with a high-voltage input pad is described. The ESD device serves as a secondary device of a two-stage protection circuit, and comprises a substrate, a first MOS transistor and a second MOS transistor. The first MOS transistor is disposed on the substrate and comprises a first gate, a first drain and a first source, wherein the first gate is coupled to a bias Vg1, and the first drain is coupled to the high-voltage input pad. The second MOS transistor is disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first MOS transistor.

Abstract: An embodiment of a method of redistributing power in a semiconductor component includes varying a saturation current between a drain terminal (330) and a source terminal (320) of a field effect transistor (FET) (200, 500). The FET is at least a portion of the semiconductor component. The threshold voltage of the FET is maintained substantially constant across the FET while the drain-to-source saturation current per unit area is varied across the FET. In one embodiment, the drain-to-source saturation current per unit area is varied such that it is lower at a center of the FET than at a periphery of the FET. In particular embodiments, the drain-to-source saturation current per unit area may be varied across the FET by changing one or more of the gate-to-source voltage, the channel length, the channel width, the gate oxide thickness, and the channel mobility across the FET.

Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: An integrated circuit with a D.C./D.C. internal voltage regulator, including at least two power stages of the regulator, having respective terminals of connection to a supply voltage connected to distinct pads of the integrated circuit, and a single control stage.

Abstract: A radio frequency (RF) mixing device wherein RF core circuit elements requiring signal splitting are provided with one or more signal splitting element(s) (“balun(s)”) integrated on-chip with the core RF circuit elements. The RF mixing device comprises one or more RF circuit element(s) integrated on a common substrate with one or more balun(s), wherein the common substrate is an insulating substrate further provided with associated silicon-based CMOS circuitry formed in a thin, highly crystalline silicon layer formed on the insulating substrate. The insulating substrate is selected from transparent crystalline materials such as sapphire, spinel, etc. The common substrate is preferably ultrathin silicon-on-sapphire.

Abstract: An integrated semiconductor circuit has a potential detector for detecting a potential boosted by a high voltage generator. One terminal of a first capacitor is connected to a potential detection terminal via a first switching device, the other terminal thereof being connected to a reference potential terminal. A terminal of a second capacitor is connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, the other terminal thereof being connected to the reference potential terminal. A third switch is connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal. A clock generator generates clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switch periodically in an opposite timing for the first and the third switching devices.

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: A power integrated circuit includes a gate driver coupled to an output transistor having a plurality of segments. The gate driver also has a plurality of segments, each of the segments of the driver circuit being located adjacent a corresponding one of the segments of the output transistor. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.