Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run interconnect lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing on the remaining interconnect lines and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without critically increasing the line-to-line capacitance of these lines and adversely affecting the overall line RC time constant.

Abstract: A high-frequency circuit, wherein there is provided a switching transistor connected between an input terminal and an output terminal, with a gate electrode connected to a control terminal via a resistance element, and with an effective gate portion of the gate electrode divided into a plurality of sections, and arrangement is made of additional capacitance elements added in parallel to a capacitance between a gate and a source or drain of the switching transistor at positions in proximity to one ends of at least two effective gate sections of the plurality of effective gate sections. Preferably, there is provided a short-circuiting transistor similarly having an additional capacitance element between the output terminal Tout and a reference voltage supply line.

Abstract: Depletion mode pass transistor (38) accepts input voltage Vin and provides regulated output voltage Vout. The regulated output voltage is referenced to the threshold voltage of MOSFET (40) and is directly proportional to the ratio of resistors (50 and 52). MOSFET (58) provides enabling and disabling of voltage regulator (54). Multiple voltage regulators (FIG. 5) having multiple output potentials are realized on the same semiconductor die producing the same threshold potential for MOSFET's (40), whereby the output potentials are selectable using the ratio of resistors 50 and 52. Constant current source (56) reduces output voltage variation due to input voltage variation.

Abstract: A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are occupied by capacitors formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: An integrated circuit (100) has an input (110) for receiving an externally applied power supply voltage. Internal to the integrated circuit, a pass transistor (104) conveys the supply voltage to an internal supply node (120) which supplies the operating circuitry (102) of the integrated circuit. The pass transistor has a relatively low threshold voltage for operation at reduced supply voltage, such as 1.0 volt. The pass transistor is controlled by an enable signal received at an input (112) and by a charge pump (106). In a standby mode, the charge pump raises the voltage on the gate of the pass transistor to fully turn off the pass transistor and minimize standby current.

Abstract: A semiconductor chip of the present invention is provided with a switching means which connects a first signal terminal to a first internal signal wiring in response to a control terminal being in a first state, connects the first signal terminal to a second internal signal wiring different from the first internal signal wiring in response to the control terminal being in a second state different from the first state, and connects a second signal terminal to the first internal signal wiring. Since it is possible to switch the function of the first signal terminal and the function of the second signal terminal, wiring within a package is facilitated.

Abstract: A radio frequency device may be formed which has high power output and high transistor switching speeds. This may be done by providing thicker gate oxides and a higher supply potential to transistors utilized to form the power amplifier and using thinner gate oxides conventionally associated with high switching speed and advanced process technologies for other applications on the same integrated circuit. Thus, high switching speeds can be achieved-with some transistors which utilize a lower supply voltage and high power output can be achieved from other transistors which are coupled to a higher supply voltage. The different types of transistors may be made in the same integrated circuit fabrication process on the same integrated circuit.

Abstract: A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.

Abstract: A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Abstract: A multi-function output driver that may be used with at least two types of busses includes a multiplexer that shifts calibration bits to the pull-down transistors. This shifting changes which transistors of the transistor array are turned on when the pull-down drive transistors are driving. By changing which transistors are turned on, the impedance of the driver is changed. This shifting is used with a disable function on the pull-up drive-transistors to allow the driver to be used as an end-of-line termination, an open-drain driver, or as a source-terminated driver.

Abstract: A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.

Abstract: The invention relates to a variable capacitor and method of making it. The variable capacitor comprises a fixed charge plate disposed in a substrate, a movable charge plate disposed above the fixed charge plate, and a stiffener affixed to the movable charge plate. The movable charge plate may be patterned to form a movable actuator plate where the fixed charge plate is elevated above a fixed actuator plate.

Abstract: A high-side, low-side driver that controls voltage from a voltage source to an inductive or resistive load includes a power transistor with a gate, a source and a drain. The driver is configured in a high-side configuration when the load is connected between the source and ground and the drain is connected to the voltage source and in a low-side configuration when the load is connected between the drain and the voltage source and the source is connected to ground. A gate drive circuit turns the power transistor on and off. The positive clamp circuit is connected to the drain and the voltage source. The positive clamp circuit provides a recirculation path for inductive energy that is stored in the inductive load when a loss of reverse battery condition occurs or when ground is lost.

Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

Abstract: A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.

Abstract: A method and apparatus for reducing leakage in dynamic Silicon-On-Insulator (SOI) logic circuits improves the performance of dynamic gates implemented in SOI technology. A bias generator is used to create a negative potential by using the pre-charge input signal to bootstrap a bulk capacitor charging circuit, shifting a positively charged bulk capacitor terminal to ground, causing a negative potential at the other terminal. A bias control circuit applies this negative potential to intermediate nodes of logic input ladders of a dynamic logic gate to reduce leakage and threshold lowering effects due to the voltage variation on the bodies of logic input transistors implemented in SOI logic.

Abstract: A multi-stage assembly is disclosed, including a plurality of stages successively arranged, each having a controllable circuit portion and a controlling switching portion coupled thereto. The controlling switching portions have one or more ON/OFF switches which can be MOS transistors, CMOS circuits, etc. A first end of each ON/OFF switch of each controlling switching portion is coupled to a separate node of the controllable circuit portion of that stage and, also, is coupled, respectively, to a second end of a corresponding switch in an adjacent succeeding stage thereby to form selectively actuated one or more strings of series-coupled ON/OFF switches. All switches in an individual string being substantially simultaneously either turned ON or turned OFF.

Abstract: An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom.

Abstract: A voltage generator is disclosed which has a charge pump unit including a pump transistor for performing a charge pumping operation by a pump control signal from a ring oscillator and a precharge transistor for performing a charge precharge operation by a precharge control signal from the ring oscillator. The voltage generator additionally has a controller which provides a new back-bias control signal by combining the pump control signal from the ring oscillator with the precharge control signal from the ring oscillator and controls a threshold voltage of the precharge transistor with the back-bias control signal.

Abstract: In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.

Abstract: The microstructure includes an electronic circuit formed by a plurality of transistors (6) and a flat coil formed by a conductive wire or a conductive path (14). The coil (10) is arranged on an upper face (8) of the semiconductor substrate (4). The coil (10) generates a magnetic field (B) in this substrate (4) in the vicinity of the transistors (6) which are situated in superposition with said coil (10). The source (20) and the collector (22) of the sensitive transistors (6) are aligned along a direction perpendicular to the wire or path (14) in the portion of the coil situated in proximity to each of said transistors (6). Thus, the electric current (I) flowing in the transistors (6) is substantially parallel to the magnetic field (B).

Abstract: An output-matched LDMOS RF power transistor device includes a semiconductor die having a plurality of interdigitated electrodes formed thereon, the electrodes each having respective input terminals and output terminals. An input lead is coupled to a first terminal of an input matching capacitor by a first plurality of conductors (e.g., bond wires), with a second terminal of the matching capacitor coupled to a ground. The first terminal of the matching capacitor is also coupled to the electrode input terminals by a second plurality of conductors. A conductive island isolated from the ground is coupled to the electrode output terminals by a third plurality of conductors. Output matching of the device is provided by a shunt inductance formed by a fourth plurality of conductors, which couple a first terminal of an output blocking capacitor the conductive island, with a second terminal of the blocking capacitor coupled to the ground.

Abstract: A self-aligned SOI FET device with an "L" shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a "T" shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

Abstract: This invention discloses an integrated circuit device including transistors having predetermined upper voltage limits, a multi-layer metal interconnect structure connecting the transistors to each other and to an external voltage source having a voltage in excess of the predetermined upper voltage limits of a first plurality of the transistors, and a voltage reducer connected along the interconnect structure between the external voltage source and the first plurality of the transistors.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) A substrate region in the semiconductor substrate is enclosed by a ring of highly doped region (350). An NMOS ESD protection transistor (N1) with its backgate in the enclosed substrate region can be voltage pumped by pump circuitry (N2) in order to trigger bipolar conduction of the ESD protection transistor at a lower voltage. Control circuitry (304) is connected to the signal bond pad and to the gate of amplifier circuitry (P1) to provide a voltage pulse in response to an ESD zap applied to the signal bond pad. PMOS amplifier circuitry (P1) provides an amplified voltage pulse to the pump circuitry with a magnitude approximately equal to the ESD potential on the signal pad so that a strong pump current is provided to the highly doped ring.

Abstract: A gate-array cell uses smaller and larger transistors. Four larger transistors are provided: two n-channel and two p-channel. A small p-channel transistor is placed between the contact tabs of the polysilicon lines of the two larger p-channel transistors, and between the p-channel transistors and a N-well tap. A small n-channel transistor is similarly placed between the contact tabs of polysilicon lines of the two larger n-channel transistors, and between the n-channel transistors and a P-well tap. The cell is slightly expanded in height to accommodate the two smaller transistors. The smaller transistors enable a reduction in the number of transistors required for latches and flip-flops. The smaller transistors allow a feedback inverter to directly connect to an input, since the input can easily over-power the feedback current. This is not possible for standard gate array cells having only one transistor size. Transmission gates are eliminated when direct feedback is feasible.

Abstract: A resistor circuit having its impedance controlled by a DC voltage is provided. The resistor circuit includes a first resistor with an expected impedance. The circuit also includes a second resistor connected in series with a DC voltage controlled transistor. The first resistor is placed in parallel with the series connection of the second resistor and the transistor. Adjustments to the impedance of the circuit occur by adding or removing the impedances of the second resistor and transistor by varying the DC voltage applied to the transistor. In doing so, the impedance of the resistor circuit will be controlled to match a desired impedance regardless of the variations caused by the manufacturing process, operating temperature or operating power supply voltage.

Abstract: A booster circuit is disclosed, the booster circuit having a plurality of booster cells tandem-connected, each of the boosters having a transfer transistor and a capacitor, an input terminal, a drain, and a gate of the transfer transistor being connected, a source of the transfer transistor being an output terminal, a first terminal of the capacitor being connected to the source of the transfer transistor, a clock signal being supplied to a second terminal of the capacitor, wherein the transfer transistor is composed of a triple-well having a first well and a second well, the first well being formed on a semiconductor substrate, the second well being formed on the first well, and wherein the semiconductor substrate is connected to a reference voltage, a diffusion layer in the first well, a first diffusion layer in the second well, a second diffusion layer in the second well, the first terminal of the capacitor, and the gate of the transfer transistor being connected, the conduction type of the first well bein

Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

Abstract: A semiconductor integrated circuit device is responsive to a potential level applied to a signal pad connected to a mode changer, and the mode changer causes a mode selector to change a control signal between a first level indicative of a certain combination of sub-circuits of a main circuit selected before separation of the semiconductor chip from a master slice and a second level indicative of another combination of the sub-circuits not selected by a customer; when the manufacturer evaluates the semiconductor integrated circuit device, the manufacturer changes the potential level at the signal pad, and carries out a test for the certain combination and another combination; when the semiconductor chip is sealed in a package, the signal pad is electrically isolated from a source of potential level, and the control signal is fixed to the first level.

Abstract: A motherboard/daughterboard assembly is configured to permit upgrading of a system to a microprocessor requiring different clock signals. The motherboard includes a clock generator mounted on the motherboard with a control input terminal and an output terminal. The clock generator delivers a first and second clock signal on the output terminal in response to receiving a first and second signal on the control input terminal, respectively. A first electrical connector is mounted on the motherboard and has a first terminal. The first terminal is coupled to the control input terminal of the clock generator. The daughterboard has a second electrical connector mounted thereon, and a first terminal. The second electrical connector is mateable with the first electrical connector to electrically engage the first terminals of the first and second electrical connectors.

Abstract: A signal processing apparatus is formed on a single semiconductor substrate and includes in a mixed relation an analog signal processing section and a digital signal processing section. A plurality of buffers are included on the substrate to buffer the respective sections from one another for preventing abnormalities such as circuit malfunctions, circuit failures, noise and excess current flow between the respective sections at power-on. The buffers are of different types according to the abnormality they are designed to prevent.

Abstract: A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time, the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

Abstract: A structure is provided to create a voltage-independent capacitive structure using a typical MOS fabrication process. The capacitive structure includes two FET devices connected in series by having their source, drain, and body terminals all coupled together into a common node. A biasing circuit that includes a current generator and a current mirror biases the common node so that a constant capacitance is maintained across the gate terminals of the two serially connected FET devices, independent of the applied voltage.

Abstract: A clock driver circuit comprises a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common line 18 and 21. The second common line 21 is connected to a plurality of clock signal supply lines 20(1) through 20(m) which in turn are connected to the clock input nodes of second macro cells 16 each requiring a clock signal. In a test mode, the first and second common lines 18a and 21a of the first clock driver 15a and the first and second common lines 18b and 21b of the second clock driver 15b are electrically connected by first and second connection means 22 and 24, respectively. Thus, a clock driver circuit is provided that offers high driving ability with negligible clock skews in both normal mode and test mode.

Abstract: A variable voltage driver circuit produces an output swing off of a single voltage power supply which is logically configurable to allow interconnection of CMOS chips of varying technologies and power supplies. First a voltage requirement for a destination chip is identified to which a driver chip is to be coupled, and the voltage requirement for the driver chip is identified. The variable voltage driver circuit is activated to produce a variable voltage output swing off of a single voltage power supply meeting the voltage requirements of the driver chip. The driver has data input, and level selection inputs and pins which select and enable the driver independent of the output level state that the driver is in.

Abstract: There is provided an array device including functional circuits for a plurality of channels, constant current generating circuits for the plurality of channels for generating constant currents used to drive the functional circuits, respectively, in accordance with a control signal supplied from the outside, and a wiring for supplying therethrough the constant currents from the constant current generating circuits to the functional circuits, respectively, which are formed on an integrated circuit chip, wherein the constant current generating circuits provided so as to correspond to the channels are arranged concentratedly in a specific region on the integrated circuit chip, and the wiring is comprised of a common wiring extending from one terminal provided in the vicinity of the specific region to the vicinities of the constant current generating circuits.

Abstract: A solid-state switching element that works with at least one semiconductor region or a pair of antiserially arranged semiconductor regions having characteristic curves similar to those of FETs. An internal body diode in inverse operation is also provided. In addition to having a drain and a gate, each of the semiconductor regions has two source electrodes, with several cells combined with the electrodes in cell design. One source serves as a load current electrode, called a load source, and the other source is available as a gate electrode, called a control source. The effective semiconductor region of the load source is larger than the effective semiconductor region of the control source.

Abstract: An integrated circuit voltage multiplier 30 in a semiconductor substrate of a first conductivity type. The multiplier includes a diode 22, having a first voltage VDD applied to a first port thereof, the diode being made of: 1) a first well 12 of a second conductivity type formed in the substrate, being connected to a second voltage VB; 2) a second well 14 of the first conductivity type formed in the first well, having an electrical contact point comprising the first port of the diode; and 3) a third well 16 of the second conductivity type formed in the second well, having an electrical contact point comprising a second port of the diode. The multiplier also includes a capacitor C3, having a first contact thereof connected to the second port of the diode and having a third, pulsed voltage PH1 connected to a second contact of the capacitor.

Abstract: A pull-up output driver circuit includes a field effect transistor (FET) fabricated in a well region having a first conductivity type. The well region, in turn, is surrounded by a semiconductor region having a second conductivity type. The FET has a source connected to an output pad and a drain connected to a V.sub.CC voltage supply rail. The gate of the FET and the well region are connected to a driving circuit, and the semiconductor region is connected to the V.sub.CC voltage supply rail. A lateral bipolar transistor is formed by the drain, the source and the well region, and a vertical parasitic bipolar transistor is formed by the source, the semiconductor region and the well region. The driving circuit provides a signal (or signals) to the gate and well region to control the pull-up driver circuit. The FET turns on at a relatively low threshold voltage because the lateral bipolar transistor and the FET are turned on at substantially the same time.

Abstract: A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

Abstract: A semiconductor integrated circuit comprising a first functional block consisting essentially of a first circuit which includes a small junction device, and a second functional block consisting essentially of a second circuit which includes a field effect transistor, the second functional block being mutually connected to the first functional block.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract: A computer implemented method provides for orientation and lay-out asymmetrical semiconductor devices. The sources of operating potential (20, 30) are identified. The PMOS transistors (22-28) are combined between the first (more positive) source of operating potential and a common node (12) into a combination block (48). The NMOS transistors (14-18) are combined between the common node and the second (less positive) source of operating potential into another combination block (52). The PMOS source terminals are coupled to more positive potentials, and the PMOS drain terminals are coupled to less positive potentials within the first combination block. The NMOS source terminals are coupled to less positive potentials, and the NMOS drain terminals are coupled to more positive potentials within the second combination block. For transmission gates (60, 62), a driving source is identified and the PMOS and NMOS source terminals are coupled to the driving source.

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Abstract: In an integrated circuit, a central reference generator (3) generates a setpoint signal determining the operating characteristic required to be common to some of the functional components of the circuit. Lines (4-1 to 4-n) distribute this signal among units of the circuit, each unit comprising a functional Component (2-n). In each unit, a local adjustment circuit (5-n) receives the setpoint signal and generates an adjustment value. Correction circuitry adjusts the operating characteristic of a device in the local adjustment circuit (5-n) as a function of the adjustment value. The device is placed in proximity to the functional component and configured in such a way that the operating characteristic which is thus imposed on the device is also imposed on this component.

Abstract: A weak pull-up disable method and mechanism therefor for use in association with a microcontroller incorporated in an integrated circuit. The weak pull-up disable mechanism is incorporated in the integrated circuit containing the microcontroller. The mechanism disables the weak pull-ups of I/O buffers of the microcontroller. The weak pull-ups serve to pull the voltage of the associated ports high. By so disabling the weak pull-ups, the need for a driver to sink the current when in input mode is eliminated. Elimination of the need for an external driver due to the weak pull-up disable mechanism reduces power consumption by the integrated circuit.