Abstract: An integrated circuit includes a data terminal, a supply potential terminal, a configuration signal generator with an input, a buffer circuit with a terminal and a bond pad connected to the input and the terminal. The bond pad is connected to the data terminal for operating the integrated circuit using the buffer circuit and the bond pad is connected to the supply potential terminal for operating the integrated circuit using the configuration signal generator. A method for producing such an integrated circuit includes connecting the input of the configuration signal generator and the terminal of the buffer circuit to the bond pad. The bond pad is connected to the supply potential terminal for operating the finished integrated circuit using the configuration signal generator, or to the data terminal for operating the finished integrated circuit using the buffer circuit.

Abstract: A semiconductor integrated circuit includes a chip having an element forming surface with a side thereof extending along a first direction, an output buffer portion provided on the element forming surface of the chip, a plurality of output transistors having different emitter areas provided on the element forming surface of the chip and arranged approximately in a line along a second direction, which is perpendicular to the first direction, and a pad provided on the element forming surface of the chip. An output circuit is formed by the output buffer portion, a portion or all of the output transistors and the pad. The output buffer portion, the output transistors and the pad are arranged approximately in a line along the second direction.

Abstract: The threshold voltage and on-resistance of a four-terminal power MOSFET switch are reduced by partially forward-biasing (to, for example, 0.5 V) the junction between the body and electrical source of the MOSFET. Preferably, as the MOSFET is switched on and off to control the current to a load, the body is switched synchronously with the gate so that the source-body junction is partially forward-biased (i.e., biased at a level that is insufficient to cause a forward current to flow through the junction) when the MOSFET switch is turned on and the body is shorted to the source when the MOSFET switch is turned off, thereby reducing the leakage current through the MOSFET in its off state. The body bias may be derived directly from the gate voltage or from a separate voltage supply line. A current-limiting device and a voltage clamp may be used to limit the body current and voltage, respectively.

Abstract: A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.

Abstract: Method and apparatus for controlling an output transistor in an output driver circuit. In one embodiment of the invention, an input signal is routed to a first gate body which is disposed over a first channel region in a substrate. The first gate body has a first resistance to the input signal and delays the input signal through the first gate body to provide a delayed input signal. This delayed input signal is routed to a second gate body which is disposed over a second channel region in the substrate. The first gate body is coupled to the second gate body to provide the delayed input signal to the second gate body. According to one embodiment of the invention, the transistor includes the first gate body coupled to an input signal and coupled to the second gate body to receive the input signal through the first resistance of the first gate body.

Abstract: An FET with a lightly doped drain is connected between an input/output pad and ground and is protected from ESD at a pad by a structure that includes a resistor formed by the process step for the lightly doped drain. The resistor adjoins and interconnects a diffusion underlying the pad and the diffusion for the drain of the FET. A parasitic bipolar transistor is formed by the pad diffusion, the source diffusion for the FET, and the intervening substrate. When an ESD voltage appears at the pad, the FET conducts in circuit with the resistor and the voltage drop across the resistor helps to protect the FET and to turn on this parasitic bipolar transistor (in preference to a parasitic bipolar transistor otherwise formed by the FET) and thereby hold down the ESD voltage at the pad and at the drain of the FET. The FET and resistor can be formed as a number of parallel connected FETs and resistors located symmetrically on opposite sides of the pad diffusion. Protection for an input inverter circuit is also provided.

Abstract: An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

Abstract: An integrated circuit (IC) with metal-oxide semiconductor field effect transistor (MOSFET) circuitry and on-chip protection against oxide damage caused by plasma-induced electrical charges includes a MOSFET circuit for receiving and processing an input signal and a complementary MOSFET pass gate coupled to the input thereof for receiving and passing the input signal thereto. The complementary MOSFET pass gate includes complementary MOSFETs with control terminals, input terminals and output terminals, with the control terminals being connected for receiving the IC power supply voltage and ground potentials, the input terminals connected together for receiving the input signal and the output terminals connected together and to the input of the MOSFET circuit for passing the input signal thereto in response to the receiving of the IC power supply voltage and ground potentials.

Abstract: A first circuit and a second circuit having the same voltage-current characteristics are connected in series between a power supply potential node and a ground potential node. Each of the first and second circuits includes as a load element a MOS transistor formed on a semiconductor substrate having a triple-well structure. A first reference potential is provided from the first circuit. A third circuit and a fourth circuit having the same voltage-current characteristics are connected in series between the power supply potential node and the ground potential node. Each of the third and fourth circuits includes as a load element a MOS transistor formed on the semiconductor substrate having the triple-well structure. A second reference potential is provided from the third circuit. The first reference potential is applied to the gate of an n-channel MOS transistor connected between the power supply potential node and an output node.

Abstract: A semiconductor circuit which has such a configuration that a power supply terminal connected to an overvoltage protection circuit is formed independently from a power supply terminal connected to a semiconductor circuit unit, or that an overvoltage protection circuit and a semiconductor circuit unit are connected to a common power supply terminal with wirings branched from the power supply terminal with an overcurrent flowing through the overvoltage protection circuit prevented from flowing into the semiconductor circuit unit.

Abstract: Within an integrated circuit, an input/output driver circuit is provided. The input/output driver circuit is configured to provide electrical isolation and power savings when the integrated circuit is configured into a computer system such as a personal information device. By providing a mechanism permitting removal of power from the driver circuit, the integrated circuit inhibits current flow from the integrated circuit into a powered-down peripheral device. A force term is activated, when electrical isolation is desired, to inhibit current flow into or from the integrated circuit via an input/output pad voltage level. A power savings is enabled by allowing the power down of peripheral devices coupled to the integrated circuit without the need for external buffer circuits.

Abstract: A circuit for controlling a power transistor connected in series with a load. The circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, and which produces a signal at two levels referred to the node between the power transistor and the load. The level shifter includes a flip-flop the output of which controls the power transistor as well as two transistors driven by the control logic circuit to switch alternately and provide switching signals on the "set" and "reset" inputs of the flip-flop via two resistors. Two parasitic current generators inject current into the two resistors during the phase in which the power transistor is cut off. To prevent this current from causing unwanted switching of the flip-flop, a resistor connected to the "set" terminal of the flip-flop has a lower resistance than that of the other resistor.

Abstract: An electrostatic discharge protection device for protecting the input of a circuit comprises a p-channel MOSFET (P-FET). The n-well with P+ implants of the P-FET provides a functional lateral PNP bipolar transistor that is coupled between the input of the circuit and a supply node of the circuit. Biasing circuitry controls biasing of the gate and n-well body of the P-FET in accordance with the voltage at the input of the circuit.

Abstract: The invention concerns an analog amplifier constructed using digital transistors. The digital transistors are those contained in a gate array, and which are used for fabrication of digital devices. The analog amplifier includes an invertor, which contains two cascode amplifiers in series. The analog amplifier also includes a differential amplifier. The invertor is contained within the feedback circuit of the differential amplifier.

Abstract: Circuit blocks to which reference clock signals with different frequencies are input can be fabricated on the same substrate. A supply path of a supply voltage applied to a source region of a first PMOSFET and a first N-type well region, and a supply path of a supply voltage applied to a source region of a second PMOSFET and a second N-type well region, are isolated from each other by the first and second N-type well regions, respectively. A supply path of a supply voltage applied to a source region of a first NMOSFET and a first P-type well region, and a supply path of a supply voltage applied to a source region of a second NMOSFET and a second P-type well region, are isolated from each other by the first and second P-type well regions, respectively. The respective isolation of the supply voltage supplied path ensures that substrate potential fluctuations caused by the different frequencies do not result in a beat (a wave form distortion) being present on outputs of the circuit blocks.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Abstract: An intensity controlling circuit device can correct variation in intensity of light beams, due to tolerance occurred in each of a plurality of LED-array chips, emitted by LEDs provided in each of the LED-array chips. The intensity controlling circuit device is connected to at least one LED-array chip comprising a plurality of LEDs and slave transistors corresponding to each of the LEDs. The intensity controlling circuit device comprises an intensity controlling circuit connected to the respective LED-array chip. The intensity controlling circuit comprises a first transistor provided between a power source and a constant current generating unit so as to supply a current to the LED-array chip, and an intensity adjusting unit having a second transistor connected to the first transistor in parallel and a controlling unit for controlling the on/off state of the second transistor.

Abstract: An electronic circuit is provided with a first field effect transistor and a second field effect transistor, in which a drain of the first field effect transistor connected to a source of the second field effect transistor. This electronic circuit inputs a first signal to a gate electrode of the first field effect transistor, inputs a second signal to a gate electrode of the second field effect transistor and outputs a signal from a drain of the second field effect transistor. This electronic circuit is a cascode circuit related to the current drivability of the second field effect transistor is set to be larger than the current drivability of the first field effect transistor, and there is an effect that third-order or higher order distortion characteristics of a cascode type or dual-gate circuit can be reduced.

Abstract: An interface circuit for interfacing between an integrated circuit (IC) on a transmitting side and an IC on a receiving side over a line on a printed circuit board comprises an output circuit implemented in the IC on the transmitting side and composed of a current source for supplying a given current and a switching circuit for cutting off the given current according to a binary signal and delivering the given current as a current signal to the line, and an input circuit implemented in the IC on the receiving side and composed of a transimpedance circuit whose input impedance is equal to the one of the line and which converts the current signal into a voltage signal, and a comparator for identifying the voltage signal relative to a given threshold voltage and reproducing the binary signal. This circuitry makes it possible to provide an interface circuit that can be implemented in a CMOS IC during CMOS processing and operated at a low voltage.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: The voltage reference generator of the present invention includes a plurality of p-channel transistors configured to act as resistors. Switching transistors, responsive to input signals, are utilized to bypass the resistors when in the "on" state, and enable the resistor when in the "off" state. Thus, when enabled, the resistors become part of a total resistance value in a branch of a voltage divider circuit. A minimum amount of space is used on an integrated circuit because the switching transistors are of the same type as the transistors which are configured to act as resistors.

Abstract: A MOS-type semiconductor clamping circuit includes a semiconductor substrate receiving a substrate potential, a well isolated electrically from the substrate potential, and MOS-type transistors formed in the well. Those transistors are connected with each other in series, each transistor has its gate connected to its drain, and a stable potential different from the substrate potential is applied to the well.

Abstract: High-frequency, low-power CMOS oscillators having electrically-tunable tank circuits are disclosed. Electrically-tunable inductors assure highly efficient oscillator operation and can be adjusted after manufacture to assure high yields of high-precision oscillator circuits.

Abstract: Microelectronic semiconductor integrated circuit devices integrated on a common substrate with molecular electronic devices, having barrier-well-barrier structure with the well being conductive oligomer.

Abstract: A low-voltage driven semiconductor device is simple to fabricate, operates at high speed, and consumes low power. The semiconductor device is made of first and second MISFETs connected in series. The MISFETs have channels of the same conduction type. If the conduction type is n, the drain and gate of the first MISFET are connected to the high-potential side of a power source. The source and well of the second MISFET are connected to the low-potential side of the power source. The well of the first MISFET and the gate of the second MISFET are connected to a signal input terminal. A voltage applied to ends of the MISFETs and the potential fluctuation range of a signal supplied to the signal input terminal are each set to be lower than a voltage determined by a built-in potential (a forward withstand voltage) of a pn junction between a well of the first MISFET and a diffusion layer of the same. The diffusion layer is one that is adjacent to the second MISFET.

Abstract: A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line.

Abstract: To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel transistor are disconnected and a third transistor couples the body to a reference potential. The N-channel transistor and high voltage transistor share a common body in a semiconductor substrate. The source of the N-channel transistor provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.

Abstract: A semiconductor device is disclosed which is directed to drastically reduce a conduction test time by reliably executing the conduction test of all terminals in a lump. The invention discloses the semiconductor device including a first power supply terminal, a second power supply terminal having a lower potential than the first power supply terminal, an internal circuit portion to which the first and second power supply terminals are connected, and an input signal terminal group and an output signal terminal group each connected to the internal circuit portion, wherein a first voltage supply source and a second voltage supply source having a predetermined potential difference from the first voltage supply source are disposed, a switching device is interposed between the first and second voltage supply sources, and the switching device is turned ON and OFF in accordance with the existence of a voltage applied to each of the terminals described above.

Abstract: Control voltages are generated so that each transistor in a plurality of parallel connected field effect transistors turns ON with smooth transitions between transistors and in a manner that is relatively insensitive to processing and operating temperature variations.

Abstract: A device including a MOS power transistor, and a temperature sensor including a bipolar transistor integrated in the MOS transistor and having its emitter and collector connected directly to the source and gate terminals respectively of the MOS transistor. Parallel to the base-emitter junction of the bipolar transistor, there is connected a voltage source for biasing the junction to such a value that the bipolar transistor remains off at room temperature, and absorbs the maximum current supplied by a drive circuit of the MOS transistor at the maximum permissible temperature TUM. At temperature TUM, the bipolar transistor takes over control of the gate-source voltage of the MOS transistor for maintaining thermal feedback of the device at maximum temperature TUM.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.

Abstract: A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.

Abstract: A system for reducing power in electronic systems blocks current paths by electrically isolating idle, targeted devices through switching off the various device's entire sets of pins from the rest of the electronic system. Solid state switches are connected to every pin of a targeted device. In one logic state a control signal will turn the switches on and thereby connect the targeted device to the remainder of the system. In another logic state, the control signal will isolate the targeted device.