Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.

Abstract: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.

Abstract: A semiconductor device includes a differential circuit for receiving a differential signal at an input terminal and a detection circuit for outputting a detection signal when a predetermined signal is inputted to the input terminal. The detection circuit detects whether the differential signal becomes outside an electric input standard and outputs the detection signal.

Abstract: Aspects of a method and system for wide range amplitude detection are provided. In this regard, many electronic systems may require amplitude detection of a variety of signals with widely varying amplitudes. Aspects of the invention may comprise suitable logic, circuitry, and/or code to perform amplitude detection and may be easily configured to accommodate a wide range of amplitudes. In this regard, the configuration of the amplitude detector may be performed via simple design changes and/or may be dynamically configured by suitable logic, circuitry, and/or code. Accordingly, multiplexing a single instance of the wide range amplitude detector and/or multiplexing multiple instances of the wide range amplitude detector may result in reduced design time, reduced circuit size, and/or reduced cost.

Abstract: A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage.

Abstract: An amplifying unit performs a differential amplification with a highest level or a lowest level of an input signal and a previous input signal. A semiconductor element transfers a signal level output from the amplifying unit from a second terminal to a third terminal by using a current conducted from the second terminal to the third terminal in response to a voltage applied to a first terminal. A control unit controls the voltage applied to the first terminal of the semiconductor element based on a voltage or a current related to a reference semiconductor element. A holding unit holds a signal level output from the third terminal of the semiconductor element.

Abstract: Method and apparatus for providing a peak detection circuit comprising a diode including an input terminal and an output terminal the input terminal of the diode configured to receive an input signal, a capacitor operatively coupled to the output terminal of the diode, an output terminal operatively coupled to the capacitor and the output terminal of the diode for outputting an output signal is provided. Other equivalent switching configuration is further provided to effectively detect and compensate for a voltage droop from a power supply signal, as well as to electrically isolate the voltage droop from the system circuitry.

Abstract: A peak detector for implementation in a monolithic integrated circuit includes one or more Miller capacitors and one or more transistors for selectively setting large RC time constant values only with components included in the integrated circuit's die. Neither resistors nor capacitors located outside the integrated circuit are used for setting a selected value of a time constant. Some embodiments of the invention include diodes for compensation of amplifier leakage current in the peak detector, thereby increasing a maximum value of a time constant that can be implemented in an integrated circuit. A peak detector in accord with an embodiment of the invention may optionally be configured for either single-ended or differential operation.

Abstract: A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein the positive-side Schmitt trigger is configured to receive an output provided by the input stage, and wherein the positive-side Schmitt trigger is configured to create a positive-side Schmitt trigger output representative of the current input, and a negative-side Schmitt trigger in communication with the input stage, wherein the negative-side Schmitt trigger is configured to receive the output provided by the input stage, and wherein the negative-side Schmitt trigger is configured to create a negative-side Schmitt trigger output representative of the current input.

Abstract: A peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier. A source/emitter of the correction transistor is coupled to the operational amplifier. The peak hold circuit also includes a current detection circuit, which detects current flowing to the input transistor, and a peak current hold circuit, which holds the peak value of the current detected by the current detection circuit as a peak current and supplies the peak current to the correction transistor.

Abstract: A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again.

Abstract: An exemplary programming circuit (40) includes an input terminal (42) configured for receiving an external high voltage signal, a driving circuit (20), a switch circuit (43) connected between the input terminal and the driving circuit, and a feedback circuit (45). When the external high voltage signal is larger than a normal value thereof, the feedback circuit outputs a first control signal to turn off the switch circuit. When the external high voltage signal is less than the normal value thereof, the feedback circuit also outputs the first control signal to turn off the switch circuit. When the external high voltage signal is equal to the normal value thereof, the feedback circuit outputs a second control signal to turn on the switch circuit.

Abstract: A method for calculating a voltage spike value includes: predefining calculating requirements; inputting parameter values; analyzing whether inputted parameter values match with the calculating requirements; establishing a computing formula for calculating the voltage spike value if the inputted parameter values match with the calculating requirements; and calculating the voltage spike value by utilizing the inputted parameter values and the computing formula. A related system is also disclosed.

Abstract: There is described a method for increasing an availability and a redundancy of an analog current output as well as an analog current output with increased availability and redundancy. To improve the availability and also the redundancy behavior of an analog current output a first set of current sources is switched to active to generate an output current, one current source respectively of the first set is checked cyclically for serviceability and the other current sources respectively generate the output current in equal parts. Where unserviceability is determined, the corresponding current source is disconnected and removed from the first set. If a malfunction occurs, such as a failure of a current source for example, the output current advantageously does not drop out completely due to the allocation of generation to a number of current sources.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: A direct relationship exists between an integrated comparator's propagation delay and the input differential pair's bias current and overdrive voltage. A new method using a pulsed bias scheme for the input differential pair improves propagation delay by more than one order of magnitude without increasing significantly the average quiescent current, as long as the pulse width of the bias current is small relative to the system clock. A voltage limiter optimizes the comparator's transition time and a built-in hysteresis circuit minimizes spurious output transitions whenever the pulsed bias current pulse changes state. The bias current pulse and sampling of the comparator occur in predefined relation to the system clock.

Abstract: A high speed analog transmission envelope (data-validity) detector for detecting the validity or invalidity of received data by generating (and comparing) first through fourth level-shifted signals based on a pair of differential input signals that are externally applied (received). Each of the first through fourth level-shifted signals has voltage levels different from (e.g., higher than) the differential input signals. After comparing the first through fourth level-shifted signals with each other, the comparison results are used in determining the validity of the differential input signals (data). The analog transmission envelope (data) detector flexibly adapts to variations in common mode voltage, and simplifies the circuit architecture because it does not require an additional reference voltage for determining the validity of received data.

Abstract: An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.

Abstract: A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.

Abstract: There is disclosed a circuit and a process for detecting peak-to-peak voltage. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.

Abstract: A circuit configuration which includes an input circuit referenced to one ground voltage and an output circuit referenced to another ground voltage capacitively coupled to the input circuit.

Abstract: Differential peak detection for outputting a signal indicative of a peak value of an input signal. The input signal is differentially amplified using common mode feedback and a common mode output is thereby output, wherein common mode level of the common mode output is substantially the same as a common mode voltage. The common mode output of such differential amplification is coupled to an input of a first common source input pair, and the common mode voltage and a feedback from the output signal across a sampling capacitor is coupled to an input of a second common source input pair. A summation of respective outputs of the first and second common source input pairs is coupled to an input of a transconductance stage, wherein an output of the transconductance stage controls charging of the sampling capacitor. In this manner, a more accurate output signal is provided.

Abstract: A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1st input, 2nd input and an output, where the 1st input is operably coupled to receive the high frequency signal. The transistor has an input, a first node, and a second node, where the input is coupled to the output of the amplifier, the second node is coupled to a supply voltage, and the first node is coupled to the 2nd input of the amplifier. The capacitor is operably coupled to the first node of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.

Abstract: A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.

Abstract: A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwith (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.

Abstract: An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential at a first connection point of the first drive transistor (Q1) and a first conductivity-type transistor (M1) is removed, and by setting a current flowing through a second diode-connected transistor (Q6) and a current flowing through a second drive transistor (Q4) to be in a predetermined relationship, variation with temperature in potential at a second connection point of a second conductivity-type transistor (M2) and the second drive transistor (Q4) is removed.

Abstract: A self-stop circuit has a nonvolatile storage element (20), and a write terminal (50) and an erase circuit (30) for controlling the amount of electric charges charged in or discharged from the nonvolatile storage element (20). A determination circuit (40) determines that the amount of electric charges accumulated in the nonvolatile storage element (20) falls below a threshold, so as to detect an elapsed time. Thereby, the end of the lifespan of a product is detected and the operation of the product is stopped or modified after the end of the lifespan. When the operation is desired to be restored, electric charges are injected into the nonvolatile storage element (20) again, or a cancel signal is supplied through an external terminal (53) to the determination circuit (40).

Abstract: A method for operating a threshold circuit arrangement and a threshold circuit arrangement is disclosed. In one embodiment, the invention provides a threshold circuit arrangement, wherein a comparator circuit is configured to compare an input signal is compared with a predetermined threshold, and wherein, depending on the result of the comparison, an output signal is adapted to change its state. A circuit is provided for preventing the change of state of the output signal in the case of predetermined forms of the input signal.

Abstract: A system for detecting the envelope of a signal is provided. The system includes a first envelope detector generating a first envelope signal of an input RF signal, such as an envelope signal representing the positive peak envelope of the input RF signal. A second envelope detector generates a second envelope signal of the input RF signal, such as an envelope signal representing the negative peak envelope of the input RF signal. A signal combiner receives the first envelope signal and the second envelope signal and generates an even-order harmonic compensated envelope signal, such as by compensating for the difference between the positive peak envelope and the negative peak envelope.

Abstract: The invention provides a transient voltage detecting circuit for detecting changes of voltage in an electronic system which has a first power supply (VDD), a second power supply (VDD), a third power supply (VDD), a fourth power supply (VDD), a first ground (GND), and a second ground (GND). The voltage of the first VDD is substantially equal to that of the second VDD. The voltage of the third VDD is substantially equal to that of the fourth VDD. The voltage of the first GND is substantially equal to that of the second GND. The circuit according to the invention can detect a positive or negative transient voltage once that occurs at the first VDD, the second VDD, the third VDD, or the fourth VDD.

Abstract: An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a second input voltage. The second comparator circuit may be configured to generate a second intermediate current in response to the first input voltage and the second input voltage. The third comparator circuit may be configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage. The difference circuit may be configured to generate a first compare voltage and a second compare voltage in response to the first intermediate current, the second intermediate current, and the intermediate reference current. The apparatus may indicate a squelch condition when the first compare voltage is greater than the second compare voltage.

Abstract: A peak detector can advantageously increase its bandwidth, i.e. its charging and discharging speed, while minimizing the ripple of its output signal by sensing the charging current of a storage device. In response to that charging current, the peak detector can control a discharge current, thereby accelerating its response. For example, the peak detector can reduce a discharge current in response to an increased charging current (which indicates a charging phase) and increase the discharge current in response to a decreased charging current (which indicates a discharge phase).

Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

Abstract: A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: A demodulator for demodulating a modulated signal has a peak detector (206) with an input (100) coupled to receive the modulated signal and an output (207) to supply a peak detector output signal. The peak detector has a charge storer (314) coupled to the peak detector output so that the peak detector output signal is provided by a voltage across the charge storer (314) and a comparator (313) having a first comparator input coupled to the peak detector input to receive the modulated signal and a second comparator input coupled to the peak detector output to receive the peak detector output signal. The comparator (313) provides a comparison signal representing a comparison between the voltage of the modulated signal and the peak detector output signal.

Abstract: A signal amplification device which uses inexpensive standard CMOS and yet is capable of high-accuracy threshold setting. An offset voltage generator detects the direct-current level of an input signal, and generates a positive or negative offset voltage signal. A peak detector outputs, as a peak value, the positive offset voltage signal if the level thereof is higher than the maximum level of the input signal, or the maximum level of the input signal if the maximum level is higher than the positive offset voltage signal. A bottom detector outputs, as a bottom value, the negative offset voltage signal if the level thereof is lower than the minimum level of the input signal, or the minimum level of the input signal if the minimum level is lower than the negative offset voltage signal. A voltage divider subjects the peak and bottom values to voltage division, to generate a threshold level.

Abstract: A matched filter and peak detector identify peaks of a received signal. The peak detector may detect peaks during a fixed or adjustable time window. The peaks may be used as a preliminary decision (e.g., soft decision) for subsequent receiver decoding operations. The detector may be used to detect high bandwidth signals such as ultra-wide band signal pulses yet consume relatively minimal power.

Abstract: An RF envelope detection circuit that operations at low currents, high sensitivity, and high dynamic range. The circuit receives an AC signal at its input terminal and applies a signal on its output terminal that is a function of the envelope magnitude of the AC signal. To do so, a current source provides a current with an AC signal being superimposed thereon. A rectification circuit rectifies the AC component of this current. A voltage amplifier then amplifies the voltage for providing on the output terminal of the detection circuit. A current sink draws a current from the output terminal that has approximately the same magnitude as the current provided by the current source. A capacitor is coupled to the output terminal of the rectifier so as to store excess charge provided by the rectifier that is in excess of the magnitude of the current provided by the current source.

Abstract: A method and device are disclosed for the detection and synchronization of a signal in a frequency-hopping system. The method has a step, for each frequency F(1) . . . F(M), of selecting the K samples corresponding to the greatest values of the signal, and their positions. For a given position, the M greatest values are combined which are selected from among K samples on each frequency having the given position. The greatest combined value is kept and the corresponding position. The greatest combined value is compared with a threshold value, and if the greatest combined value is greater than this threshold value, then the detection of the signal is declared.

Abstract: A wide linear range peak detector including first and second peak detectors and a compensation circuit. The first peak detector receives an input signal and has an output providing a first peak signal approximation which approximates a peak level of the input signal. The first peak signal approximation includes a non-linear portion which is a function of the peak level of the input signal. The second peak detector also receives the input signal and has an output providing a second peak signal approximation. The compensation circuit uses the second peak signal approximation to provide a compensation signal which compensates the non-linear portion of the first peak signal approximation. In particular, the second peak signal is used to generate the compensation signal to approximate and cancel the non-linear portion.

Abstract: A line trouble detecting circuit comprises a peak detecting circuit, a first comparison circuit, a bottom detecting circuit, a bottom detecting circuit, a second comparison circuit, and a signal keeping circuit. The peak detecting circuit detects a peak voltage of amplitude of the one of the differential signal. The first comparison circuit compares an output of the peak detector and a first reference voltage. The bottom detecting circuit detects bottom voltage of the amplitude of the one of the differential signal. The second comparison circuit compares an output of the bottom detecting circuit and a second reference voltage. The signal keeping circuit keeps a signal from the first comparison circuit or the second comparison circuit.

Abstract: A signal detector includes, in part, first and second peak detectors, a comparator and an amplifier. The first peak detector generates a first signal in response to receiving an incoming signal. The second peak detector generates a second signal in response to receiving a threshold signal. The comparator generates an output signal representing the detected signal in response to the first and second signals. The amplifier amplifies the difference between the second signal and a reference voltage and, in response, generates a control signal that controls the gain of the first and second peak detectors. Each of the first and second peak detectors optionally include a differential amplifier and a pair of common-gate amplifiers each coupled to one of the output terminals of its associated differential amplifier. An RC network may be coupled to a common terminal of the first and second common gate amplifiers of each peak detector.

Abstract: An electric circuit for providing a selection signal being used to select a control value of a control variable which oscillates, at steady state, about a reference value about a first control value and a second control value with a first period duration comprises a first differential circuit which provides a first current being dependent on a difference between the first control value and the reference value. The electric circuit further comprises a second differential circuit which provides a second current being dependent on a difference between the reference value and the second value and a first node at which a differential current between the first current and the second current is formed. The differential current forms the selection signal indicating if the first control value or the second value is to be selected in order to minimize a difference between the reference signal and control variable.

Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy.

Abstract: A load drive device for driving an electrical load includes high-side and low-side transistors, and a switch. When the load is driven, each of the high-side and low-side transistors operates in a first mode where each of the high-side and low-side transistors is fully tuned on or in a second mode where each of the high-side and low-side transistors is controlled so that a load current flowing through the load is constant. When the load is driven, there is a first state where the high-side transistor operates in the second mode and the low-side transistor operates in the first mode and a second state where the high-side transistor operates in the first mode and the low-side transistor operates in the second mode. The switch switches between the first and second states to distribute heat generation between the high-side and low-side transistors.