Abstract: A depletion type n-channel MOS transistor (hereinafter referred to as “D-type NMOS”) as a MOS transistor of a SOI structure is disposed between a plus side power supply terminal of a CMOS circuit and a plus side terminal of a power supply unit so as to connect a source thereof to the pulse side power supply terminal of the CMOS circuit, to connect a drain thereof to the plus side terminal of the power supply unit, and to input to a gate thereof a voltage such that even if the voltage of the plus side terminal of the power supply unit exceeds the upper limit of the operation voltage of the CMOS circuit, the source of the D-type NMOS is equal to or lower than the upper limit of the operation voltage of the CMOS circuit, and the same voltage as the voltage of the plus side terminal of the power supply means when the voltage of the plus side terminal of the power supply means is the vicinity of the lower limit of the operation voltage of the CMOS circuit.

Abstract: A programmable transducer device that includes a signal source (e.g., a sensor) and a transducer output to output a transducer output signal and to receive a control signal from an external control unit. The control signal is superposed on the transducer output signal, and is detected at the transducer output from a resultant superposition signal by a detector circuit. The transducer output signal and the control signal may co-exist on the transducer output. Advantageously, providing a programmable transducer device that is actuated by control signals conducted through the transducer output and does not need to be switched over to a special receiving state, ensures the uninterrupted transmission of transducer output signals even while the control signals are received by the programmable transducer device. In addition, no additional signal path is required for programming.

Abstract: A race logic circuit of the present invention includes: a WTA circuit for receiving an operand logic signal and outputting only a high signal which is the first to arrive among the operand logic signals; plural race lines for inputting the operand logic signal into the WTA circuit; a clock distribution line having plural delay devices connected in series, both ends of the respective delay devices being connected to a triggering line, the clock distribution line receiving an external clock and outputting a triggering signal into the triggering line; and plural operand logic signal input switches which are triggered by the triggering signal output from the triggering line, for deciding whether to input the operand logic signal into the race line. According to the race logic of the present invention makes it possible to compose various logic circuits. Especially, when realizing the race logic circuit as integrated circuits, time delay due to the transistors can be removed during the logic operation.

Abstract: There is provided a signal detection circuit capable of detecting a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. The signal detection circuit includes a peak hold circuit, a constant potential setting circuit, and a comparison circuit. The peak hold circuit holds a peak value of an input signal at a given node. The constant potential setting circuit always returns the potential at the given node changed by holding the peak value by the peak hold circuit to a constant potential at a time constant greater than the potential change caused by holding the peak value. The comparison circuit compares the potential at the node at which the peak value is held and which is slowly returned to the constant potential with a given reference level, and outputs the comparison result as a detection signal.

Abstract: A current limiting circuit to limit current including an input circuit to input an input voltage, a connecting circuit to connect the input voltage to a current, and a current limiting circuit controlled by a constant voltage to limit said current.

Abstract: A pair of serial data signals having reciprocal signal levels are detected when a voltage of one of the serial data signals becomes larger than a voltage of the other serial data signal that is provided with an offset by a differential amplification circuit included in a signal detection circuit unit. A differential amplification circuit unit provides an offset for one of different predetermined constant voltages supplied thereto, and outputs signals by performing a differential amplification to the different constant voltages. An offset control circuit unit controls the offset provided by the differential amplification circuit unit so that voltages of the signals output by the differential amplification circuit unit coincide, and correspondingly controls the offset provided by the differential amplification circuit included in the signal detection circuit unit.

Abstract: A polyphase amplitude detector for detecting the amplitude of a polyphase signal. The polyphase amplitude detector includes means for generating differential pair signals. The differential pair signals are buffered and amplified and then AC coupled to the amplitude detector. The amplitude detector detects the amplitude of each phase of the polyphase signal and generates output signals which are used to control the amplitude of the polyphase signal.

Abstract: Peak capture circuitry for measuring a peak value of a waveform characterized by a first portion having a first rate of change and a second portion having a relatively faster rate of change. Peak stretching circuitry stretches a portion of the waveform as a function of time. Digital signal processing circuitry samples an output waveform of the peak stretching circuitry for determining the peak value. Thus, despite any steeply sloped portion, samples can be reliably taken throughout the waveform for calculation of peak value.

Abstract: A transmission signal which is output from a power amplifier is rectified by a first rectifying circuit and is then input to a first transistor of a voltage-to-current converting circuit, while the reference voltage is output from a second rectifying circuit and is then input to a second transistor of the voltage-to-current converting circuit. The output current of the first transistor is subtracted from the output current of the second transistor via a first current-mirror circuit, and a current that is proportional to the output voltage of the power amplifier is caused to flow to a two-terminal p-n junction electronic device. Then, a voltage that is proportional to the logarithm of the current is output from across the p-n junction electronic device.

Abstract: The present invention relates to a proximity IC card (PICC). More particularly, the present invention relates to and provides a detection circuit of a simple structure, which is easy to set up in a PICC and a proximity coupling device (PCD) for transmitting data to and receiving data from the PICC. This detection circuit is operative to detect a subcarrier signal sent from a PICC and superposed onto a carrier signal received through an antenna. Further, this detection circuit comprises a bias circuit for applying predetermined DC potential to a signal received from the antenna, a rectifier circuit for extracting a subcarrier signal superposed onto the carrier signal by rectifying a signal received from the antenna at a bias point, and an amplifier circuit for amplifying the subcarrier signal extracted at the bias point.

Abstract: An envelope detector circuit for use in controlling a RF amplifier is provided. The envelope detector circuit includes a first semiconductor device having a first input port that receives a first input signal and a first output port that provides current to charge a capacitor in response to the first input signal. The envelope detector circuit additionally includes a first current drain coupled to the first semiconductor device and the capacitor, where the first current drain conducts current away from the capacitor. The envelope detector circuit further includes a second semiconductor device having a second input port that is set to a biasing voltage and a second output port that is coupled to the first output port of the first semiconductor device.

Abstract: A differential envelope detector for detecting the envelope of a received differential signal. The received differential signal comprises first and second received voltages, and the differential envelope detector provides a differential output voltage comprising first and second output voltages, where the difference of the first and second output voltages is indicative of the envelope of the difference of the first and second received voltages. For full-wave rectification, the first received voltage is coupled to the non-inverting input port of a first differential amplifier and the inverting input port of a second differential amplifier, and the second received voltage is coupled to the inverting input port of the first differential amplifier and the non-inverting input port of the second differential amplifier. The output ports of the differential amplifiers are coupled to their input ports to provide negative feedback.

Abstract: An analog comparator architecture has improved immunity to single event effects and variations in input offset voltage. A conventional single analog comparator-based circuit is replaced with plural comparators, driving a “majority vote” logic block. The effective input offset voltage of the multi-comparator design is the middle one of the individual comparators' input offset voltages. A single event upset on any comparator may momentarily perturb its output into the incorrect state; however, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset. In addition, where a heavy ion strike on any comparator's bias current source causes a momentary loss of bias current, this upsets only one comparator, so that the output of the voting logic block is unaffected.

Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

Abstract: The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: Disclosed is a peak hold circuit wherein output current corresponding to the peak value of input current is obtained for input currents with little change in magnitude, at essentially higher speeds. Detected drain current and input current of a P-MOS FET are compared, a first reference potential is applied to an NPN transistor, and a second reference potential lower than the first reference potential by a predetermined voltage such that the NPN transistor and a PNP transistor are not simultaneously turned on, is applied to the PNP transistor. In the event that the detected current is greater than the drain current, the NPN transistor is turned on and the PNP transistor is turned off, in the event that the detected current is smaller than the drain current, the NPN transistor is turned off and the PNP transistor is turned on, and in the event that the detected current and the drain current are equal, the NPN transistor and the PNP transistor are both turned off.

Abstract: The invention relates to a transmitting device and a bus system for the serial data transfer of binary data between at least two communication stations, which are coupled to one another via an individual bus line. The transmitting device of a communication station has a circuit for waveform setting. The circuit for waveform setting generates, from a data signal to be transmitted, an output signal having signal edges which are as far as possible in the form of sinusoidal half-waves. In order to generate the signal edges in the form of sine half-waves, an oscillator, a clock counter and a parallel D/A converter are connected in series one after the other. The output signal at the output of the D/A converter has stepped edges. An optimized output signal having signal edges in the form of sine half-waves can be generated by means of suitable dimensioning of the reference elements of the voltage divider of the D/A converter and also by means of a smoothing filter connected downstream of the D/A converter.

Abstract: A signal reception circuit capable of detecting and receiving a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. A differential pair of reception signals DP and DM is detected by an HS_SQ_L circuit for low speed having high receiving sensitivity and an HS_SQ circuit for high speed having high speed response performance. In the case of a high-speed reception signal, a logical product of a signal HS_DataIn fetched by an HS differential data receiver and a signal HS_SQ indicating the result of signal detection by the HS_SQ circuit for high speed is supplied to a DLL circuit. In the case of a low-speed reception signal, an FS differential receiver is activated after the detection of differential pair of reception signals DP and DM by the HS_SQ_L circuit for low speed. A signal FS_DataIn fetched by the FS differential receiver is supplied to an FS circuit.

Abstract: There is provided a signal detection circuit capable of detecting a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. The signal detection circuit includes a peak hold circuit, a constant potential setting circuit, and a comparison circuit. The peak hold circuit holds a peak value of an input signal at a given node. The constant potential setting circuit always returns the potential at the given node changed by holding the peak value by the peak hold circuit to a constant potential at a time constant greater than the potential change caused by holding the peak value. The comparison circuit compares the potential at the node at which the peak value is held and which is slowly returned to the constant potential with a given reference level, and outputs the comparison result as a detection signal.

Abstract: An offset window detector that senses the sum of two signals and compares the result to a reference voltage for attenuating an offset voltage and producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset and a low power dissipation. The detector is part of the offset circuits in the I/Q path of a wireless receiver. The maximum input signal and the minimum input signal are the positive and negative peak values of the in-phase or the quadrature signal paths. They are generated by a peak detector. The offset signal can be estimated by the addition of the maximum input signal with the minimum input signal. This resulting offset signal is compared to the reference voltage to determine if the resulting signal is greater than a maximum reference voltage, less than a minimum reference voltage or within the maximum and minimum voltages. A reference voltage generator creates the desired voltages within a desired tolerance.

Abstract: A peak detecting circuit capable of accurately detecting a peak of a time discrete signal without increasing a circuit scale. The peak detecting circuit detects a peak of a waveform of a time discrete signal by calculating an approximate function which approximates the waveform of the time discrete signal. A peak of the approximate function is detected according to parameters of the approximate function so that the peak of the approximate function is estimated as the peak of the waveform of the time discrete signal.

Abstract: The present invention generally relates to a peak hold and calibration circuit, and more particularly, to a peak hold and calibration circuit for use in measuring the signals in a digital multi-meter implemented by using an integrated circuit (IC) and a capacitor, wherein said IC is connected to said capacitor; wherein said IC comprises an operational amplifier, and a switching circuit; wherein a first voltage is applied to one input terminal of said operational amplifier and the other input terminal of said operational amplifier is connected to the feedback network while the output terminal of said operational amplifier is connected to said switching circuit; wherein the output of said switching circuit is a second voltage and connected to said capacitor.

Abstract: A peak detector for measuring the voltage amplitude of low amplitude balanced digital signals. The N-diode peak detector uses the non-linear characteristics of a diode to convert a high speed low amplitude input signal into a DC voltage, linearly proportional to the signal amplitude (peak). A compensation circuit is designed to match the characteristics of a digital modulation signal and track over a large range of temperatures and signal amplitudes. The circuit can be used for digital and analog modulation signals. For analog signals, the peak detector uses a larger number of diodes or a reduced range.

Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.

Abstract: A peak detector circuit for detecting a peak output signal including an input circuit for inputting an input signal, a comparator for comparing the input signal and said peak output signal to generate a difference signal, a current source to generate a current in response to the difference signal, and a comparator to generate the peak output signal based on said current.

Abstract: Apparatus and methods for limiting transient current in an electrical power system in response to an over-current condition where a current-limiting electronic circuit breaker senses electrical current flowing in a circuit and isolates the electrical power source when the current is greater than a first preset value. During the time delay from the time that the electrical current increases above a first preset value and until circuit breaker opens, where the electrical current increases above a second preset value, greater than the first, the electrical current is limited to a maximum value.

Abstract: A peak detector for detecting a peak signal includes an input circuit to input an input signal, a track and hold circuit to hold the input signal and to output the peak signal, a comparator to compare the input signal and the peak signal to generate a clock signal, and said track and hold circuit to output the peak signal in accordance with the clock signal.

Abstract: A peak detector for detecting a peak signal includes an input circuit for inputting an input signal, a differential comparator for comparing the input signal with the peak signal to generate a difference signal, a diverting circuit to divert current between a first current path and a second current path based on the difference signal, and a comparator to accept current from the first current path and not from the second current path and to form the peak signal resulting from the current.

Abstract: A current-mode peak detector circuit is disclosed. The current-mode peak detector circuit includes an input transistor for receiving an input current that impresses a voltage on a control node, a pair of transistors for providing an output current in response to the voltage at the control node, and a decay control circuit for controlling the decay of the voltage at the control node such that the output current is representative of a peak value of the input current signal. A clamp circuit may be provided for clamping the input voltage to a predetermined level. All of the elements of the current-mode peak detector circuit may be realized using transistors for facilitating integration of the current-mode peak detector circuit on an integrated circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure.

Abstract: An apparatus and method for digitally decoding an asynchronous data signal is disclosed. Analog communication signals are converted into binary signal values. A negative peak register and a positive peak register store the negative and positive peak signal values corresponding to the negative and positive peak signal values of the analog communication signal. A negative peak comparator and a positive peak comparator compares the positive and negative signal peaks of the currently received binary signal value with minimum negative and maximum positive peak signal values stored within the negative and positive peak registers, and updates the negative and positive peak registers with any new minimum negative and maximum positive peak signal values. A subtraction circuit subtracts the positive peak signal value from the negative peak signal value to determine the magnitude signal value corresponding to the difference between a binary zero and one.

Abstract: Tracking percent overload signal as an indicator of output signal magnitude is achieved by measuring the percent of time the envelope of a varying modulated signal is above a predetermined programmable threshold. The technique is implemented by a level detector including an envelope detector along with circuitry for detecting when the envelope has exceeded the programmable threshold. The output of the level detector is sampled and fed to a counter which provides a digital output which indicates the percentage of time the envelope exceeds the set threshold.

Abstract: A variable power supply technique for use with a high efficiency line driver uses a signal peak amplitude to determine a start of a rise time for a power supply to begin supplying operating voltage to the line driver. This ensures that the voltage supplied to the line driver essentially tracks the output signal. A slew start delay circuit detects when the signal rises above a level that can be supported by a current power supply, and determines a variable delay for switching on a power supply to supply a higher voltage to the line driver. The advantages include reduced power usage, less heat dissipation, and the ability to select a primary power supply that outputs a lower voltage.

Abstract: A complex filter minimizing mismatch error by averaging the mismatch error by integrating the real and imaginary input signals using the same integrator. A further advantage is that, as compared to known devices, the complex filter uses fewer number of components thereby reducing the consumed power. The complex filter may be used in a complex bandpass sigma-delta modulator, thereby increasing the performance of the sigma-delta modulator. The complex filter used in a sigma-delta modulator analog to digital converter increases performance of the analog to digital conversion since the mismatch noise is minimized. The complex bandpass sigma-delta modulator analog to digital converter include any number of complex filter stages.

Abstract: A signal sorter for magnitude sorting among a number of signals is disclosed that allows for magnitude sorting of a number of signals in an ascending or descending ordered manner governed by the clock controlling signals. The sorter can generate sorted outputs fast enough for real-time applications and has a circuit structure suitable for implementation as integrated circuit devices. The sorter has a signal input section, maximum-deriving section, a feedback control and voltage output section and a sorted output section. All four sections are controlled by a set of timing clock input signals to manipulate the signal magnitude sorting.

Abstract: To realize a high frequency power detection circuit constituting a detection circuit by a GaAs semiconductor and thereby capable of realizing a small sized, low cost, and broad band detection circuit and suppressing variations in the detection characteristics due to variations in a pinchoff voltage of the field effect transistors, the invention is a detection circuit for detecting an envelope of a high frequency signal, comprising a field effect transistor to the gate of which the high frequency signal is input, a gate bias circuit for providing a gate bias voltage to the gate of the field effect transistor, a capacitor connected between the drain of the field effect transistor and the ground, and a load capacitor and a load resistor connected in parallel between the source of the field effect transistor and the ground, wherein a detection signal corresponding to the envelope of the high frequency input signal is output from the source of the field effect transistor.

Abstract: An apparatus for tracking a peak level of an input signal includes a comparator for comparing the peak level of the input signal with a reference peak voltage signal. A sample and block circuit is coupled to the output of the comparator and is capable of sampling a portion of the input signal. The sampled portion of the input signal is defined by a smart window (timing window) which is received by the sample and block circuit. The sample and block circuit controls a charge pump that determines the level of the reference peak voltage signal. A method of generating a reference peak voltage signal includes receiving an input data, generating a timing window based upon the input data to define a sampling portion in the input data, comparing a level of the reference peak voltage signal with a level of the sampling portion in the input data, and determining a level of the reference peak voltage signal based upon the comparing step.

Abstract: A peak detector that compares an input signal to a first reference voltage to produce a maximum sample signal, and compares the input signal to a second reference voltage to produce a minimum sample signal, wherein the maximum and minimum sample signals produce a sampling of the current input signal thereto to produce a maximum output signal and a minimum output signal, respectively. The detector compares the previously retrieved input signal value with a current input signal value. The current input signal is used as the maximum output signal if it is greater than a previous maximum output signal and providing the current input signal as the minimum output signal if it is less than a previous minimum output signal. The output provides signal level and offset signal information which, when gated with a predetermined clock signal, produces nonoverlapping phased output signals.

Abstract: A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents to be sorted, a winner-take-all (WTA) circuit unit for finding the maximum current, a feedback control and voltage output circuit unit for generating feedback control signals and output voltages indicating the maximum current, and an output circuit unit for outputting sorted currents. A plurality of input currents are simultaneously input to the input circuit unit and the sorted results are output in a time-shared manner on the output circuit unit.

Abstract: A multi-input comparator determines a minimum or maximum signal value in a given set of signal values. In an illustrative embodiment, a multi-input comparator includes a number of interconnected inversion circuits, with each of the inversion circuits having an input node associated therewith. The input node of each of the inversion circuits is coupled to an output of at least one of the other inversion circuits. As a result, after activation of the inversion circuits, the voltages at the input nodes are indicative of the relative magnitude of the signal values previously applied thereto. The inversion circuits may be constructed using, for example, single-inverter or multiple-inverter building blocks. Additional inputs can be provided by replicating the corresponding single-inverter or multiple-inverter blocks.

Abstract: A bipolar peak detector that maintains the charge on its capacitor longer than prior art peak detectors can due to the discharging thereof that occurs during long periods of reception of only a single value in the received signal, e.g. a long string of zeros, by substantially exactly duplicating, i.e., duplicating to within manufacturing tolerances, the current that is leaking out of the capacitor and injecting the duplicate current into the capacitor.

Abstract: An apparatus for detecting peaks of positive and negative polarity in an information signal. The apparatus comprises a first peak detector means for detecting the positive peaks and a second peak detector for detecting the negative peaks. The first peak detector means comprises a first capacitor, and has an attack time for charging the first capacitor (32) and a decay time for discharging the first capacitor, the attack time being shorter than the decay time. The first peak detector has an output for generating an output signal (42) having a first output signal value when the first peak detector is in a charging state for charging the first capacitor and having a second output value when the first peak detector is in a non-charging state.

Abstract: The present invention provides a peak and bottom detecting circuit including a current source for charging or discharging the capacitor, a switch for connecting the current source to the capacitor, a comparator for comparing a potential of a connection node between the switch and the capacitor, and a potential of an input signal with each other, and for turning the switch on/off in accordance with the result of the comparison, a buffer for buffering the potential of the connection node between the switch and the capacitor, and outputting an output signal, and a damper for comparing the potential of the output signal and the potential of the input signal and reducing the current allowed to flow from the current source as the potential difference becomes smaller.

Abstract: A gain control arrangement is suitable for controlling the gain of a variable gain amplifier in dependence on the difference between the actual magnitude and the desired magnitude of a read signal provided over an optical data carrier read channel. The amplitude of the read signal is sampled at periodic sampling points to determine an envelope value based on the sample value at a sampling point and an envelope value at a preceding sampling point, and a gain error value is derived from the difference between that envelope value and a desired envelope value.

Abstract: A peak detector for a maximum likelihood decoding system, using an automatic threshold control (ACT), and a method therefor are provided. In the peak detector, positive and negative peak values are detected from an input signal having digital information, based on positive and negative threshold values, and then each threshold value is evaluated according to positive and negative values of the input signal, to reset each threshold value to a predetermined value based on the detected peak value having the opposite polarity thereto. Accordingly, data can be detected exactly, improving performance of Viterbi decoding.

Abstract: A reference voltage generation circuit which is capable of generating a reference voltage having multiple steps by using a periodic response characteristic of a chaotic circuit. The circuit includes a first sample/hold unit for sampling and holding a periodic output voltage V3 in accordance with a first clock signal CLK1 from an externally connected clock signal generation unit, a second sample/hold unit for sampling and holding an output voltage V3' from the first sample/hold unit in accordance with a second clock signal CLK2 from the externally connected clock signal generation unit, a non-linear unit for receiving voltage V4 from the second sample/hold unit and outputting a non-linear voltage V2 signal having a sawtooth-shaped transfer characteristic, and an addition unit for adding the non-linear voltage signal V2 from the non-linear unit and an externally applied voltage signal V1 and outputting the periodic output voltage V3.

Abstract: An interleaved digital peak detector has multiple acquisition pipes with each pipe receiving a common input signal. Each acquisition pipe receives a common sample clock signal that is delayed through an analog delay circuit for selectively delaying the sample time of each analog-to-digital converter in the pipe. Each pipe has peak detector that receives the digitalized output from the analog-to-digital converter and accumulates maximum and minimum peak values. A programmable decimator receives the sample clock signal and a decimation value for establishing an acquisition clock by decimating the sample clock signal as a function of the decimation value to trigger a latch circuit for storing the accumulated maximum and minimum values from the peak detector.

Abstract: A switched capacitor sorter based on magnitude includes a plurality of input units, a winner-take-all (WTA) circuit for finding a maximum voltage level, and an output unit. A plurality of input voltages are simultaneously input to the respective input units, and the sorted results are output in a time-shared manner.

Abstract: A circuit to generate a servo burst signal, including a circuit to generate a first differential signal and a second differential signal, a first half wave rectifier to rectify the first differential signal and to generate a first rectified signal, a second half wave rectifier to rectify the second differential signal and to generate a second rectified signal, a first peak detector to detect a first peak of the first rectified signal, a second peak detector to detect a second peak of the second rectified signal, and a circuit to generate the servo burst signal based on the first peak signal and the second peak signal.

Abstract: It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below "at-speed" frequencies.