Abstract: A circuit which detects the median peak of a burst of pulses. The peak value of each pulse in a pulse burst is detected and stored. The peak value of each pulse is then compared to the peak value of every other pulse and the results of the comparison are used to determined the median peak.

Abstract: A data slicer follows abrupt variations in level of the detection signal. The data slicer for converting a detection signal into a digital signal in a data transmission system includes a maximum value detecting section, a minimum value detecting section, a voltage shift-down section, a voltage shift-up section, and a binary encoding circuit. The maximum value detecting section detects the maximum value of the detecting signal, while the minimum value detecting section detects the minimum value of the detecting signal. The voltage shift-down section sets a minimum value which the minimum value detecting section should take according to the output voltage of the maximum value detecting section, while the voltage shift-up section sets a maximum value which the maximum value detecting section should take according to the output voltage of the minimum value detecting section.

Abstract: A peak amplitude detector for use in a synchronized position demodulator associated with a linear variable differential transformer. The peak amplitude detector adjusts for phase shift in the transformer and maintains the full bandwidth of the transformer. The detector obtains the maximum positive or negative amplitude of the sinusoidal signal at one of the secondary windings of the transformer by first counting either a positive or negative half cycle of the signal and then while down counting one half of the counted half cycle sampling the amplitude of the sinusoidal signal. The sampling ends when the count reaches zero.

Abstract: A method for tracking a received signal comprises the steps of setting (635) a counter (130) to a first value indicative of a first signal voltage, determining a center threshold of the received signal, and determining a number of center transitions of the received signal within a predetermined time period. The method further comprises the step of automatically decrementing (685, 695) the counter (130) to a second value indicative of a second signal voltage in response to expiration of a predetermined amount of time, wherein the second value differs from the first value by a predetermined amount determined by the number of center transitions of the received signal within the predetermined time period.

Abstract: A vertical ramp generator includes a voltage controllable charge current source and a switched discharge current source coupled across a ramp capacitor. A pair of comparators coupled to first and second reference potentials are supplied with the ramp capacitor voltage and drive a flip/flop, the output of which operates the discharge current source. A sync signal voltage is injected into the output of one of the comparators. Another comparator compares the ramp capacitor voltage with a third reference potential corresponding to the midpoint of the desired ramp voltage to control the switching of a pair of current sources that supply a square wave current to a correction capacitor which develops a DC correction voltage. The duty cycle of the square wave current is a function of the deviation of the ramp capacitor voltage from the third reference potential. The correction voltage controls the amount of current supplied by the charge current source.

Abstract: A signal processing circuit that is subject to signal chatter is provided with signal chatter-elimination circuitry. Prior signal processing circuitry included a peak voltage detector which received a data input signal and provided a peak voltage representation of the input signal and a threshold-comparator that provided a threshold-comparison signal of a first output voltage magnitude when the peak voltage representation was below a predefined threshold voltage and of a second output voltage magnitude when the peak voltage representation was above the predefined threshold voltage.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: A peak detector circuit operates to charge a capacitor to a level proportional to the peak input signal level. The charging circuit includes an emitter follower driver. The response time of the charging circuit is enhanced by coupling a constant current to the emitter follower output. The constant current acts to lower the emitter follower source impedance which operates to increase the rate of capacitor charging.

Abstract: A peak detector samples and holds amplitudes of pulses of a servo burst and includes a master peak detector for following a portion of a rising edge of each pulse until a peak amplitude is reached, and for decaying rapidly at a falling edge of each burst following the peak until a rising edge of a subsequent burst is intercepted at a point of interception, and for generating a control window extending from the point of interception of a rising edge to a peak value of each subsequent pulse; a slave peak detector enabled by the control window of the master detector for following the portion of the rising edge of each burst from the point of interception to the peak value, and for holding the peak value reached by the master detector during the control window, a holding circuit responsive to the slave detector and having a first, rapid time constant for rapidly acquiring a peak value of at least one initial peak of the burst, and having a second, slower time constant for adjusting the initially acquired peak val