Abstract: An output amplitude regulating circuit comprises a first MOS differential circuit, with a first MOS transistor connected between an output terminal of the first MOS differential circuit and a power supply. The circuit also includes a second MOS differential circuit having a first input terminal that receives a reference electric potential, and a second MOS transistor that is connected between the power supply and a second input terminal of the second MOS differential circuit, and is connected to a reference electric potential via a third MOS transistor and a current source. In the circuit, output terminals of the first and second MOS transistors are used to regulate an output amplitude from the output terminal of the first MOS differential circuit.

Abstract: A data slicer which effectively compensates for wobble and asymmetrical phenomena due to optical and electrical characteristics of a disk. The data slicer includes a comparator for outputting a pulse signal by comparing an RF signal detected by an pickup device with a slice reference value, a low pass filter for low-pass-filtering the pulse signal output from the comparator, a first differential amplifier for detecting the difference between the output of the low pass filter and a predetermined reference value (Vref), and providing the detected difference as the slice reference value of the comparator, a peak detector for detecting a peak value of the RF signal, a bottom detector for detecting a bottom value of the RF signal, and an average value detection portion for detecting an average value of the peak value detected by the peak detector and the bottom value detected by the bottom detector, and adding the detected value to the slice reference value of the comparator.

Abstract: It is an object of the invention to provide a peak detector with improved precision for low amplitude AC signals for a broad range of input frequencies.

Abstract: A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak and trough detect output signals, respectively. A peak level rate of change detector (17) is coupled to the peak detector circuit (13) for detecting a rate of increase in the voltage level of detected peaks and to the trough detector circuit (14) for controlling the trough detector circuit to detect troughs when the voltage level of detected peaks rises rapidly. Similarly, a trough level rate of change detector (18) is coupled to the trough detector circuit (14) for detecting a rate of decrease in the voltage level of detected troughs and to the peak detector circuit (13) for controlling the peak detector circuit (13) to detect peaks when the voltage level of detected troughs falls rapidly.

Abstract: A peak detector circuit (100) includes an output transconductance amplifier (102), a current rectifier (104) and an averaging circuit (108). The current rectifier includes an amplifier (115) which reduces input impedance of the current rectifier to increase the operating frequency of the peak detector circuit. An isolator (106) employs a current mirror (509) with a cascode transistor (512) having a bias potential which is dynamically adjusted to achieve accurate mirroring. An amplifier of a common mode feedback circuit (110) has improved linearity.

Abstract: In order to restore a clock signal that has been used for coding digitized signals transmitted on a transmission channel, such as a line, the case when the received signals are distorted, the times (ti) when the signals go through their maxima (M) are detected with precision through an analysis of a series of samples (Ep) taken from the signals received during a time "window" (W) positioned with reference to a local clock. A device determines the amplitude differences between the successive samples and compares the difference configuration as obtained with predetermined standard configurations representative of forms that are acceptable for the maxima. In case when the difference configuration corresponds to no recognized standard configuration, the frequency of the local clock is changed so as to re-establish a sufficient similarity with a standard configuration.

Abstract: To solve a problem that, as the number of signal sources for outputting peak values decreases, a peak output voltage decreases, and to improve detecting precision, there are provided a plurality of first buffer units ?Q.sub.11 .multidot.Q.sub.21 .multidot.M.sub.31 to Q.sub.13 .multidot.Q.sub.23 .multidot.M.sub.33 !, which are emitter-follower circuits, to each of which a signal is input, a plurality of second buffer units ?Q.sub.31 to Q.sub.33 ! which are respectively connected to the first buffer units and an output unit for outputting the detected peak signal.

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Abstract: In order to eliminate an erroneous peak detection caused by turn-on characteristics of switches, a signal generating circuit comprises a first switching device for controlling the output of a first signal, a second switching device for controlling the output of a second signal, and a comparator to which the first and second signals are applied, and either one of the first and second switching device is enabled by the output of the comparator to produce a signal having a higher or lower level than that of the other signal.

Abstract: A differential amplifier circuit includes a differential amplifier having inversion and non-inversion input terminals and input amplifiers each individually connected to one of these input terminals, serving to receive an input voltage within a certain range and output it as another voltage in a smaller range. The differential amplifier is of a kind using n-type and p-type MOS transistors with threshold voltages given respectively by V.sub.thn and V.sub.thp, and connected to a source voltage V.sub.DD and a reference voltage V.sub.ref. Input voltages to the input amplifiers within the range between V.sub.ref and V.sub.DD, are outputted within the range between (V.sub.DD -V.sub.thp) and (V.sub.ref +V.sub.thn), or preferably between (V.sub.DD -1.5V.sub.thp) and (V.sub.ref +1.5V.sub.thn).

Abstract: The present invention overcomes the shortcomings and deficiencies of the prior art by providing a circuit for processing an AC signal having a peak to peak envelope associated therewith, this circuit including structure for detecting the upper edge of the peak to peak envelope of the AC signal, structure for detecting the lower edge of the peak to peak envelope of the AC signal, structure for sampling the AC signal at a mid range upper point, and structure for sampling the AC signal at a mid range lower point.

Abstract: In respective comparators, a plurality of input voltages are compared with a comparison voltage that has been swept, and only the binary output of a D flipflop corresponding to the comparator that has exceeded the comparison voltage earliest is allowed to have "1", while the outputs corresponding to the rest of the comparators have "0". Therefore, it is possible to detect a maximum output by using the comparators of a normal CMOS construction and a binary-change detection means circuit constituted by logical circuits. Compared with the application of floating-gate MOS, this arrangement makes it possible to reduce costs, and also to easily carry out offset-voltage compensation for each comparator by using switched capacitors. As a result, in a maximum input detector which detects a maximum input from analog inputs through multiple channels by carrying out analog operations, it is possible to reduce costs, and also to improve detection precision.

Abstract: An inputted signal applied to an input terminal of a detecting circuit is rectified in a positive amplitude range thereof by a rectifier block and stored in a capacitor. In a negative amplitude range, the electric energy stored in the capacitor is discharged through a load block. The rectifier block and the load block have equal impedances, and hence a time constant when the capacitor is charged is equal to a time constant when the capacitor is discharged. A DC signal outputted from an output terminal of the detecting circuit has a level which is the same as the average power level of the inputted signal. The detecting circuit is capable of outputting a DC signal which is accurately representative of the power level of the inputted signal.

Abstract: A voltage detector circuit (10) for detecting voltage levels of a digital data bitstream has an input terminal (20) coupled to receive the digital data bitstream. A first peak detector circuit (40) coupled to the input terminal detects a positive peak voltage, and provides a first peak signal. A first differential amplifier is coupled to the input terminal and further coupled to receive the first peak signal, for providing a first difference signal. A second peak detector circuit is coupled to receive the first difference signal from the first differential amplifier, for detecting a peak voltage in the first difference signal and for providing a second peak signal. The first peak signal indicates the value of logical 1 levels in the bitstream, and the second peak signal indicates the relative value of logical 0 levels in the bitstream with respect to the logical 1 levels.

Abstract: A method for monitoring a serial transmission of digital data signals on two parallel data lines between mutually communicating signal processing devices in which the data signals are transmitted on the two data lines with mutually inverse signal levels. In order to ensure the operability of the input components of the signal processing devices, the signal levels of the signals which are received from the two data lines are compared individually or combined with at least one reference level limit which defines a limit of the permissible common-mode signal range for the operability of the signal processing devices.

Abstract: A method and apparatus for signal threshold adjustment that compensates for signal asymmetry which utilizes an algorithm to detect each side of an asymmetric signal independently to ensure that the proper signal detection point is used on both the high and low side of the asymmetric signal. In particular, the high side threshold is adjusted downwards a predetermined amount until detected, the high side threshold voltage is then recorded and reset to the maximum value. Correspondingly, the low side threshold is then adjusted upwards the predetermined amount until detected, the low side threshold voltage is then recorded and reset to the minimum value. The algorithm may be repeated to continuously monitor a signal. The gain of the read amplifier can then be accordingly adjusted by the controller such that it approximately equals the peak of the amplified reference burst to the predetermined value.

Abstract: An optical receiving circuit comprises a photodetector, a differential transimpedance amplifier, a peak detector, a resistor network circuit and a discriminator. The transimpedance amplifier receives a current pulse converted by the photo-detector and outputs a non-inverting voltage signal and an inverting voltage signal of the same level. A peak detector for detecting a peak value of the non-inverting voltage signal. A resistor network circuit make an additional operations between an output signal from the peak detector and the inverted voltage signal, and between the non-inverting voltage signal and the non-inverting voltage signal, thereby generating two complemental voltage signals, which have the same amplitude and cross each other at a middle point of the amplitude.

Abstract: The present invention relates to a circuit for supplying the extremum voltage among several input voltages, including, for each input voltage, a first bipolar transistor, the base of which receives the input voltage and the emitter of which is connected to a common output supplying the extremum voltage; a first current source for biasing the emitter of the first transistor; and switching means for disconnecting the first source from the first transistor when this transistor is blocked.

Abstract: A digital peak detector formed of a plurality of comparators for outputting signals which, in combination, can form a thermometer code signal, apparatus for distributing an analog input signal to an input of each of the comparators, a plurality of digital to analog converters (DACs), apparatus for providing an output signal of each DAC to another input of a corresponding comparator, and apparatus for applying a digital signal to an input of each DAC to establish a comparison level against which a corresponding DAC can determine an output signal level.

Abstract: A low voltage constant transconductance input stage is achieved with relatively simple design methodology. The approach uses current-mode techniques and is based upon the processing of signal currents, rather than handling the bias currents of input stages. Such an approach becomes universal and independent of the input stage transistor types (FET or bipolar) and their operating regions. Further, the arrangement considerably simplifies the design procedure of low voltage operational amplifiers. MOS and bipolar Op Amp input stages are described wherein almost constant g.sub.m is achieved which is independent of the common mode input voltage ranging from rail-to-rail.

Abstract: A peak detector having several novel detection modes including detecting a pair of peaks with opposite polarity and selecting whether or not the peaks must cross programmed thresholds to be detected. The novel detection modes together with several known detection modes are provided in one unit and can be selected by the user. A power down feature is also provided.

Abstract: A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit.

Abstract: A protection circuit inhibits saturation and damage of sensitive circuit elements when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multistep/subranging analog-to-digital/converters.

Abstract: A pulse detection system for detecting pulses of sufficient magnitudes using a control detector providing crossing indications of pulses going beyond a threshold value, a stored threshold crossing adjustable actuator representing at least portions of selected crossing indications previously stored therein but reduced in magnitude as controlled by a magnitude reduction controller acting over time. An output detector may be used to detect signals going beyond another threshold.

Abstract: The present invention overcomes the aforementioned shortcomings and deficiencies of the prior art by providing a circuit for processing an AC signal having a peak to peak envelope associated therewith, this circuit including structure for detecting the upper edge of the peak to peak envelope of the AC signal, structure for detecting the lower edge of the peak to peak envelope of the AC signal, structure for sampling the AC signal at a mid range upper point, and structure for sampling the AC signal at a mid range lower point.

Abstract: A correlation peak detector including an envelope detector, a peak-holder, a peak scaler, and a comparator detects the envelope of a correlator output signal, derives a peak threshold signal from the peak signal level produced by the correlator output signal, and compares the envelope of the correlator output signal to the peak threshold signal to produce a correlation peak detector output signal which indicates detection of a correlation peak. A minimum threshold signal is generated and provided to the comparator to inhibit detection of false peaks or noise. The comparator produces a correlation peak detector output signal which indicates occurrence of a correlation peak by producing a pulse whenever the magnitude of the envelope of the correlator output signal exceeds the sum of the magnitude of the peak threshold signal and the magnitude of the minimum threshold signal. Pulses in the correlation peak detector output signal may be used to synchronize receiver timing signals with a received signal.

Abstract: An accurate peak-to-peak detector, readily implemented in CMOS and consuming low power. The peak-to-peak detector includes a clamp portion (circuit) followed by a peak-detect portion (circuit), each of which circuits includes at least one active component (e.g., transistor). The clamp circuit receives an input signal having an alternating current (AC) component via an input coupling capacitor which outputs a voltage on a line to the peak-detect circuit. The clamp circuit includes either a passive load element (e.g., a resistor), or an active load element (e.g., a CMOS transistor), so that the clamp circuit bleeds current from the input coupling capacitor, and any slow drift in the DC level of the input voltage will be followed. The peak-detect circuit follows the voltage output by the coupling capacitor, and includes either a passive load element (e.g., a resistor) or an active load element (e.g.

Abstract: An extreme level circuit for determining an extreme level of a plurality of input levels includes a plurality of independent parallel branches (T4+M2+M5, T5+M3+M6) with intercoupled output terminals (MAX) from which the extreme level can be taken. Each branch has an input terminal (INA, INB) for receiving a respective one of the input levels, and includes a separate distortion compensation circuit (M2+M5, M3+M6) which is independent of the distortion compensation circuits of the other parallel branches.

Abstract: An enhanced peak detector circuit for the amplitude demodulation of an incoming amplitude modulated signal is provided. In its simplest form, the enhanced peak detector circuit includes a forward biased NPN transistor, a peak detecting segment coupled to the base-emitter junction of the transistor; and a peak holding capacitor leading from the collector of the transistor and connected in parallel to the peak detecting segment. The peak detecting segment includes a parallel connected peak detecting capacitor and a resistor. When the base-emitter junction of the transistor is conducting, both the peak detecting capacitor and the peak holding capacitor are charging. Conversely, when the base-emitter junction of the transistor is back biased, the peak detecting capacitor discharges through the resistor and the collector remains open such that the peak holding capacitor remains charged.

Abstract: An apparatus for detecting off-track positioning of a disk read/write head seeking a selected data track on a disk having data tracks with embedded servo burst patterns recorded thereon. The apparatus comprises a compare and select component, a charge redistribution A/D converter circuit and an off-track controller. The compare and select component compares and selects from among voltage values corresponding to the servo bursts a pair best representing track centerline as a first servo signal and a second servo signal and determines which of the servo signals is greater. The charge redistribution analog-to-digital (A/D) converter circuit determines if the normalized track position exceeds a position threshold representing a percentage of the normalized track position distinguishing on-track from off-track position through the use of an internal binary-weighted, switched capacitor array DAC and a comparator.

Abstract: A circuit is described for processing an input signal received from a bus of a computer. The circuit includes level identification circuitry to characterize the magnitude of the input signal and to generate a corresponding level identification signal. Level toggle circuitry is connected to the level identification circuitry to process the level identification signal and generate a level hold signal during spurious signal transitions in the input signal. The level toggle circuitry generates a level toggle signal at a predetermined point of the input signal after the spurious signal transitions have subsided. Level hold circuitry, connected to the level identification circuitry and the level toggle circuitry, processes the level identification signal, the level hold signal, and the level toggle signal. During spurious signal transitions in the input signal, the level hold circuitry maintains a high digital circuit output value in response to the level hold signal and the level identification signal.

Abstract: A peak and valley measuring circuit (40) featuring a single digital-to-analog converter (DAC) (100), a peak counter (110), a valley counter (120), and a comparator (130). The peak and valley measuring circuit (40) uses the peak counter (110) when detecting peaks of the recovered audio signal and the valley counter (120) when detecting valleys of the recovered audio signal. The DAC (100) is used in conjunction with one of the counters (110) or (120) depending on whether peaks or valleys are being detected, and is preferably a current-mode DAC.

Abstract: A method and apparatus for detecting a peak value of a waveform signal continuously inputted during a predetermined time period.

Abstract: A level measuring set for low-frequency signals with superimposed direct voltage includes a low-pass filter, a measuring rectifier, and a subtractor. A low-frequency measurement signal is supplied to the low-pass filter, which outputs a reference potential (U.sub.B) which corresponds to the direct voltage. The reference potential (U.sub.B) is applied to a reference point of the measuring rectifier. The measuring rectifier forms a positive and a negative direct voltage component (+U.sub.M, -U.sub.M) superimposed on the reference potential (U.sub.B) for the positive and negative half-waves of the low-frequency signal, respectively. The subtractor receives at inputs thereof the positive and negative direct voltage components (+U.sub.M, -U.sub.M) superimposed by the reference potential (U.sub.B) and emits a level measurement value of the low-frequency measurement signal.

Abstract: A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

Abstract: A peak detector for extracting pulses in a magnetoresistive sensor circuit while suppressing the recovery transients created by thermal asperities. The disclosed peak detector circuit is a simplified variation of the standard magnetoresistive sensor peak detector circuit. The signal differentiation is performed ahead of the usual amplification to remove transient pulse amplitudes before they can affect the AGC gain. The resulting differentiated signal is processed by a modified amplitude qualification circuit to extract data output pulses. The thermal asperity transient recovery period is eliminated without additional circuit complexity, leaving only the initial thermal asperity pulse effects to be corrected by any suitable relatively simple error correction code (ECC).

Abstract: A digital FM modulating apparatus includes a device for restricting modulation data between a lower limit data value and an upper limit data value which respectively correspond to a minimum allowable frequency and a maximum allowable frequency value of an FM modulated signal. The apparatus also includes a device for suppressing transitional variance in the restricted modulating data and a direct digital synthesizer for receiving the suppressed data and producing synthesized data corresponding to the FM modulated signal.

Abstract: A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.

Abstract: A circuit for detecting when peaks occur in an amplitude modulated electrical signal, and for measuring in real time the amplitudes of the detected peaks. The circuit delays the input signal a short time, and then notes when the input signal and its delayed version have the same amplitude, thereby to detect when a peak has occurred. The amplitude of the peak is then measured. This circuit and technique have particular advantages when used as part of a servo control system that positions a read/write head to accurately follow moving tracks of recorded data on magnetic tape, magnetic disks, optical disks, and the like.

Abstract: An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.

Abstract: A circuit which can be used to hold either the maximum or minimum voltage applied. A comparator compares the input voltage to the previous high or low and a set of two mirror circuits either charge or discharge a holding copacitor to the new value. A control circuit of transistor switches configures the circuit into either a maximum or minimum holding mode.

Abstract: A circuit calculating the minimum value comprising a plural number of pMOS, wherein source of the plural pMOS are connected to a power source with lower voltage than a drain, the drain is grounded through high resistance, in input voltage is connected to each pMOS, and a common output is connected to a drain of each pMOS.

Abstract: A transistor circuit for detecting and holding a peak or bottom level of an input voltage includes a first transistor connected between a first power line and an output terminal, a capacitor connected between the output terminal and a second power line, a second transistor supplied with the input voltage and producing a current responsive to the input voltage, and a current mirror circuit supplied with the current from the second transistor as an input current and discharging the capacitor with an output current. The output current of the current mirror circuit is preferably designed to be smaller than a charging current to the capacitor from the first transistor.

Abstract: A calculating circuit for outputting a maximum value based on a plurality of inputs. The circuit is comprised of a plurality of nMOS transistors connected in a parallel configuration.

Abstract: A voltage regulator is capable of providing multiple fixed outputs plus a user-selected output by the use of a window comparator circuit that produces one of three different possible outputs, depending upon whether an input control signal is above, below or within the window voltage range. Two of the outputs operate different switches within a feedback circuit for a multiplying operational amplifier, causing the amplifier to produce different regulated output levels depending upon which switch is operated. The third window output disables the operational amplifier and establishes a mode in which the regulated output is set by an external feedback circuit for another operational amplifier, with the external circuit connected across the circuit's input and output terminals.

Abstract: A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop V.sub.BE thereacross, a voltage source providing a voltage V.sub.CC coupled to one end of the electron flow path, a resistance R.sub.L coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation V.sub.i =V.sub.H -I.sub.i R.sub.L for i=1 to n where I.sub.i =(V.sub.H /R.sub.L)(1-e.sup.-i.alpha.) and V.sub.H =V.sub.CC -V.sub.BE and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.

Abstract: An information processing system comprises a sub-circuits, each performing a part of the processing of the information or data. The operation of the sub-circuits is synchronized by means of clock signals applied to clock inputs of the sub-circuits. The clock signals are derived from a system clock and are transferred to each sub-circuit via the sub-circuit or sub-circuits preceding that sub-circuit in the data processing chain. To avoid deterioration of the clock pulses while they are transferred between the sub-circuits, clock regeneration circuitry is arranged in the chain of sub-circuits. The clock regeneration circuitry is preferably integrated together with the data-processing sub-circuits.

Abstract: An analog signal processing circuit used to suppress unipolar transient effects and signal averaging. Two transistors and one capacitor are provided in series to sample and condition an input signal. An additional transistor is provided in parallel to the capacitor to provide further signal processing capabilities. The circuit can function as an analog signal average, suppressing unipolar transient effects and as a peak detector while using a conservative amount of fabrication material and can be operated with low power.

Abstract: A dc-coupled packet mode digital data receiver, for use with an optical bus uses peak detectors to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A dc compensator, responsive to outputs of the peak detectors, shunts dc or low frequency currents, corresponding to "dark level" optical signals, from the input of the receiver.

Abstract: A clock signal conditioning circuit (100) for use in a smart card (102) has an input node (112) for receiving an applied clock signal, an output node (126) for producing a conditioned clock signal, a rising/falling edge detector (118) for detecting edges in the received clock signal, a bistable device (122) for forming at the output node a clock signal in response to the edge detector, and a timer (120, 124) for inhibiting switching of the bistable device for a predetermined time (T) following detection by the edge detector of an edge. Such a clock signal conditioning circuit provides a conditioned clock signal which is substantially independent of variations in the duty cycle of the applied clock signal and is substantially immune to glitches in the applied clock signal.