Abstract: A multiplication circuit of minimized transfer error having a selector for inputting analog data to one of a plurality of sample hold circuits. The data input in the sample hold circuit is introduced to one of a plurality of multiplication circuits by a multiplexer with multi-input and -output. Data is not transferred between adjacent sample hold circuits.

Abstract: A track and hold signal processing system is capable of driving 256 gray scale active matrix LCD displays at speeds limited only by the electrical characteristics of the display. The quiescent power dissipated by the system is substantially less than known track and hold drivers due to separation of the tracking circuit from the hold circuit resulting in optimization of the tracking function.

Abstract: An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.

Abstract: A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output.

Abstract: A circuit which detects the median peak of a burst of pulses. The peak value of each pulse in a pulse burst is detected and stored. The peak value of each pulse is then compared to the peak value of every other pulse and the results of the comparison are used to determined the median peak.

Abstract: A high speed sample and hold circuit comprises an amplifier for producing an output current which is a linear function of an input voltage. A capacitor is responsive to the output current for producing an output voltage representative of the integral of the output current over a predetermined period of time. A switch selectively connects the amplifier to the capacitor during the predetermined period of time. A circuit for discharging the capacitor is also provided. A circuit for producing clock pulses controls the operation of the switch and the discharge circuit. A finite impulse response filter may be constructed around the sample and hold circuit.

Abstract: There is provided a potential data selection circuit suitable for use, e.g., in a device for driving a liquid crystal pane adapted for selecting an arbitrary one of a plurality of potential data to output the selected one. This potential data selection circuit comprises: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output them, and a decoder adapted to receive the selection data from the sample-hold circuit to decode them to output control signals. The potential data selection circuit further comprises a multiplexer including analog switches adapted to respectively receive at least two potential data, and responsive to the control signals from the decoder to control the operations of the analog switches to select any one of the potential data to output the selected one, and an output circuit adapted to receive the selected potential data to output a signal of a voltage of the selected potential data to the exterior.

Abstract: A phase detector comprises a ramp voltage generator for receiving a reference pulse of a constant frequency and an input pulse and producing a ramp voltage proportional to the phase difference between these pulses. A first sample-and-hold circuit samples the ramp voltage in response to a sampling pulse and holds the sampled voltage. To eliminate ripple component, a second sample-and-hold circuit is provided, which is also responsive to the sampling pulse for sampling a voltage from a constant voltage source and holding the sampled voltage. The voltages sampled by the first and second sample-and-hold circuits are input to a subtractor where the voltage difference between the two input voltages is detected. Ripple components generated by the two sample-and-hold circuits are cancelled out by the subtractor.

Abstract: A reference signal generator that operates in response to a digital control signal has an increased resolving power without the requirement for increasing the basic clock rate or increasing the bit capacity of a down counter by thinning a pulse from the basic clock signal each the down counter overflows so as to adjust the down-counting clock rate of the down counter. The down counter counts the higher-bit data of the digital control signal. The basic clock signal is multiplied by a decoded signal to obtain the adjustment of the down counting clock signal. The decoded signal is obtained by counting the overflow pulses from the down counter and decoding the counter output with the lower-bit data of the digital control signal.

Abstract: A new and unique multiplication circuit solves the problems associated with digital multiplication circuits which operate on digital operands only. The multiplication circuit according to the present invention uses negative feedback in conjunction with an operational amplifier to maintain the output voltage of the operational amplifier at a level which depends on the logic level of the digital input datum applied to the gate of a field-effect transistor in the negative feedback loop. This unique multiplication circuit is capable of directly multiplying digital data with analog data.

Abstract: A hold circuit has a purpose to provide a hold circuit capable of controlling a hold error of an analog hold in the minimum during transferring. A hold circuit keeps a voltage signal, whose voltage level is compensated by operational amplifiers Amp.sub.1 and Amp.sub.2, at capacitances C.sub.1 and C.sub.2 by two steps, and holding and transferring of voltage data is performed at the different timing. The accuracy is compensated, as well.

Abstract: Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.

Abstract: A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.

Abstract: A peak amplitude detector for use in a synchronized position demodulator associated with a linear variable differential transformer. The peak amplitude detector adjusts for phase shift in the transformer and maintains the full bandwidth of the transformer. The detector obtains the maximum positive or negative amplitude of the sinusoidal signal at one of the secondary windings of the transformer by first counting either a positive or negative half cycle of the signal and then while down counting one half of the counted half cycle sampling the amplitude of the sinusoidal signal. The sampling ends when the count reaches zero.

Abstract: In an autozero type MOSFET comparator, the spurious current induced by the high frequency input voltage can flow through the resistance of the reset switch to introduce an offset voltage error during the autozero mode. A canceler is used to prevent the spurious current from flowing through the reset switch. A T-network with two series capacitors and a shunt switch is used as the canceler. The spurious current is by-passed by the shunt switch and prevented from flowing through the reset switch placed at the output of the T-network.The spurious current canceler is particularly useful for a sub-ranging ADC, where the comparator is used also as a sample-and-hold circuit to hold the input voltage across the series capacitors by opening all the sampling switches, the reset switch and the shunt switch.

Abstract: An offset detecting circuit 10 includes: a sample hold circuit 12 for holding a reference voltage Vref; and a buffer amplifier 13 having two pairs of input terminals. The reference voltage Vref is applied to at least one input terminal of one pair of the two input terminal pairs, and an output signal of the sample hold circuit 12 and an output signal VDout of the buffer amplifier 13 are applied to the other pair of the two input terminal pairs of the buffer amplifier 13, respectively. Further, an output circuit is composed of this offset detecting circuit 10 and a signal voltage outputting circuit 20 configured in the same way as the offset detecting circuit 10. The signal voltage outputting circuit 20 corrects the offset of a signal Vin inputted thereto on the basis of an offset voltage V between the reference voltage Vref and the output voltage VDout supplied from the offset voltage detecting circuit 10.

Abstract: A wide-band sample and hold circuit comprising an input buffer for inputting an analog input signal and buffering the inputted analog input signal, 1/2 frequency divider for frequency-dividing a sample and hold clock signal by two and outputting a 1/2 frequency clock signal, first switching circuit for switching in turn an output signal from said input buffer to sample and hold condensers in accordance with the 1/2 frequency clock signal, second switching circuit for switching selectivel sample and hold signals from the sample and hold condensers in accordance with said 1/2 frequency clock signal and transferring or block the selectively switched sample and hold signals in accordance with an inverted sample and hold clock signal, and an output buffer for buffering an output signal from said second switching circuit and outputting the buffered signal as an output signal of the sample and hold circuit.

Abstract: An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Abstract: A power-on reset circuit includes a differentiator circuit, a sample-hold circuit and a reset signal generating circuit. The differentiator circuit differentiates a clock signal from an oscillator after a power supply is applied to a power supply terminal. The sample-hold circuit samples a power component only from the output of the differentiator circuit. When the power component exceeds a threshold voltage of the reset signal generating circuit, the reset signal generating circuit generates and provides a reset signal for a logic circuit during a certain period.

Abstract: A sample and hold circuit is arranged to have a common input bus line and a plurality of combinations of analog switches and capacitors connected to the command input bus line. The sample and hold circuit includes as features a signal feeding unit for sequentially feeding a sampling control signal to the analog switches and a preventing unit for preventing the plurality of analog switches from being made conductive at one time because of the delay of the sampling control signal.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: A transconductance push-pull amplifier (20) generates primary push-pull currents (I1, I2) corresponding to a voltage input signal (VIN). Current mirrors (42,44) generate secondary push-pull currents (I3, I4) corresponding to the primary push-pull currents (I1, I2). For sampling, both the primary and secondary push-pull currents (I1, I2, I3, I4) are applied to charge a capacitor (C3) in a current feed-forward arrangement with high slew rate and fast signal acquisition to produce a voltage output signal (VOUT). The capacitor (C3) is disconnected from the amplifier (20) and current mirrors (42,44) to hold the output signal (VOUT). Switching transistors (Q13, Q15) which are connected between the capacitor (C3) and the current mirrors (42,44) have substantially the same non-linear modulation characteristics as corresponding output transistors (Q7, Q8) in the amplifier (20).

Abstract: A sample-and-hold circuit device which includes a plurality of sample-and-hold circuits and a comparator/amplifier for comparing a reference potential with an output signal which is output from the plurality of sample-and-hold circuits so as to amplify a difference between these two signals. An output of the comparator/amplifier is fed back to respective control terminals of the different sample-and-hold circuits, each being provided as a level control signal. In another embodiment, a plurality of adding circuits are provided for adding the outputs of the plurality of sample-and-hold circuits and then comparing this value with an arbitrary reference potential, whereby a difference between the sum value and the arbitrary reference potential is amplified and fed back to the control terminals of the sample-and-hold circuits.

Abstract: A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Abstract: A voltage circuit, which provides a plurality of reference voltages, is formed from a resistive line having a first and second ends. The resistive line also includes a multiplicity of reference voltage tap points, and first and second sense points. The sense points are offset from the ends of the resistive line, and thus at least a plurality of the reference voltage tap points are located between the first sense point and the first end of the resistive line and another plurality of the reference voltage tap points are located between the second sense point and the second end of the resistive line. A plurality of other functional circuits, such as comparator circuits, are connected to various ones of the reference voltage tap points.

Abstract: A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator.

Abstract: A peak detector samples and holds amplitudes of pulses of a servo burst and includes a master peak detector for following a portion of a rising edge of each pulse until a peak amplitude is reached, and for decaying rapidly at a falling edge of each burst following the peak until a rising edge of a subsequent burst is intercepted at a point of interception, and for generating a control window extending from the point of interception of a rising edge to a peak value of each subsequent pulse; a slave peak detector enabled by the control window of the master detector for following the portion of the rising edge of each burst from the point of interception to the peak value, and for holding the peak value reached by the master detector during the control window, a holding circuit responsive to the slave detector and having a first, rapid time constant for rapidly acquiring a peak value of at least one initial peak of the burst, and having a second, slower time constant for adjusting the initially acquired peak val

Abstract: A waveform classification system uses a detector 10 for detecting an analog input x(t), as well as sampler 14 and quantizer 16 to convert this analog input into a series of digital values {J.sub.k-1, J.sub.k, J.sub.k+1 }. This series of digital values {J.sub.k-1, J.sub.k, J.sub.k+1 } is represented by a fixed number of quantized digital values. A collection of predetermined feasible values is held in a feasible set table 20. A waveform classifier 18 compares the digital series from the quantizer 16 to the predetermined series held in the feasible set table 20. The waveform classifier 18 has an output, f(Z.sub.k), that marks the data in the digital series as either high or low interest. Low interest data can either be eliminated or reduced in priority to improve the overall system performance.

Abstract: A peak detector circuit operates to charge a capacitor to a level proportional to the peak input signal level. The charging circuit includes an emitter follower driver. The response time of the charging circuit is enhanced by coupling a constant current to the emitter follower output. The constant current acts to lower the emitter follower source impedance which operates to increase the rate of capacitor charging.