Abstract: In a signal input circuit, an input signal integrating circuit integrates an input signal in only a predetermined integration period. A reference voltage integrating circuit integrates a reference voltage in only the predetermined integration period. A differential amplifier circuit amplifies a difference between an output signal of the input signal integrating circuit and an output signal of the reference voltage integrating circuit. The input signal integrating circuit may be a charge/discharge type integrating circuit which stores charges corresponding to the input signal in only the predetermined integration period and thereafter releases the stored charges before the next integration period. The reference voltage integrating circuit may be a charge/discharge type integrating circuit which stores charges corresponding to the reference voltage in only the predetermined integration period and thereafter releases the stored charges before the next integration period.

Abstract: The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

Abstract: The switch circuit has a replica switch connected to a main switch to reduce feedthrough otherwise resulting from parasitic capacitance of the main switch. In operation, the replica switch is always open so as not to interfere with the signals generated by the main switch. A track-and-hold amplifier (TH amp) having both open-loop linearization and feedthrough reduction yet requiring low power supply voltage and low power consumption. In one embodiment of the TH amp, two input buffers each receive a differential input and both generate two output signals, where the output signals from one input buffer are out of phase with the output signals from the other input buffer. Two switch circuits each receive one signal from each input buffer and each switch circuit generates an output signal that is accumulated in one of two hold capacitors, when the switch circuit is closed (i.e., track mode). When the switch circuits are open (i.e.

Abstract: A track-and-hold amplifier circuit capable of increasing hold mode isolation includes an input circuit to buffer an input signal coupled to a switching transistor. A clamping transistor couples to the base of the switching transistor, and a hold capacitor couples between the emitter of the switching transistor and circuit ground. A differential amplifier circuit has a first input for receiving a track signal and a second input for receiving a hold signal. When the differential amplifier circuit receives the track signal, the switching circuit closes to charge the hold capacitor. When the differential amplifier receives the hold signal, the switching transistor opens to store the voltage representative of the input signal on the hold capacitor and the clamping transistor clamps the voltage at the base of the switching transistor. Thus, the base emitter voltage of the switching transistor is zero volts, and the signal held by the hold capacitor is independent of the input signal.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Abstract: A very low voltage sampling circuit which is capable of a full ranging output when powered with a very low voltage, e.g., of about 1 volt. A pre-charge circuit is combined with a sample and hold circuit to avoid the need for low threshold switching devices in the sampling circuit, thus avoiding output droop due to the increased leakage of low threshold devices. The pre-charge circuit is placed between the sample and hold circuit and an output of the sampling circuit to `boost` the voltage level of the output of the sample and hold circuit to above a predetermined threshold voltage level. The pre-charge circuit includes an output voltage boost capacitor which is charged before the hold cycle of the sampling circuit. The negative node of the output voltage boost capacitor is charged to a reference voltage based on a range of correction for the output voltage, and the positive node is charged approximately to a level of the input signal itself.

Abstract: An integrated circuit sample-and-hold (S/H) circuit includes an amplifier offset compensation circuit for compensating for the D.C. offset of a buffer amplifier. The amplifier offset compensation circuit may include an offset determining circuit for determining an offset voltage generated by the buffer amplifier, and an offset correction circuit for generating an offset correction signal and coupling the offset correction signal to the buffer amplifier. The S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and a first field-effect transistor (FET) formed on the substrate. The first FET may have a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the first sampling capacitor during a sampling time and for disconnecting the input signal from the first sampling capacitor during a holding time.

Abstract: In a switched-mode power supply, when the controller and the switching device are encapsulated together with a heat sink, in which the drain of the switching device is connected to the heat sink, the heat sink and the paths to the various pins of the controller forms various parasitic capacitances which, when the switching device switches injects inordinately large currents into the pins of the controller. In the case of the D.sub.MAG input, this may result in throwing the switched-mode power supply out of regulation. The sample-and-hold circuit connected to the D.sub.MAG input includes an additional comparator for comparing the current on the D.sub.MAG input to an extra large current. If the current on the D.sub.MAG input exceeds this extra large current, the sampling switch of the sample-and-hold circuit is held open while a clamp circuit is engaged on the D.sub.MAG input.

Abstract: An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET.

Abstract: An interface circuit for a capacitive sensor capable of outputting a detection signal with high stability and reliability while suppressing to a minimum the influence of offset and temperature dependency onto the output signal. In a differential capacitance type sensor having a common electrode connected to the ground potential, an electric discharge redistributing method and impedance conversion technique are adopted for obtaining an output voltage which is in proportion to the inter-electrode relative displacement. A switching mechanism is provided for mitigating an offset voltage component contained in the output due to an input offset voltage of the operational amplifier. Further, the sensitivity of the capacitive sensor is increased with the temperature-dependent drift of the sensor output being suppressed by providing additionally a power source change-over switches for allowing the voltages sampled in response to predetermined clocks to be differentially amplified.

Abstract: At a sampling operation, an analog signal and an inverted signal thereof are respectively supplied to first and second sampling capacitor elements, DC components of input signals are supplied to first and second capacitors, and reference voltages are supplied to third and forth capacitors. At the time of the comparison operation, the reference voltages are respectively supplied to the first and the second sampling capacitor elements, the first and the third capacitors and the second and the forth capacitors are connected in parallel, respectively.

Abstract: A novel signal processing scheme comprises a digital to analog converter which is clocked at a first frequency, and a switched capacitor filter which receives input from the digital to analog converter and is clocked at a second frequency which is a multiple N times the first frequency. A preferred version of the present invention further comprises an analog signal sychronization circuit which allows the switched capacitor filter to oversample output from the digital to analog converter. The analog signal sychronization circuit comprises a sample and hold circuit, which receives input from the digital to analog converter and holds the input so that the switched capacitor filter can sample the same input N times, and a digital clock generator, which clocks the sample and hold circuit such that the sample and hold circuit only samples settled and valid output data from the digital to analog converter.

Abstract: A very low voltage sampling circuit which is capable of a full ranging output when powered with a very low voltage, e.g., of about 1 volt. A pre-charge circuit is combined with a sample and hold circuit to avoid the need for low threshold switching devices in the sampling circuit, thus avoiding output droop due to the increased leakage of low threshold devices. The pre-charge circuit is placed between the sample and hold circuit and an output of the sampling circuit to `boost` the voltage level of the output of the sample and hold circuit to above a predetermined threshold voltage level. The pre-charge circuit includes an output voltage boost capacitor which is charged before the hold cycle of the sampling circuit. The negative node of the output voltage boost capacitor is charged to a reference voltage, and the positive node is charged approximately to a level of the input signal itself.

Abstract: In an interface circuit connected to a capacitance type sensor having two sets of capacitors C1 and C2 whose capacitances are varied, this interface circuit is equipped with an OP amplifier A1 where a feedback/sampling capacitor C3 is connected between its output terminal and its inverting input terminal; and a holding capacitor C4 connected between a non-inverting terminal of the OP-amplifier A1 and a reference voltage source; one ends of the respective capacitors C1, C2, C3 are connected to the inverting input terminal of the OP amplifier A1; at timing .phi.1 of a switching cycle, the other ends of the respective capacitors C1, C2 are connected to a power source and the capacitor C3 is shortcircuited; at timing .phi.

Abstract: A sampling circuit which is capable of a full ranging output when powered with very low voltage supplies, e.g., of about 1 volt. A current copier function is added to a sample and hold circuit to avoid the need for low threshold switching devices in the sampling circuit, thus avoiding output droop due to the increased leakage of low threshold devices. A pre-charge circuit is placed between the sample and hold circuit and a current storage transistor to `boost` the voltage level of the output of the sample and hold circuit above the threshold voltage of the current storage transistor. The pre-charge circuit includes an output voltage boost capacitor which is charged before the hold cycle of the sampling circuit. The level of the voltage charged onto the output voltage boost capacitor is based on the threshold voltage of the current storage transistor.

Abstract: An active pixel sensing structure includes an array of pixel unit cells each of which an adapted to alternate between a light sensing mode wherein the cell outputs an image signal and a reset mode wherein the cell outputs a reset signal. The image signal is proportional to light incident on the cell, and the reset signal is proportional to a predefined reference potential. An improved readout circuit according to the present invention includes a first sample and hold component for receiving and storing the image signal, and second sample and hold component for receiving and storing the reset signal. A signal amplifier is provided for each sample and hold component. A switching circuit is operable between a first mode and a second mode. In the second mode, the first and second sample and hold components are operatively decoupled from the corresponding signal amplifiers while input terminals of the signal amplifiers are connected to a source of predetermined reference potential.

Abstract: A sample and hold (S/H) circuit with common mode differential signal feedback for converting single-ended signals to differential signals includes a feedback loop for the input switched capacitor circuit to ensure that the input common mode voltage for the differential amplifier is maintained at a known value during the hold phase of operation. The feedback loop consists of a three-input error amplifier which monitors the two voltages at the differential input terminals of the differential amplifier in relation to the common mode reference voltage and generates a feedback voltage which is applied to the input terminals of the input switched capacitor circuit during the hold phase of operation. If both of the differential input terminal voltages are either more negative or more positive than the common mode reference voltage then the feedback voltage generated by the error amplifier is made more positive or negative, respectively.

Abstract: A waveform shaping circuit free of error in the hold capacitor due to parasitic capacitance of the MOSFET transistor.

Abstract: In a current amplifier, a current obtained by holding an input current from an input terminal by a first current sample/hold circuit is added through a connection to a current obtained by inverting the input current by a current inverter to generate a current twice the input current. This current is alternately sampled and held by second and third current sample/hold circuits and alternately output to an output terminal.

Abstract: The objective of the present invention is to provide a type of sample-and-hold circuit free of the influence of parasitic capacitors.In the sampling state, charging/discharging are performed for hold capacitor C.sub.H1 at the sampling voltage, and, in the holding state, hold capacitor C.sub.H1 is cut off from the input voltage. Current flows through MOSFET 54 connected to hold capacitor C.sub.H1 for operation, and a voltage corresponding to the hold voltage is output. Nearly the same current flows through MOSFET 54 in the sampling state and the holding state, and the voltage variation at the terminal of MOSFET 54 in transition from the sampling state to the holding state becomes smaller. Consequently, the influence of the parasitic capacitance on the hold voltage can be reduced. As the potentials of the source terminal and the drain terminal of MOSFET 54 become nearly equal, the influence of the parasitic capacitance on the hold voltage can be further reduced.

Abstract: A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

Abstract: A sampling circuit for sampling an analog signal in accordance with a timing signal includes a sampling switching element having a CMOS configuration. The sampling switching element includes an n-channel transistor and a p-channel transistor connected in parallel. The drive power and the feedthrough voltage are substantially the same in the n-channel transistor and the p-channel transistor. The sampling circuit, for example, is continued with an image display device.

Abstract: A non-volatile two terminal programmable logic element and associated methods for charging and discharging are disclosed. The logic element includes one input and one output terminal, a first capacitor region, a second capacitor region, and a floating gate (transistor-type) structure. The first capacitor region does not permit tunneling. The second capacitor region permits tunneling between its respective electrodes when a predetermined voltage, substantially higher than the normal operating voltage is applied. The source is connected to the input terminal and one electrode of the first capacitor region. The drain is connected to the output terminal and one electrode of the second capacitor region. The floating gate is connected to the other electrodes of the first and second capacitor regions. A programmable logic device constructed from these elements and associated methods of programming and erasing such a device are also shown.

Abstract: Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.

Abstract: In a photodetector amplifier scheme, the invention compensates for variations in photodetector quiescent current by sampling the amplifier output and subtracting a controllable current from the input to the amplifier. When a chopper or other modulator is used on the optical signal, the samples are taken periodically during the chopping cycle. This sampled signal is processed by a combination of gain and low pass filtering. The result of this processing controls a current source which subtracts a significant fraction of the average quiescent current from the total detector current. In a typical application, the amplifier is of the resettable current integrator type. In this case, the invention makes it possible to use smaller integration capacitors resulting in larger signals than if the quiescent current were not reduced by the operation of the invention. The gain, frequency response, and range of compensated quiescent currents and can be altered by changing timing signals.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A method (701-717) and apparatus for providing a driver system requiring a reduced number of amplifier circuits. Load driving circuitry (205) is configured to include a single loop amplifier (401) for sequentially receiving multiplexed signals representative of the parameter values and effecting the output of such signals to corresponding loads. Sample-and-hold circuitry is coupled between the output of the loop amplifier (401) and load circuitry within the driver circuits (409, 429, 435) in an arrangement such that only one loop amplifier (401) is required in a multiplexed multi-input system.

Abstract: A circuit for generating a threshold voltage level from a time division duplex analog data signal. The circuit comprises a sample/hold circuit and an amplifier. The sample/hold circuit is arranged to sample the threshold voltage level during a reception interval and hold the threshold voltage level during a transmission interval. The amplifier includes an operational amplifier coupled to the sample/hold circuit for amplifying the analog data signal during a reception interval and amplifying the threshold voltage level during a transmission interval. A transconductance device is coupled to the operational amplifier, and a plurality of load legs are respectively coupled to a plurality of bias legs. A first selected pair of the respectively coupled load legs and bias legs is coupled to the transconductance device, and a second selected pair of the respectively coupled load legs and bias legs coupled to the output of the amplifier to provide the threshold voltage level.

Abstract: In order to eliminate an erroneous peak detection caused by turn-on characteristics of switches, a signal generating circuit comprises a first switching device for controlling the output of a first signal, a second switching device for controlling the output of a second signal, and a comparator to which the first and second signals are applied, and either one of the first and second switching device is enabled by the output of the comparator to produce a signal having a higher or lower level than that of the other signal.

Abstract: A sample-and-hold circuit is provided for a switched-mode power supply of the type having a transformer with a primary winding, an auxiliary winding and a secondary winding, with a switching transistor coupled in series with the primary winding and a sample-and-hold capacitor for storing a voltage proportional to an output voltage of the auxiliary winding and coupled to a controlled terminal of the switching transistor in a feedback loop which normally operates in a closed-loop mode for switchably regulating the power supply. To prevent the feedback loop from being driven to an open-loop or "stuck" mode of operation, a discharge capacitor is provided which is switchably coupled in parallel with the sample-and-hold capacitor to discharge excess voltage from the sample-and-hold capacitor and thereby restore the feedback loop to its normal closed-loop operating mode.

Abstract: A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples. At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.

Abstract: A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

Abstract: A signal processor with a simplified circuit configuration provides an improved processing speed and can be realized of small size and at inexpensive cost. The signal processor includes signal holding means for holding output signals from plural signal sources (S1-S4), and signal mixing means (M31-M34) for mixing at least two signals among the plural signals held to output plural mixed signals. Since the mixed signals are less than the signal sources in number, the small number of signal lines can lead to an increased processing speed. Then the mixed signals corresponding to discrete signals from plural signal sources enables processing without substantially destroying information.

Abstract: An improved CMOS CDS circuit which can operate on 2.7 volts, provides increased noise immunity and can handle a 0.8 volts maximum signal input. The present invention provides internal capacitors to isolate the input pads. The present invention also provides switches and capacitors to perform a sample and hold function on every pixel value.

Abstract: In a sample/hold circuit, a current switch generates a constant current in response to a control signal. A first current mirror circuit receives the constant current to generate first and second currents, and a second current mirror circuit receives the first current to generate a third current. A voltage buffer receives an input voltage at an input terminal to generate an output voltage at an output terminal. The voltage buffer is activated by the second and third currents. A hold capacitor is connected to the output terminal.

Abstract: An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

Abstract: A current mode track and hold(T/H) circuit is provided having a high degree of accuracy. The current mode T/H circuit includes an input node, and output node, a voltage controlled current source, and a switched integretor circuit. The input node is configured to receive an input analog current signal and a feedback current provided by the voltage controlled current source. The output node is configured to receive an output analog current signal generated by the voltage controlled current source. The feedback current is equal to the output current, and both are proportional to a control voltage generated by the switched integrator circuit. The switched integrator circuit operates in either a tracking mode or a holding mode in accordance with a received binary T/H control signal. In the tracking mode, charge produced by a difference between the feedback current and the input analog current is integrated by the switched integrator circuit.

Abstract: A correlated double sampling circuit comprising an input node comprising a first plate of input capacitor and an output node. A first plate of a feedback capacitor is connected to the output node and a second plate of the feedback capacitor is connected to a second plate of the input capacitor. An input transistor has a gate connected to the second plate of the input capacitor, a source connected to a first supply voltage rail, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. A reset transistor is connected between output node and the second plate of the input capacitor, and has a gate connected to a reset signal line.

Abstract: A low distortion track-and-hold circuit in which a simple, four-transistor amplifier makes the circuit characteristics independent of the source impedance, and compensates for unequal voltage drops caused by mismatched diodes. An additional pair of bipolar transistors is used to eliminate errors caused by switching transients coupled through the diodes. In the track mode, the differential output voltage between two sampling capacitors tracks the differential input voltage of the circuit. At the end of the track time, this differential output voltage is equal to the differential input voltage. During the hold period, the sampling capacitors are isolated from the differential input voltage. The voltages controlling the switching diodes reverse symmetrically during the transition from track to hold, resulting in a cancellation of any feedthrough of the switching transients to the sampling capacitor. Beta and temperature compensation circuits are also included in the differential track-and-hold circuit.

Abstract: A full differential sample and hold circuit for an analog to digital converter. The sample and hold circuit samples and holds the differential signal resulting from two input signals. The sample and hold circuit includes a comparator, two differential capacitors and a common mode sample and hold circuit. The comparator has two input terminals and an output terminal. Each of the differential capacitors corresponds to one of the input signals and has an input terminal adapted for selective coupling to the respective input signal. Each of the differential capacitors has an output terminal electrically coupled to a different input terminal of the comparator. The common mode sample and hold circuit is disposed between the input terminals of the two differential capacitors. In one embodiment, the common mode sample and hold circuit comprises two common mode capacitors.

Abstract: A circuit for detecting leakage voltage of a MOS capacitor, the detecting circuit including a timing control signal generator for generating a timing control signal; a sample/hold circuit for sampling and holding a first voltage, the sample/hold circuit comprising a switching circuit switched by an output of the timing control signal generator and being operatively coupled to a MOS capacitor; a monitoring capacitor for monitoring a leakage voltage of the MOS capacitor operatively coupled to the sample/hold circuit; a monitoring capacitor precharge circuit for holding a second voltage in the monitoring capacitor; and a leakage voltage detecting portion for detecting when a leakage voltage of the monitoring capacitor is below a predetermined value. The leakage voltage detecting portion is also capable of detecting what value the leakage voltage of the monitoring capacitor is, for example, when the leakage voltage is below the predetermined value.

Abstract: A bus to which a bus control circuit and at least one electronic circuit are connected is controlled by a) storing a signal level which is output to the bus when the bus is in an active state, and b) fixing the bus to the signal level stored in the step a) when the bus switches to an inactive state.

Abstract: There is provided a correlative double sampling (CDS) device which can effectively and efficiently remove noise from video signal. The CDS device includes at least two sample-and-hold circuits for sampling a video signal output from an image sensor and outputting a predetermined DC level signal, and a differential amplifier. The correlative double sampling device also includes a clamping circuit for DC-clamping a video signal output from the image sensor and applying the DC-clamped signal to the sample-and-hold circuits. At least two re-sample-and-hold circuits are provided for re-sampling the signal output from the sample-and-hold circuits. A level correcting portion is used for correcting the output level of one of the sample-and-hold circuits and one of the re-sample-and-hold circuits, and outputting a signal whose phase is synchronized with the output of the re-sample-and-hold circuits.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.

Abstract: A fast differential sample-and-hold circuit includes two transistors controlled so as to be turned on or off. The output signal of the circuit is recovered at the terminals of an output capacitor connecting the emitters of the two transistors. The sample-and-hold circuit includes additional circuitry having two dynamic current generators and an additional capacitor which make the current flowing through the transistors constant when they are on. To this end, the two dynamic current generators are modulated by differential current which is output by the additional capacitor and the variations in which reproduce the current variations which appear in the output capacitor.

Abstract: A current cell for switch current circuits includes first and second MOS transistors connected in series between a constant current source and a reference ground. The first MOS transistor has its drain coupled to the constant current source and the second MOS transistor has its source coupled to the reference ground. Each of the two MOS transistors has a respective first and second switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current is applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor memorizes a gate voltage corresponding to the input current, constant current source current and a clock feedthrough error. A channel effect is purposely induced in the second MOS transistor to a degree sufficient to compensate for, and correct, its clock feedthrough error.

Abstract: A device for copying a voltage (Ve) comprises a pair of series-connected MOS transistors, their sources forming a common point. The voltage (Ve) to be copied is applied between the gate of the first MOS transistor of the pair and a reference. Means are provided to inject a flux of electrons at a common point. A storage capacitor has a first terminal connected to the drain of the second MOS transistor and a second terminal designed to be biased. Means dictate a potential at the drain of the second MOS transistor and then let it vary so that the flux of electrons is stored in the storage capacitor while at the same time decreasing in the second MOS transistor to the benefit of the first one. The copied voltage Vs is available, after stabilization, between the first terminal of the storage capacitor and the reference. Application in particular to circuits for the reading of charges generated in a photosensitive matrix or photosensitive linear array.

Abstract: Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories where the second current memory has a plurality of scaled outputs which feed switching arrangements. Resistors are provided in the current memories, the resistance of the resistors being equal to the "on" resistance of the switching arrangement multiplied by any multiplying factor applied to this output to which the switching arrangement is coupled.

Abstract: A current copier is disclosed having a reduced transconductance at the output to reduce the corresponding amount of deviation of the current sample. The disclosed current copier may be implemented on an integrated circuit and includes a residue circuit for receiving an input current at an input node during a first operating cycle, for generating an estimate current corresponding to the input current, and for generating a residue current from the input current and the estimate current; and a first current copier for storing the residue current during the first operating cycle, and for generating an output current from the stored residue current during a second operating cycle.

Abstract: The present invention is an apparatus for storing a voltage level within a storage element such as an EEPROM. The apparatus includes a track and hold circuit that receives the voltage level to be stored and an integrator that determines a target voltage to be applied to the storage element representative of a voltage level less than the received voltage level. The apparatus further includes a voltage ramp circuit that applies a voltage ramp signal to the storage element for increasing an amount of voltage held in the storage element while simultaneously reading a voltage level of the storage element to determine whether the voltage of the storage element matches the target voltage and a comparator that deactivates the voltage ramp signal when the voltage of the storage element matches the target voltage.