Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read circuit process determines a memory cell's threshold voltage by slowly ramps the control gate voltage of a memory cell being read and senses when the memory cell conducts. Another read circuit determines the threshold voltage of a memory cell using a source follower read process and a ramping circuit which slowly increases the source voltage. Still another read circuit includes a cascoding device connectable to a memory cell, bias circuit for biasing the memory cell in its linear region, and a load which carries a current that mirrors the current through the memory cell wherein the threshold voltage of the memory cell is determined from a voltage across the load. Read circuits disclosed can be used with analog memory cells, binary memory cells, multi-level digital memory cells, and other applications which require precise reading of threshold voltages.

Abstract: In a differential sample-hold circuit used in a serial-parallel type A/D conversion circuit containing a current-added type D/A converter, a pair of differential analog input voltages Vin1 and Vin2 are supplied to a non-inverting input and an inverting input of a buffer amplifier. An non-inverted output and an inverted output of the buffer amplifier are supplied through a pair of switches to one end of a pair of voltage holding capacitors having their other end connected to ground, respectively, and also to an input of a pair of closed-loop buffer amplifiers having their outputs for outputting a pair of differential sampled-and-held voltages.

Abstract: A very fast circuit for tracking an input signal and holding the value for digitization comprises a holding capacitor, two charging circuits connected to either side of the capacitor and extending between a constant current generator and a supply voltage. Each charging circuit has an input transistor responsive to an analog input signal and a load including the capacitor, as well as a series switching transistor responsive to a sample signal to permit a tracking mode or forcing a hold mode. The load includes a diode to effect a low resistance during the tracking mode when the capacitor is charging and a very high resistance during the hold mode when the capacitor is discharging.

Abstract: Prior art differential track and hold amplifiers produce an error voltage when transitioning from a track mode to a hold mode. An error voltage limits the resolution of a track and hold amplifier. A first circuit (44) and a second circuit (45) couple a differential voltage to the storage capacitor. Control signals applied to the first and second circuits (44, 45) generate parasitic currents through parasitic capacitances which couple to a storage capacitor of a track and hold amplifier (41). The control signals applied to the first and second circuits (44, 45) are forced to transition an equal voltage magnitude to produce identical parasitic currents through the parasitic capacitance. Identical parasitic currents affect common mode voltage but do not change the differential voltage stored on the storage capacitor. A clamping circuit (50) clamps the voltage transition of the control signals to produce identical voltage transitions.

Abstract: A method and apparatus for reducing reference frequency signal and/or clock switching noise in self-tuned integrated continuous-time filters. In the master-slave automatic tuning scheme, one or more sample-and-hold circuits sample and hold the frequency control signal and Q-control signal generated by the feedback loop(s) of the automatic tuning system. The control signals are held at a constant level for a period of time during which the reference frequency signal and/or clock signal are quiescent. At one or more predetermined times, the frequency control and Q-control signals are intermittently updated to automatically tune the slave filter.

Abstract: An active matrix liquid crystal drive circuit comprising an input-signal storage capacitor for storing an analog input signal, a differential amplifier which alternately presents a first operative state in which the output thereof is returned to the inverting input terminal thereof in a negative feedback manner and a second operative state in which the output is returned to the non-inverting input terminal thereof through a polarity inverting output buffer circuit in a negative feedback manner, and an output-voltage storage capacitor for storing an output voltage of the differential amplifier. In the first operative state, the voltage stored in the input-signal storage capacitor is applied to the non-inverting input terminal, and the output voltage which is returned to the inverting input terminal in a negative feedback manner is stored in the hold capacitor.

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

Abstract: A signal processor alternately outputs two input signals to a common output terminal every predetermined period to form a single serial signal. A capacitor for holding the input signal is provided on each input signal transmitting path. A buffer is provided at each of the preceding and succeeding stages of each capacitor. The turning on and off of these buffers is controlled by a single switch. The switch is controlled so that when one capacitor is supplied with the input signal, the other capacitor outputs a signal.

Abstract: There is provided signal node for receiving a signal, a reference node having a reference voltage, an operational amplifier having an input terminal and an output terminal, a first capacitor, and a second capacitor equivalent in capacitance to the first capacitor connectable by a combination of switches responsive to a control signal for connecting the first capacitor between the signal node and the reference node and the second capacitor between the input terminal and the output terminal of the operational amplifier, and to an inverted signal of the control signal for connecting the second capacitor between the signal node and the reference node and the first capacitor between the input terminal and the output terminal of the operational amplifier, the control signal and the inverted signal thereof being complementary to each other so as to be alternately effective.

Abstract: A telephone answering device (TAD) includes a remote access mode which is operative responsive to dual tone multi-frequency (DTMF) signals. At least three bandpass filters each receive an input signal from a telephone line interface provided in the TAD. A software controlled sampling section receives outputs from all the bandpass filters for sampling outputs from the bandpass filters, the sampling section including a multiplexer which receives the outputs from all of the bandpass filters, and a peak hold circuit coupled to an output of the multiplexer. An analog-to-digital converter receives an output from the peak hold circuit, and a digital controller receives the output of the analog-to-digital converter for controlling operations of the TAD in a remote access mode responsive to the detected DTMF signals. First and second ones of the bandpass filters have respective center frequencies corresponding to frequencies of respective DTMF signals and a third bandpass filter has a different center frequency.

Abstract: The analog signal input circuit comprises an analog-to-digital circuit and a conversion error measuring circuit. The conversion error measuring circuit comprises the following elements. A first switching device is provided between an analog signal input terminal and the sample/hold circuit for disconnecting the analog-to-digital circuit from the analog signal input terminal when measuring a conversion error value. A reference voltage generation circuit is connected via a second switching device between the first switching device and the sample/hold circuit. The correction reference voltage generation circuit generates a correction reference voltage in relation to the A/D conversion reference voltage. The second switching device is operated to connect the analog-to-digital circuit to the correction reference voltage generation circuit when measuring the conversion error value.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge amplifiers with self trigger and calibration capabilities to provide timing information with better than 20 nanosecond precision. The trigger threshold can be adjusted to provide energy discrimination. The chip has a sparse readout function in which only the channels which have received signals greater than a preselected threshold value are readout, thus providing fast data acquisition capabilities.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: A sample-and-hold circuit comprises an analog signal control circuit for supplying a potential of an input signal to one end of a hold capacitor, a first transistor having a base connected to the one end of the hold capacitor and operating in an emitter follower fashion, an amplifier having a second transistor having a base connected to an emitter of the first transistor, and a leak current compensating circuit including a third transistor having an emitter connected to a collector of the first transistor and a current mirror circuit for supplying to the base of the first transistor the same current as a base current of the third transistor.

Abstract: A semiconductor memory device 200 includes: a memory cell array 101 including a plurality of pairs of bit lines (BL, XBL), a plurality of word lines WL and a plurality of memory cells 100; a decoder 104 for decoding address information to activate one of the plurality of word lines WL in accordance with the address information; precharge circuits 105 for setting each of the plurality of pair of bit lines (BL, XBL) to a predetermined precharge potential; sense amplifiers 110; and potential difference transmission circuits 109 provided between the memory cell array 101 and the sense amplifiers 110. The potential difference transmission circuits 109 hold a potential difference V.sub.d0 between respective pair of bit lines among the plurality of pairs of bit lines (BL, XBL) and transmit the held potential difference V.sub.d0 between the pair of bit lines to a respective sense amplifier 110. The sense amplifier 110 amplifies the potential difference V.sub.

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract: A switched capacitor differential circuit switches first and second differential input signals (Vinp1, Vinp2) to respective inputs (A, B) of an operational amplifier (12) via respective first and second signal paths. Each signal path includes a coupling capacitor (13, 14) and two switching devices (2, 3 and 4, 5) to switch the input signals to charge the capacitors at a first phase of a clock signal and to discharge the capacitors onto the inputs of the amplifier at a second phase of the clock signal. In order to remove common mode spikes from transferring to the amplifier, a pair of comon mode capacitors (16, 17) are coupled between the inputs and a common node (15), which is coupled via a pair of switches (6, 7) to the first and second signal paths between the capacitors and the second of the switching devices so that the coupling capacitors are discharged relative to the common node.

Abstract: A method and apparatus is provided for comparing a first input voltage to a second input voltage. In one embodiment of the invention, a first input voltage is transformed into a first current flowing through a first transistor and a second transistor. A second input voltage is transformed into a second current flowing through the first transistor while the first current continues flowing through the second transistor. A difference current is developed which represents the difference between the first current and the second current. An indicator signal is generated which indicates the larger of the first and second input voltages based on the value of the difference current.

Abstract: A capacitative load driving circuit is provided in a liquid crystal display device and has an input selection circuit having a wide and effective voltage range of an input signal. The driving circuit changes over through source or emitter followers formed by two types of conductivity, for detecting as to whether or not a potential of the input signal is in an input voltage range of a differential amplifier circuit constituting a voltage follower after selecting at least one input signal through any of source or emitter followers.

Abstract: A sample/hold circuit which receives a voltage level at the input terminal thereof at a specific timing, and outputs the received voltage level in the form of a hold voltage. The sample/hold circuit includes an analog-to-digital converter for receiving a voltage level at the input terminal thereof, a memory element for storing the received voltage level in the form of hold voltage data, and a digital-to-analog converter for outputting the hold voltage data. The sample/hold circuit may be fabricated into a one-chip integrated circuit. The memory element may be a nonvolatile and reprogrammable memory.

Abstract: An analog input voltage is inputted to a first sample and hold circuit and a second sample and hold circuit is connected to an output of the first sample and hold circuit. The output of the first and second sample and hold circuits are inputted to a multiplexer which alternatively outputs the output of first sample and hold circuit or the second sample and hold circuit. When one of the first and second sample and hold circuits is refreshed, the output of the other sample and hold circuit is selected to be outputted from the multiplexer.

Abstract: A sample and hold flip-flop that includes a clock buffer circuit responsive to a first clock signal for producing a second clock signal and a third clock signal, wherein the second clock is delayed inverted replica of the first clock and wherein the third clock is a delayed inverted replica of the second clock signal; a CMOS inverter having an input and an output, wherein the output of said CMOS inverter forms the output of the sample and hold flip-flop; a first MOS transistor of a first type having a gate terminal connected to the first clock signal and a drain terminal connected to the input of the CMOS inverter; a second MOS transistor of the first type having a gate terminal connected to the second clock signal and a drain terminal being connected to the source terminal of the first MOS transistor of the first type; a first MOS transistor of a second type having a gate terminal connected to the second clock signal and a drain terminal connected to the input of the CMOS inverter; a second MOS transistor of

Abstract: A CCD signal read-out circuit is operative, upon receipt of a CCD signal outputted from a CCD, to output an output signal from which a reset noise has been removed through correlated double sampling. The CCD signal includes pixel periods each comprising a reset period, a succeeding feed-through period and a further succeeding pixel signal period.

Abstract: A sample circuit (10) maintains linear operation over frequency. A switchable diode bridge (12) passes the analog input signal when enabled to one terminal of a sample storage capacitor (14). The second terminal of the capacitor is coupled through a closed FET switch (16) to a reference node (18). Once the analog input signal is stored across the capacitor, the FET switch opens before the diode bridge disables. When the second terminal of the capacitor floats and prevents any further charge from altering the sample voltage across the capacitor. When the diode bridge is disabled, the sample voltage across the capacitor does not change. The sample voltage may be amplified and digitized for further processing in the cellular system.

Abstract: A sample-and-hold circuit comprises a first buffer stage, a first sampling switch, a sampling capacitor, and a feedback output amplifier for supplying a sampled output signal (Uout). The sampling capacitor is connected to an output of a second buffer stage, which has an input connected to earth. The output amplifier receives feedback via a third buffer stage and a second sampling switch and via a fourth buffer stage and a second sampling capacitor, which together with the first sampling switch are controlled by the same clock signal. The first sampling switch gives rise to clock feedthrough at the non-inverting input of the output amplifier. This clock feedthrough is cancelled by an equal clock feedthrough at the inverting input, so that the sampled output signal is freed from undesired clock feedthrough.

Abstract: A waveform shaping circuit shapes a waveform by comparing an output signal generated by an electromagnetic coil in response to a change in an incident magnetic flux to a reference voltage in a comparator. The circuit prevents waveform shaping error due to rapid fluctuations in the output signal. The waveform shaping circuit includes a high-pass filter that removes low-frequency components having frequencies not higher than a cut-off frequency from the output signal of the electromagnetic coil and that has at least two different attenuation characteristics with respective cut-off frequencies, a voltage limiting circuit for switching between the attenuation characteristics of the filter in response to the amplitude of the output signal of the electromagnetic coil by limiting the amplitude of the output signal to a maximum voltage, and a comparator for comparing the filtered output signal with a reference voltage and generating a shaped output signal in response.

Abstract: A sample-and-hold circuit is formed in bipolar transistor technology with the aid of clocked and complementary-clocked bipolar transistors in combination with a holding capacitor whose output terminal, in going from sample to hold phases of the clock, undergoes change in voltage .DELTA.V equal to the input voltage samples Vin applied to its input terminal during the sample phases (electrical bootstrapping operation). In particular, an input terminal of the holding capacitor is connected to a clocked input voltage device that ensures that, during the sample phases, the input voltage applied to the input terminal of the capacitor represents the input voltage being sampled, and that during the hold phases of the clock, the input terminal of the capacitor is electrically clamped. An output terminal of the holding capacitor is connected to one of the clocked transistors and to an auxiliary bipolar transistor whose base terminal is controlled by a complementary-clocked voltage-dropping device.

Abstract: A track and hold circuit including an input terminal V.sub.IN, a first node, a second node and a capacitor C.sub.H. A diode D connects between the first node and the input terminal V.sub.H. Circuitry coupled to the first node makes the diode conductive during track mode of operation, indicated by a clock CK being at a first state, and non-conductive during hold mode of operation, indicated by a clock CK being at a second state. A transistor Q3 is coupled between said first node and said second node. The capacitor C.sub.H is connected to said second node. The transistor Q3 is operative to charge the capacitor C.sub.H during track mode and to isolate the capacitor C.sub.H from the input terminal V.sub.IN during hold mode. Additional circuitry coupled to said transistor Q3 senses the clock shifting from said first to said second state to rapidly discharge the inherent base/emitter capacitor of the transistor Q3 to thereby cause rapid turn off of the transistor Q3.

Abstract: A low component count, high speed sample gate, and digitizer architecture using the sample gates is based on use of a signal transmission line, a strobe transmission line and a plurality of sample gates connected to the sample transmission line at a plurality of positions. The sample gates include a strobe pickoff structure near the strobe transmission line which generates a charge displacement current in response to propagation of the strobe signal on the strobe transmission line sufficient to trigger the sample gate. The sample gate comprises a two-diode sampling bridge and is connected to a meandered signal transmission line at one end and to a charge-holding cap at the other. The common cathodes are reverse biased. A voltage step is propagated down the strobe transmission line. As the step propagates past a capacitive pickoff, displacement current i=c(dv/dT), flows into the cathodes, driving the bridge into conduction and thereby charging the charge-holding capacitor to a value related to the signal.

Abstract: A non-linear circuit includes a first variable resistor one end of which is applied with an input signal, an amplifier whose inverting input is connected to the other end of the first variable resistor and whose non-inverting input is connected to ground, a second variable resistor one end of which is connected to the inverting input of the amplifier, a third variable resistor one end of which is connected to the output of the amplifier and the other end being connected to the other end of the second variable resistor, and a fourth variable resistor one end of which is applied with the input signal and the other end being connected to the third variable resistor.

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract: A sampling circuit which obtains a level of sampled-and-held signal which is determined with respect to a well-determined reference level V0, even though the input signal is a useful signal referenced with respect to a low-stability reference level. This is the case in particular for sampling of signals derived from charge-transfer photosensitive devices for which the dark level can vary. The circuit includes a sample-and-hold device (EB1) and an input via a capacitor (C1), with a reset circuit which periodically charges the capacitor (C1) to a value which is roughly the difference between the (variable) input reference level and the (fixed) output reference level. According to the invention, it is provided that the reset circuit comprises a looped amplifier (AD1) in which the loop (B1, EB2, B2) is designed to introduce a voltage level shift equal to the shift introduced intrinsically by the sample-and-hold device (B1, EB1, B2).

Abstract: Offset-compensated sample and hold arrangement to sample an input signal comprising at least an operational amplifier (A), a first capacitor (C1), a second capacitor (C2), a first switch (S110), a second switch (S211), a third switch (S210), a fourth switch (S111), a fifth switch (S120), a sixth switch (S121), a seventh switch (S220) and an eighth switch (S221), which switches capacitors and operational amplifier are interconnected in such a way and may be switched in such a way that during an offset-compensation phase the output voltage will only experience a very small voltage change.

Abstract: A circuit (10) for generating a voltage ramp signal (V.sub.RAMP) having minimum amplitude variation over a large frequency range has been provided. The circuit includes a comparator (40) for comparing a voltage across a ramp capacitor (32) with a reference voltage. From the result of this comparison, a sampling capacitor (16) is discharged during the time that the voltage ramp signal is less than the reference voltage and charged during the time that the voltage ramp signal is greater than the reference voltage. The resulting voltage across the sampling capacitor is held and fed back to a transconductance amplifier (20) which adjusts the current that charges the ramp capacitor thereby adjusting the peak amplitude of the voltage ramp signal.

Abstract: A sample and hold circuit to reduce hold error when analog data is held and transferred. The circuit includes a plurality of capacitors and inverters for guaranteeing level, selectively holds an input voltage at one capacitor by a first switching means, transfers charged voltage to a second capacitance by a second switching means and reduces data transfer time.

Abstract: A sample-and-hold circuit device capable of realizing a high-precision and high-speed operation, in which the output signal is independent of the error signal caused by a MOS transistor. The circuit includes a first switch coupled between an input terminal and a first internal terminal, a second switch coupled between the first internal terminal and a second internal terminal, a capacitor coupled between the second internal terminal and a reference potential, a buffer for transferring a potential held in the capacitor to an output terminal, a control signal generator for controlling the first switch to turn off after the second switch is turned off, and then to again turn on the second switch so as to replace an error charge into the second switch.

Abstract: A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length.

Abstract: This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.

Abstract: A circuit which can be used to hold either the maximum or minimum voltage applied. A comparator compares the input voltage to the previous high or low and a set of two mirror circuits either charge or discharge a holding copacitor to the new value. A control circuit of transistor switches configures the circuit into either a maximum or minimum holding mode.

Abstract: A RC filter circuit is disclosed which includes a first time constant circuit composed of a first resistor and a first capacitor, a switch circuit transferring, when conductive, an input signal to the first time constant circuit, and a pulse generator generating and supplying a pulse signal to the switch circuit to control conductive and non-conductive states of the switch circuit. The pulse generator includes a second time constant circuit composed of a second resistor and a second capacitor and responding a clock signal to generate the pulse signal which has a cycle period dependent on the clock signal and a pulse width dependent on a time constant of the second time constant circuit.

Abstract: A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: A transistor circuit for detecting and holding a peak or bottom level of an input voltage includes a first transistor connected between a first power line and an output terminal, a capacitor connected between the output terminal and a second power line, a second transistor supplied with the input voltage and producing a current responsive to the input voltage, and a current mirror circuit supplied with the current from the second transistor as an input current and discharging the capacitor with an output current. The output current of the current mirror circuit is preferably designed to be smaller than a charging current to the capacitor from the first transistor.

Abstract: An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor.

Abstract: The present invention discloses an improved analog-to-digital converter. A second sampling circuit samples the voltage difference between an analog signal and a reference voltage, before a first sampling circuit moves to a follow operation from a sample operation. Owing to pipelining by the first and second sampling circuits, even after the first sampling circuit moves to a follow operation, the difference between an analog signal and a reference voltage is still applied to a logical-level amplifier. The output of the logical-level amplifier, amplified to a logical voltage, is converted by a logic device into an A/D conversion output. Therefore, ADC differential non linearity error can be reduced.

Abstract: A track and hold circuit is disclosed which may be used in high speed analog to digital conversions. The circuit includes a control transistor which keeps the circuit's input transistor in a conductive state even when the circuit is in hold mode. As a result, the track and hold circuit achieves a high switching speed while minimizing input voltage spikes.

Abstract: A circuit for sampling monotonic input voltage changes and holding an output precisely derived from the sampled input change. The output change may be of the same polarity as the input, or inverted, and in the inverting mode of operation may exhibit highly accurate gain or attenuation. A single complementary metal-oxide-semiconductor (CMOS) embodiment may be configured to operate with positive or negative input changes and to present normal or inverted outputs, according to the application of various clock or control signals. Alternatively, subsets of that circuit provide subsets of the operating modes. The circuit operates by adding measured amounts of charge to, or removing it from a capacitor under the control of the input signal. Additional functional capabilities are capture and hold of input maximum or minimum, and accurate setting or restoration of the dc level of the output.

Abstract: A discrete-time signal processing system includes a signal sampling circuit controlled by a sampling signal generator in which a clock signal is derived from an oscillation signal having a higher frequency by means of a switchable frequency divider which is driven by a sigma-delta modulator. By alternately switching from one dividend n to the other dividend n+1 and vice versa, an effective dividend m, where n.ltoreq.m.ltoreq.n+1, is realized, so that a very fine frequency tuning can take place. The use of the .SIGMA.-.DELTA. modulator is advantageous in that the frequency spectrum of the sampled signal is not corrupted by the frequency spectrum of the sampling signal (clock signal) generated by way of the switching frequency divider.

Abstract: An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor.

Abstract: A reluctance sensor produces reluctance signals in response to passing slots in a rotating wheel. When a given signal exceeds a threshold, a DIG.sub.-- OUT signal is produced. When the signal falls to zero, the DIG.sub.-- OUT signal is terminated. The invention adjusts the threshold, based on the magnitude of the reluctance signals. Since the magnitude of the reluctance signals depends on wheel speed, the invention, in effect, adjusts the threshold based on wheel speed, yet without independently measuring wheel speed.