Abstract: A sampling and hold circuit that can suppress voltage variation at the input terminals, which are virtual grounds, of a differential amplifier, depending on the frequency of input signals. During sampling operation, a serial circuit composed of a capacitor C1, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q4, which is always turned on, is connected to an input terminal INP of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C3, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q9 is also connected to the input terminal INP. A serial circuit composed of a capacitor C2, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q5, which is always turned on, is connected to the other input terminal INM of a differential amplifier circuit 2.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In one such method, a plurality of sets of input signals is received, and a plurality of sets of corresponding output signals is transmitted. One set of the output signals is delayed with respect to another set by a delay period T_DLY. In another such method, the output signals are transmitted and received on the same semiconductor substrate.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Abstract: A track and hold circuit includes a MOS transistor switch and a holding capacitor, and a bulk potential of the MOS transistor switch is changed in phase with an input signal in order to reduce harmonic distortions.

Abstract: A clock signal producing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The edge timings are quantized to a predetermined number of states. A clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is adjusted based on the edge timings.

Abstract: A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.

Abstract: A receiving circuit including an amplifier for generating a receiving voltage signal, a comparator for generating a binary signal from the receiving voltage signal, and a logic maintaining circuit for receiving the binary signal and maintaining the binary signal at a shifted level for a predetermined period after the level of the binary signal is shifted. The logic maintaining circuit prevents noise pulses from appearing in a receiving signal.

Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal.

Abstract: Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely and quickly turned off and on in different modes.

Abstract: A sampling circuit includes a first sample hold means having a sample hold switch whose one terminal receives an input signal and a sample hold capacitor whose one terminal is connected to the other terminal of the sample hold switch, an amplifier circuit whose input terminal is connected to the other terminal of the sample hold switch and a horizontal selection switch whose one terminal is connected to an output terminal of the amplifier circuit and the other terminal of which is connected to a horizontal signal line. The output terminal of the amplifier circuit is connected to one terminal of a conduction control switch, and a first constant current load is connected to the other terminal of the conduction control switch. The conduction control switch is turned on when the sample hold switch is on and the horizontal selection switch is off.

Abstract: Methods and apparatuses for double-sampling a signal using an operational amplifier having dedicated unswitched connections to sample and hold circuits. In one embodiment, a circuit according to the teachings of the present invention includes an op-amp having four input terminals. Two of the input terminals are tied to ground and the other two terminals are coupled to S/H circuits through unswitched connections. In one embodiment, the S/H circuits are coupled to sample an input signal during different clock phases.

Abstract: An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.

Abstract: In order to reduce harmonic distortion, a track and hold circuit comprising a MOS transistor switch, a hold capacitor, and a voltage stabilizer for biasing bulk potential of the MOS transistor switch at a certain voltage is disclosed.

Abstract: Circuits and methods for generating signals representing the division or multiplication of two analog signals are incorporated into optical triangulation distance measurement systems. In one embodiment one of two analog voltage signals is used to generate a current signal. A capacitor is charged by the current signal. The voltage on the capacitor is compared with the other analog voltage signal and a signal is generated that has a time interval representing the division of the two analog voltage signals. In the application of the circuit and method to optical triangulation distance measurement the time interval signal is further processed to obtain distance measurement to a target.

Abstract: An electronic circuit comprising a sample and hold circuit (S/H) for sampling and temporarily holding an input data signal (Ui, Ii), comprising means (S; TS) for the sampling of a data voltage (U1) which corresponds to the input data signal (Ui, Ii), a capacitive element (C1) for temporarily holding the sampled voltage (UC), and means (CPR) for compressing the voltage range of the data voltage (U1) which is to be sampled. The electronic circuit is further provided with expansion means (EXP) for converting the sampled voltage (UC1) into a sampled output data signal (I0) in a manner such that it corresponds linearly to the input data signal (Ui, Ii). This is achieved, for example, by using a first field effect transistor (T1) for the compression means (CPR) and a second field effect transistor (T2) for the expansion means (EXP).

Abstract: A track and hold circuit including a MOS transistor switch, a holding capacitor, and a bulk potential of the MOS transistor switch changed in phase with an input signal in order to reduce harmonic distortions.

Abstract: A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

Abstract: A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.

Abstract: A circuit capable of reducing a consumption current is provided for a digital display device composed of unipolar TFTs. There is provided a latch circuit for holding a digital video signal. According to the latch circuit, when the digital video signal is inputted to an input electrode of a TFT (101), a non-inverting output signal is outputted from an output electrode of the TFT (101) and an inverting output signal is outputted from output electrodes of TFTs (102 and 103). Two line outputs of non-inversion and inversion are obtained. Thus, when a buffer located in a subsequent stage is operated, a period for which a direct current path is produced between a high potential and a low potential of a power source can be shortened, thereby contributing to reduction in a consumption current.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.

Abstract: A system and method to overcome or nullify a charge injection and clock feed-through error voltage caused by the turning-off charge of a switched element(s) in switched networks. A circuit for nulling a charge injection and clock feed-through error voltage includes, for example, two switched elements and a capacitor. The circuit can be used to replace any switch element in a switched network. The circuit may also include, for example, three switched elements and two capacitors.

Abstract: In order to reduce harmonic distortion, a track and hold circuit comprising a MOS transistor switch, a hold capacitor, and a voltage stabilizer for biasing bulk potential of the MOS transistor switch at a certain voltage is disclosed.

Abstract: Disclosed is a peak hold circuit wherein output current corresponding to the peak value of input current is obtained for input currents with little change in magnitude, at essentially higher speeds. Detected drain current and input current of a P-MOS FET are compared, a first reference potential is applied to an NPN transistor, and a second reference potential lower than the first reference potential by a predetermined voltage such that the NPN transistor and a PNP transistor are not simultaneously turned on, is applied to the PNP transistor. In the event that the detected current is greater than the drain current, the NPN transistor is turned on and the PNP transistor is turned off, in the event that the detected current is smaller than the drain current, the NPN transistor is turned off and the PNP transistor is turned on, and in the event that the detected current and the drain current are equal, the NPN transistor and the PNP transistor are both turned off.

Abstract: When a switching signal SW is at “H”, TGs (3a and 5b) are turned on and an input voltage IN is supplied to a capacitor (4a) and a differential input unit (10a) through TG (3a). At this time, a differential input unit (10b) is connected to an output unit (20) through TG (5b) and a voltage follower circuit is constructed. A voltage held in a capacitor (4b) is outputted as an output voltage OUT from an output terminal (7). When the switching signal SW is set to “L”, TGs (3b and 5a) are turned on, and a voltage follower circuit is constructed by the differential input unit 10a and output unit (20). A voltage held on the input side of the capacitor (4a) and differential input unit (10a) is outputted as an output voltage OUT from the output terminal (7).

Abstract: A track and hold amplifier for use in analog/digital-converters comprises, in succession, an input buffer, a pn-junction switch and hold a capacitor. A feedback is provided between the hold capacitor and the input buffer and a second pn-junction switch is provided to disable the feedback during the hold mode.

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

Abstract: An improved sample and hold circuit for analog-to-digital conversion. The improvement incorporates an asymmetric drive high gain operational amplifier to rapidly slew the input voltage for maintaining a high sample rate. The asymmetric drive high gain operational amplifier allows increased current to be delivered in a uni-directional manner. The input nodes of the high gain operational amplifier are pre-charged to a predetermined reference voltage which further enhances the acquisition time. The asymmetric drive high gain amplifier may be switched off to conserve power consumption.

Abstract: A rectifying integrator of an input signal with full output dynamics, relative to a voltage reference intermediate with respect to the dynamics of the input signal, includes a first line of integration having at least one integrator for integrating that portion of the input signal that exceeds the voltage reference, and includes a hold capacitor coupled in cascade to the integrator. The rectifying integrator includes a second line of integration, identical to the first line of integration, for integrating that portion of the input signal that remains below the voltage reference. An adder output stage generates an output signal equal to the difference between the voltages existing on the hold capacitors of the first and second lines of integration.

Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow.

Abstract: A translation circuit for transferring a differential voltage to a ground referenced voltage includes a differential input circuit, a sample/hold (S/H) circuit, and a compensation circuit. The S/H circuit includes a S/H capacitor, a series capacitor and a switch. The S/H and series capacitors are connected in series between an output line and a source of ground potential (GROUND). The switch shorts the bottom electrode of the S/H capacitor to GROUND when executing a translation operation. The differential input circuit receives the differential voltage and selectively provides the differential voltage across the S/H capacitor so that the top and bottom electrodes of the S/H capacitor have voltages V+ and V−, respectively. Parasitic capacitance tends to add charge to the S/H capacitor during the translation operation. The compensation circuit compensates for parasitic capacitance by removing, ideally, the same amount of charge from the S/H capacitor by the end of the translation operation.

Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow.

Abstract: An improved sample and hold circuit for analog-to-digital conversion. The improvement incorporates an asymmetric drive high gain operational amplifier to rapidly slew the input voltage for maintaining a high sample rate. The asymmetric drive high gain operational amplifier allows increased current to be delivered in a uni-directional manner. The input nodes of the high gain operational amplifier are pre-charged to a predetermined reference voltage which further enhances the acquisition time. The asymmetric drive high gain amplifier may be switched off to conserve power consumption.

Abstract: The subject invention pertains to a method and circuit design particularly useful for long time constant RC active or passive circuits in either continuous or discrete time domains. The subject invention also relates to a method and circuit design useful for long time constant RL active or passive circuits in either continuous or discrete time domains. The subject invention can find advantage in the mixed-signal, electronic circuit component market. The subject invention widens the application and the price/performance ratio of VLSI analog electronic circuits, and can be easily included in conventional circuit designs.

Abstract: A switch circuit having low charge dumping characteristics includes multiple parallel connected switching transistors and one or more associated cancellation transistors. The switching transistors perform basic switching functions within the switch circuit in response to a digital signal. During transitions of the digital signal, the switching transistors dump charge on an output node thereof due to parasitic capacitances within the devices. The cancellation transistor(s) dumps charge of an opposite polarity on the output node to cancel the charge dumped by the switching transistors. Two switching transistors are used for each cancellation transistor so that equal sized devices can be used throughout the switch circuit.

Abstract: An electronic circuit comprising a sample and hold circuit (S/H) for sampling and temporarily holding an input data signal (Ui, Ii), comprising means (S; Ts) for the sampling of a data voltage (U1) which corresponds to the input data signal (Ui, Ii), a capacitive element (C1) for temporarily holding the sampled voltage (UC), and means (CPR) for compressing the voltage range of the data voltage (U1) which is to be sampled. The electronic circuit is further provided with expansion means (EXP) for converting the sampled voltage (UC1) into a sampled output data signal (I0) in a manner such that it corresponds linearly to the input data signal (Ui, Ii). This is achieved, for example, by using a first field effect transistor (T1) for the compression means (CPR) and a second field effect transistor (T2) for the expansion means (EXP).

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.

Abstract: An analog-to-digital converter to convert an analog signal to a digital signal, including a sample-and-hold circuit to sample and hold the analog signal and to output a held signal, a buffer circuit to buffer the held signal to output a buffered signal, and a comparator circuit to compare the buffered signal with a reference voltage.

Abstract: An exemplary electronic circuit of the present include first and second buffers 34 and 38, which are preferably unity gain buffers. A first switch 36 (e.g., a NMOS transistor or a CMOS transmission gate) is coupled between the output of the first buffer 34 and the first terminal of a capacitor 40. The input of the second buffer 38 is also coupled to the first terminal of the capacitor 40. A second switch 42 is coupled between the second terminal of the capacitor 40 and a first voltage node Va and a third switch 44 is coupled between the second terminal of the capacitor 40 and a second voltage node Vb. This circuit can be used as an integrator in a number of applications.

Abstract: A sampling circuit includes a first sample hold means having a sample hold switch whose one terminal receives an input signal and a sample hold capacitor whose one terminal is connected to the other terminal of the sample hold switch, an amplifier circuit whose input terminal is connected to the other terminal of the sample hold switch and a horizontal selection switch whose one terminal is connected to an output terminal of the amplifier circuit and the other terminal of which is connected to a horizontal signal line. The output terminal of the amplifier circuit is connected to one terminal of a conduction control switch, and a first constant current load is connected to the other terminal of the conduction control switch. The conduction control switch is turned on when the sample hold switch is on and the horizontal selection switch is off.

Abstract: High-speed sampler methods and structures are provided to enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor Cs is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal Sin. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled to the capacitor's bottom plate to provide the output voltage Vout at the capacitor's top plate. Preferably, an output capacitor Co is coupled to the sampling capacitor Cs and charge from the sampling capacitor Cs is transferred to the output capacitor Co.

Abstract: A current driving circuit includes a first terminal electrically connected to a voltage source, a second terminal grounded, a signal line through which a signal current runs, a first switch, a second switch electrically connected to the signal line and further electrically connected in series to the first switch, a third switch electrically connected to the first terminal, a memory stage converting the signal current into a voltage and stores the voltage therein, a driving transistor, a load electrically connected between a source of the driving transistor and the second terminal, and a selection line electrically connected to the first to third switches. The signal line is electrically connected to a gate of the driving transistor through the first and second switches. The memory stage is electrically connected between a gate of the driving transistor and the second terminal. The first switch is electrically connected between a drain and a gate of the driving transistor.

Abstract: A driver circuit operating in stages that comprise a programming stage and a reproduction stage, the circuit comprising: a plurality current paths each of which passes through the circuit a current driven element, a transistor connected so as operatively to control the current supplied to the said element, a capacitor connected for storing an operating voltage of the transistor during the programming stage, and switching means which control the current paths, the arrangement being such that one of the current paths does not include the said element. No current is applied to the current driven element by the current controlling transistor during the programming stage and thus the overall power consumption is reduced. Furthermore, the circuit can be operated from a normal supply voltage rather than requiring a high bias voltage. During the programming stage, the circuit uses a current sink rather than a current source. Preferably, the current driven element is an electroluminescent element.

Abstract: A titanium alloy having a composition represented by the chemical formula Ti100−xM1x, wherein M1 is at least one element selected from the group consisting of Zr, Hf, Nb, Ta and V, x is atomic % or the sum of atomic % of the element(s), and x is 20 to 80 atomic %; and a titanium alloy having a composition represented by the chemical formula Ti100−x−yM1xM2y, wherein M1 is at least one element selected from the group consisting of Zr, Hf, Nb, Ta and V, x is atomic % or the sum of atomic % of the element(s), M2 is at least one element selected from the group consisting of Al, Sn, Mo, Cr, Ag, Au, Pd, Pt, Ni, Co, Fe, Si, Mn, B, Mm, Sc, Y, La, Ce, Pr, Nd and Sm, y is atomic % or the sum of atomic % of the element(s), and the sum of x and y is 20 to 80 atomic %.

Abstract: An improved sample and hold circuit for analog-to-digital conversion. The improvement incorporates an asymmetric drive high gain operational amplifier to rapidly slew the input voltage for maintaining a high sample rate. The asymmetric drive high gain operational amplifier allows increased current to be delivered in a uni-directional manner. The input nodes of the high gain operational amplifier are pre-charged to a predetermined reference voltage which further enhances the acquisition time. The asymmetric drive high gain amplifier may be switched off to conserve power consumption.

Abstract: A sample-and-hold amplifier circuit of the present invention has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. This allows to carry out the sampling so that the first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the &phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive. This allows that the voltage thus sampled is subjected to the operational amplification.

Abstract: A sample and hold circuit uses an auto-zero feedback technique to cancel the DC level of the input signal and reference this signal to a new baseline. The circuit is based on an op-amp with two separate feedback loops. The first feedback loop is connected to the same op-amp input as the incoming signal and contains a capacitor to store charge from this signal during sample mode and set the output voltage during hold mode. The second feedback loop uses an auto-zero feedback technique and contains an integrator having a predetermined reference voltage, thereby allowing the DC level of the input signal to removed without the need for capacitors in the gain path of the circuit. This allows the sample and hold circuit to extract an embedded time varying signal from the input voltage. It can be configured for a high gain, high pass function, without the need for large electrolytic capacitors in the gain path, removing the problems associated with such capacitors.

Abstract: A test mode reference potential generating circuit outputs a reference potential from an output node by activation of a test mode signal. When a sample signal is in an activated state, a transfer gate is turned on, and a capacitor stores the reference potential. When the test is being conducted, the transfer gate is turned off by inactivation of the sample signal, and thus the reference potential stored in the capacitor is output from a node. Thus, the semiconductor memory device according to the present invention can generate a stable reference potential during the test mode.

Abstract: A sample and hold circuit includes an operational amplifier and a plurality of switched capacitors, the switched capacitors introducing a closed loop gain of one-half for the operational amplifier.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier inputs with self triggering output. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are readout. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.