Abstract: A pipelined sample-and-hold circuit is provided. The circuit is pipelined such that processing of a held signal can continue into the next sample phase. Also, the pipelined sample-and-hold circuit includes a hold switch. The hold switch includes a boosted switch and dummy circuits. The boosted switch circuit is responsive to a boosted signal. The dummy circuits are arranged for charge injection cancellation responsive to another boosted signal that is a substantially inverse of the boosted signal.

Abstract: The invention is to provide a receiving end architecture comprising a variable gain amplifier, for outputting a pair of differential signals comprising a first signal and a second signal via a first and a second outputs respectively according to the receiving signal through adjusting the amplitude of the receiving signal; a mix-type sample-and-hold circuit for outputting a first sampled signal via a first end and a second sampled signal via a second end and then outputting the second sampled signal via the first end and the first sampled signal via the second end through performing sample-and-hold on the pair of differential signals; and an analog/digital converter coupled to the mix-type sample-and-hold circuit for generating a digital signal according to the first and the second sampled signals.

Abstract: A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.

Abstract: An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase. During a sample phase a first storage device is charged to a voltage value proportional to an analog input signal, which voltage value is provided for a further circuit part of the integrated circuit in the hold phase. A second storage device is charged during a first cycle to a voltage value which is inverted relative to a final voltage value of the first storage device in the hold phase. In the sample phase of the next cycle following the first cycle, the second storage device is connected to the first storage device in order to discharge the first storage device.

Abstract: A low distortion, high frequency switch circuit for selectively coupling an input voltage terminal to an output voltage terminal includes a switching device coupled to the input voltage terminal and the output voltage terminal, a charge storage device, and a first, second and third switches. While the switch circuit is turned off, the charge storage device, typically a capacitor, is charged to a precharge voltage. Then, when the switch circuit is to be turned on, the charge storage device is coupled between the control terminal of the switching device and the input voltage terminal. As a result, the switching device receives a constant gate-to-source voltage approximately equals to the precharge voltage and becomes conductive with a minimum and constant RON for all values of input voltages. In another embodiment, the switch circuit includes a pedestal voltage compensation circuit for reducing charge injection induced pedestal errors.

Abstract: A sampling device for high frequency signal that propagates in a propagation structure. The device comprises a first stage (A1, I1, C1) to sample a first signal at a first time t1 and at least one second stage (A2, I2, C2) in series with the first stage to take a second sample representative of the first sample, starting from the first sample, taken at a second time t2 greater than t1, the life-time of the second sample being longer than the life-time of the first sample.

Abstract: A method and apparatus are provided for tracking and holding a voltage. The method includes the steps of providing an external analog voltage on an input of the track and hold circuit during a tracking mode of the track and hold circuit, storing a representation of the sampled external voltage in a storage device of the track and hold circuit, blocking a signal path between the external voltage and the storage device during a holding mode of the track and hold circuit and clamping the input of the track and hold circuit to a predetermined voltage during the holding mode.

Abstract: An X-band capable track and hold amplifier capable of handling input frequencies of greater than 1 GHz, and as high as 15 GHz. The amplifier is built using a pseudomorphic high electron mobility transistor (PHEMT) process which gives high yield and uniformity.

Abstract: A system and method to overcome or nullify a charge injection and clock feed-through error voltage caused by the turning-off charge of a switched element(s) in switched networks. A circuit for nulling a charge injection and clock feed-through error voltage includes, for example, two switched elements and a capacitor. The circuit can be used to replace any switch element in a switched network. The circuit may also include, for example, three switched elements and two capacitors.

Abstract: A chaotic signal generator includes a set of elements connected together for generating chaotic signals. The connection scheme may correspond to the circuit generally referred to as Chua's circuit, particularly when implemented as a cellular neural network. Interposed in the connection scheme is at least one switch, such as a MOS transistor. Opening and closing of the switch causes variation in the chaotic dynamics of the generated signals. A command signal applied to the switch may correspond to a modulating signal for transmission on a channel, such as a high noise channel. The modulating signal may be a binary signal, and the command signal may be a switching signal having a frequency that increases or decreases depending on the logic level of the binary signal.

Abstract: The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.

Abstract: An integrated circuit having a sample-and-hold device is provided, which can be operated in successive cycles which each include a sample phase and a hold phase. During a sample phase a first storage device is charged to a voltage value proportional to an analog input signal, which voltage value is provided for a further circuit part of the integrated circuit in the hold phase. A second storage device is charged during a first cycle to a voltage value which is inverted relative to a final voltage value of the first storage device in the hold phase. In the sample phase of the next cycle following the first cycle, the second storage device is connected to the first storage device in order to discharge the first storage device.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A sampling circuit that continuously compensates for drift. The sampling circuit includes a primary sampler surrounded by two proximity samplers. The proximity samplers are used to detect data transitions that encroach on the primary sampler. By comparing the output of the proximity samplers with the primary sampler a determination can be made as to whether data transitions are encroaching on the primary sampler. If such encroachments are detected, the delay timing of the sampling operation may be increased or shortened to compensate.

Abstract: A system and method for sampling and holding a signal. The invention includes a novel input circuit for a track and hold circuit comprising a circuit Q1 for receiving an input signal including an input node, a first output node N1, and a path connecting the input and output nodes; a current switching circuit for applying a first current to the node N1 during a first mode of operation but not during a second mode; and a current source for applying a second current to the node N1 during both of the first and second modes. The value of the first current is determined such that the total current in the path is constant during the first and second modes. In an illustrative embodiment, the first mode is a track mode and the second mode is a hold mode.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: The invention relates to a current sample-and-hold circuit comprising several sub-circuits, in which a current signal is stored. At least one of said sub-circuits contains a switch. The inventive current hold-and-sample circuit is characterized in that each of the sub-circuits contains a linear resistor, which is connected in such a way that the current signal generates a voltage drop across the resistor, that each of the sub-circuits contains at least one inverting control amplifier, which sets an initial current of the circuit in a hold operational mode, thus inducing a voltage drop across the resistor, said voltage drop being substantially as great as the voltage drop across the resistor before the hold operational mode.

Abstract: A sample-and-hold amplifier circuit has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. Thus, sampling can be carried out so that first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the &phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive.

Abstract: A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that is indicative of a level of the second input signal. The comparing section is coupled with the input section and compares the first output signal and the second output signal to responsively generate a result. The comparing section includes a first comparing unit and a second comparing unit. The control section is coupled with the input section and the comparing section. Furthermore, the control section activates, when receiving an initial load signal, the first input unit, the second input unit, the first comparing unit, and the second comparing unit.

Abstract: A hold cell implementing a closed-loop, common mode negative feedback method is provided. The hold cell enables generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the hold cell is used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal is used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the hold cell in a low power oscillator is fully implementable in a CMOS process.

Abstract: This invention relates to circuitry for detecting peak levels of signals and particularly fast hold and sample peak detectors for analyzing signals of generally arbitrary wave shape and form having a high precision, high slew-rate, very short retention, and a low distortion. The circuitry comprising a comparator circuit comprising two signal inputs and a signal output, where the output signal depends from the difference between the input signals, a sample and hold circuit comprising switching means controlled by said signal output for sampling and holding means for holding the output signal, a compensation circuit for compensating residual currents comprising emulating means for emulating residual currents caused by said comparator circuit influencing the functionality of said sample and hold circuit, and an unload circuit comprising a clearing means for decreasing the output signal of said sample and hold circuit.

Abstract: A peak detector for detecting a peak signal includes an input circuit to input an input signal, a track and hold circuit to hold the input signal and to output the peak signal, a comparator to compare the input signal and the peak signal to generate a clock signal, and said track and hold circuit to output the peak signal in accordance with the clock signal.

Abstract: A sampling device for high frequency signal that propagates in a propagation structure. The device comprises a first stage (A1, I1, C1) to sample a first signal at a first time t1 and at least one second stage (A2, I2, C2) in series with the first stage to take a second sample representative of the first sample, starting from the first sample, taken at a second time t2 greater than t1, the life-time of the second sample being longer than the life-time of the first sample.

Abstract: A peak detector employs switched capacitor filtering to implement long time constant and variable attack and decay characteristics. In one embodiment, the peak detector includes a first switch, a rectifier, a first capacitor and a second switch in the attack path, and a third switch, a second capacitor and a fourth switch in the decay path. The peak detector further includes a third capacitor coupled to the attack and decay paths and having a capacitance greater than the capacitance of the first and second capacitors. In operation, the attack path is activated by alternately closing the first and second switches to sample the input signal and generate an output voltage at the third capacitor indicative of the peak voltage value of the input signal. The second circuit path is activated by alternately closing the third and fourth switches to decrease the output voltage at the third capacitor.

Abstract: The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple sampling units 2-1˜k. Each sampling unit has input terminals 1-1˜k and output terminals 3-1˜k. The values received at the input terminals are sampled, and the sample values are accumulated. Also, the accumulated sample values are generated at output terminals 3-1˜k. One holding unit 6 has an input terminal 5 and an output terminal 7, which are shared by the multiple sampling units. By multiplexing the outputs of the multiple sampling units, multiplexing unit 4 connects any output to the input of holding unit 6. Holding unit 6 holds the sample value and generates it at output 7.

Abstract: An X-band capable track and hold amplifier capable of handling input frequencies of greater than 1 GHz, and as high as 15 GHz. The amplifier is built using a pseudomorphic high electron mobility transistor (PHEMT) process which gives high yield and uniformity.

Abstract: A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

Abstract: The data slicer circuit has a first capacitor that holds a pedestal potential of a video signal; a second capacitor that calculates an average potential of signals existing in a period where a clock run-in signal of the multiplex signal is present and holds the average potential; and a comparator which compares the two held potentials. The comparator outputs a detection signal indicative of the presence of the multiplex signal when the potential held by the second capacitor is higher than that held by the first capacitor.

Abstract: A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Abstract: A detection system is provided. In one embodiment a silicon Compton recoil electron detector uses the Compton double scatter technique with recoil electron tracking to detect medium energy gamma rays from 0.05 to 10 MeV. Two detector layers are required; a silicon microstrip hodoscope and a calorimeter. The incoming photon Compton scatters in the hodoscope. The second scatter layer is the calorimeter where the scattered gamma ray is totally absorbed. The recoil electron in the hodoscope is tracked through several detector planes until it stops. The x and y position signals from the first two planes of the electron track determine the direction of the recoil electron while the energy loss from all planes determines the energy of the recoil electron. In another embodiment of the invention, the Compton double scatter technique with recoil electron tracking is used to detect x-rays from 300 to 5,000 keV.

Abstract: A sample-and-hold amplifier circuit of the present invention has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. This allows to carry out the sampling so that the first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the &phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive. This allows that the voltage thus sampled is subjected to the operational amplification.

Abstract: Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4.

Abstract: A sampling and hold circuit that can suppress voltage variation at the input terminals, which are virtual grounds, of a differential amplifier, depending on the frequency of input signals. During sampling operation, a serial circuit composed of a capacitor C1, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q4, which is always turned on, is connected to an input terminal INP of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C3, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q9 is also connected to the input terminal INP. A serial circuit composed of a capacitor C2, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q5, which is always turned on, is connected to the other input terminal INM of a differential amplifier circuit 2.

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: A filtered reference voltage is provided with improved PSRR without the use of a large capacitor. First and second reference voltages are generated, where the reference voltages are centered about an input reference voltage. A first small valued capacitor circuit samples a selected one of the first and second reference voltages. The selected one is determined by the comparison between the filtered reference voltage and the input reference voltage. A second small valued capacitor circuit is periodically coupled to the first capacitor circuit such that charge redistribution occurs. The overall voltage on the second capacitor circuit is increased when the filtered reference voltage is less than the input reference voltage, or decreased when the filtered reference voltage is greater than the input reference voltage. The voltage from the second capacitor circuit is buffered to provide the filtered reference voltage. The overall system is suitable for an integrated circuit.

Abstract: The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.

Abstract: This invention relates to circuitry for detecting peak levels of signals and particularly fast hold and sample peak detectors for analyzing signals of generally arbitrary wave shape and form having a high precision, high slew-rate, very short retention, and a low distortion. The circuitry comprising a comparator circuit comprising two signal inputs and a signal output, where the output signal depends from the difference between the input signals, a sample and hold circuit comprising switching means controlled by said signal output for sampling and holding means for holding the output signal, a compensation circuit for compensating residual currents comprising emulating means for emulating residual currents caused by said comparator circuit influencing the functionality of said sample and hold circuit, and an unload circuit comprising a clearing means for decreasing the output signal of said sample and hold circuit.

Abstract: In the case of a sample-and-hold device a holding condenser (1) is fed with an input voltage (V-IN) via a controllable sampling switch (2). To improve the transient characteristic of the sampling switch (2) this is fed with an adjusting signal of a controller, which regulates the conductance of a mirror switch 3 with essentially identical features as the sampling switch (2) to an ideal value, whereby the mirror switch (3) is exposed to the same operating conditions as the sampling switch (2). In order to reduce distortions of the sample-and-hold device, a voltage step-up condenser (5) can be looped into the activating path, which feeds the adjusting signal to the control inputs of the sampling switch (2) or the mirror switch (3), before which was previously loaded with an auxiliary voltage (VH).

Abstract: A method and apparatus for measuring and controlling the phase difference or time difference between two signals is presented. In some embodiments two sample and hold (S/H) circuits are arranged as a cooperating system that alternately samples a first signal using the second as a reference. Chopping may be used at the input or output of the S/H circuits. In some embodiments, accurate measurement of digital signal phase differences, such as between two square waves, is obtained without the problems associated with traditional pulse-generation techniques that fail at high frequencies and short pulse lengths.

Abstract: An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the cells at low speed. Two identical memory devices are provided in each memory cell. One sample of an analog signal is stored in one memory device, and one sample of that signal that is out of phase is stored in the other memory device.

Abstract: A track-and-hold circuit including a pair of circuits each receiving input signals and providing half of a differential output signal. Each of the circuits of the pair includes an amplifier, and a configurable switch circuit coupled to a selectable reference voltages based on an expected input signal type. Each circuit includes a first switched capacitor circuit to sample its respective first input signal in response to a first clock phase, and to couple the sampled first input signal between the output and the negative input of the amplifier in response to a second clock phase. A second switched capacitor circuit samples its respective second input signal relative to an external common mode voltage in response to the first clock phase, and couples the sampled second input signal to a positive amplifier input relative to the selected reference voltage in response to the second clock phase.

Abstract: A sample and hold device is provided in which sample switches are employed to switch between a sample phase and a hold phase. The sample and hold device provides alternate paths for the AC currents flowing to and from the sampling capacitor during the sample phase to mitigate the deleterious effects of the high AC currents through sample switches. The current drawn by the sampling capacitor from the input signal is replicated and directed to charge and discharge the sampling capacitor through alternate paths with respect to a path through the sample switches.

Abstract: An active feedback loop is provided in a switched-capacitor circuit to automatically cancel both junction and sub-Vth channel leakage. Low power consumption that is crucial for implantable medical devices is achieved. The circuit technique largely minimizes the effective leakage current when the switch is turned off. This circuit technique of the invention can be used in many different circuit applications.

Abstract: In order to reduce harmonic distortion, a track and hold circuit comprising a MOS transistor switch, a hold capacitor, and a voltage stabilizer for biasing bulk potential of the MOS transistor switch at a certain voltage is disclosed.

Abstract: The invention relates to a current sample-and-hold circuit comprising, several sub-circuits, in which a current signal is stored. At least one of said sub-circuits contains a switch. The inventive current hold-and-sample circuit is characterised in that each of the sub-circuits contains a linear resistor, which is connected in such a way that the current signal generates a voltage drop across the resistor, that each of the sub-circuits contains at least one inverting control amplifer, which sets an initial current of the circuit in a hold operational mode, thus inducing a voltage drop across the resistor, said voltage drop being substantially as great as the voltage drop across the resistor before the hold operational mode.

Abstract: As each of sampling switch elements turns on in response to a scanning signal, a signal voltage from a signal wire is held on and written into a sampling capacitor. At this time, the signal voltage is held on the sampling capacitor on the basis of a common electrode. As the scanning signal transitions from high level to low level, each of the sampling switch elements turns off and changes into a floating state in which the sampling capacitor is electrically insulated from the signal wire and a driving TFT. As the scanning signal changes from high level to low level, each of the driving switches becomes conductive so that the signal voltage held on the sampling capacitor is applied as it is between the source and gate of the driving TFT as a bias voltage to make the driving TFT conductive, causing an organic LED to emit light.

Abstract: A sample-and-hold amplifier circuit has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. Thus, sampling can be carried out so that first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the (&phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive.

Abstract: A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.