Abstract: A power amplifier architecture includes high and low power paths. The high power path may include a number of different amplifier structures. The low power path includes a switching element configured to short a signal line to ground or provide an open between the signal line and ground. The low power path and an output of the high power path are summed at a summing junction. Circuitry, responsive to one or more control signals, is configured in a high power mode to turn on amplifier(s) in the amplifier structure, route an input signal through a driver amplifier to the high power path and place the switching element in one of the open/closed positions; the circuitry is configured in a low power mode to turn off the amplifier(s), route the input signal through a driver amplifier to the low power path and place the switching element in the other position.

Abstract: A power amplifier device includes an input terminal for a RF input signal. The power amplifier device includes an output terminal a RF output signal. The power amplifier device includes a first power amplifier connected to the input terminal, amplifies the RF input signal with a first gain, and outputs a first amplified signal. The power amplifier device includes a second power amplifier that amplifies a signal on the basis of the first amplified signal and outputs a second amplified signal with a second gain. The power amplifier device includes a low-pass filter or a band-pass filter that filters the second amplified signal. The power amplifier device includes an amplitude comparator to compare the first amplitude of the first comparison signal generated from the RF input signal with the second amplitude of the second comparison signal generated from the filtered signal and to output an amplitude comparison signal.

Abstract: A wireless communication system (400) for power amplification of an input signal includes a power amplifier (404) operable to amplify a data signal (405). An envelope generator 408 or detector is operable to determine an envelope signal (410) from the data signal. A tracking power supply or other power supply control circuit (409) is operable to control a supply voltage of the power amplifier with the envelope signal. An allocation manager (441) is operable to determine a resource block allocation within a channel for the data signal. A delay circuit (443) is operable to insert a delay (550) between the envelope signal and the data signal as a function of the resource block allocation within the channel, thereby intentionally causing unbalanced leakage about the resource block allocation. Increased leakage on one side of the allocation results in improved leakage on the other side.

Abstract: A circuit for providing a bias signal for a power amplifier includes a first input, a second input and an output. The first input is configured to receive an input signal to be amplified by the power amplifier. The second input is configured to receive the amplified input signal. The output is configured to provide the bias signal.

Abstract: A system and method of calibrating an amplifier are presented. The amplifier has a first amplification path and a second amplification path. A first state of the amplifier is identified defining a first phase shift of the first path and a second phase shift of the second path resulting in a maximum efficiency of the amplifier when an attenuation of the first path and an attenuation of the second path are set to first attenuation values. The attenuation of the first path and the attenuation of the second path is set to achieve a maximum efficiency of the amplifier when the phase shift of the first path and the phase shift of the second path are set according to the first state.

Abstract: Apparatus and methods for envelope tracking are disclosed. In one embodiment, a power amplifier system including a power amplifier and an envelope tracker is provided. The power amplifier is configured to amplify a radio frequency (RF) signal, and the envelope tracker is configured to control a supply voltage of the power amplifier using an envelope of the RF signal. The envelope tracker includes a buck converter for generating a buck voltage from a battery voltage and a digital-to-analog conversion (DAC) module for adjusting the buck voltage based on the envelope of the RF signal to generate the supply voltage for the power amplifier.

Abstract: Circuits and methods for achieving high linearity, high efficiency power amplifiers, including digital predistortion (DPD) and pulse cancellation in switched-state RF power amplifier systems are described.

Abstract: In an embodiment, a power amplifier (PA) includes a signal processing path including gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, sensors coupled to the signal processing path each to sense a characteristic of operation of the PA, and a microcontroller configured to execute instructions and to receive the operation characteristic(s) and to control one or more parameters of the signal processing path responsive this operation characteristic.

Abstract: An improved method for maintaining optimal amplifier bias current utilizing a signal conditioning element 0710 which serves to symmetrically condition a sense voltage 0105 such that the sense voltage 0105 distortion is substantially determined by properties of the signal conditioning element 0710 rather than by properties of the amplifier amplification devices 0101 or the input perturbing signal.

Abstract: A gain adjustment device for a wireless communication circuit comprising a transmission circuit and a reception circuit includes a signal generator and a gain adjustment circuit. The signal generator is coupled to the transmission circuit, and arranged for generating a test signal to the transmission circuit. The test signal transmitted through a printed circuit board such that the reception circuit coupled to the transmission circuit generates a corresponding reception signal in response to the test signal. The gain adjustment circuit is coupled to the reception circuit and the transmission circuit, and arranged for adjusting a transmitter gain configuration and a receiver gain configuration of the wireless communication circuit according to the reception signal.

Abstract: A method for processing signals may include, in a conditionally-stable operational amplifier, shifting the gain curve of the conditionally-stable operational amplifier to a desired position, by buffering at least one output signal from at least one transconductance module within the conditionally-stable operational amplifier using a buffer. The desired position of the gain curve may be associated with a desired feedback factor. The shifting of the gain may take place without shifting a corresponding phase. The tuning of the buffer may be based on the desired position of the gain curve which is derived from feedback factor value(s) specified by an application. A phase corresponding to the desired position of the gain curve at 0 dB frequency may be greater than a threshold phase. The buffering may be tuned using at least one tunable wideband buffer so that the corresponding phase at 0 dB frequency remains higher than the threshold phase.

Abstract: The present invention discloses apparatus and method for fast and robust automatic gain control (AGC). By using the power statistics and/or the amplitude statistics of multiple pairs of signed ADC outputs, the additional gain control can be determined and included in a statistics-aided AGC to successfully complete the AGC function for a received signal having a dynamic range up to 100 dB within a few micro-seconds.

Abstract: An integrated circuit for transmit and receive matching is described. The integrated circuit includes a transmit amplifier. The transmit amplifier includes a first transistor, a second transistor and a first inductor. The first inductor couples the first transistor to the second transistor. The integrated circuit also includes a low noise amplifier. The low noise amplifier includes a third transistor, a fourth transistor, the first inductor, a second inductor, a third inductor and a transformer. The second inductor couples the first inductor to the third transistor. The third inductor couples the third transistor to ground.

Abstract: A digital pre-distortion system and method are provided. The method includes performing a digital pre-distortion operation; and limiting an input of the power amplifier to be no greater than a limit threshold.

Abstract: In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.

Abstract: A signal amplifying circuit is provided. The signal amplifying circuit includes a signal amplifier and a control circuit. The control circuit includes a compare unit and a register unit. The compare unit compares an input signal of the signal amplifier with a reference signal to generate a compare signal. The register unit receives and registers a control signal to be transmitted to the signal amplifier, and provides a registered signal to the signal amplifier according to the registered control signal when the compare signal is changed.

Abstract: Methods and systems for conditioning wireline communications to remove intersymbol interference are provided that used adaptive equalization. The method and systems include using a digital finite state machine to control two feedback loops that adjust the gain and power of the input signal relative to a supplied reference. The eye height of the input signal is conditioned by a gain feedback loop so that signal equalization can be performed in a known state. The digital finite state machine allows the loops to be flexibly run in sequence or concurrently. The adaptation functions can be shut off when adequate signal equalization has been achieve, thus saving power.

Abstract: Provided is a transmission circuit capable of compensating a variation in output power caused due to a temperature change or an individual variability when the operation mode is switched without an increase in the size of the transmission circuit which switches the operation mode between a linear operation mode and a nonlinear operation mode, and capable of suppressing the deterioration of the quality of a transmission signal. In the transmission circuit, a gain setting section (160) sets the gain (target gain) of a variable gain amplifier (140), to a value which enables the variable gain amplifier (140) to operate linearly and corresponds to a comparison result (output error level) obtained through comparison between the target level of the variable gain amplifier (140) corresponding to the set power level of the transmission signal and the power level of an output signal of the variable gain amplifier (140) detected by a power detection section (150).

Abstract: An integrated circuit includes a millimeter wave transceiver section that is coupled to generate a first modulated RF signal from a first outbound symbol stream and to convert a first inbound RF signal into a first inbound symbol stream. A wireless transceiver section is coupled to generate a second modulated RF signal from a second outbound symbol stream and to convert a second inbound RF signal into a second inbound symbol stream. A processing module is coupled to convert first outbound data into the first outbound symbol stream, convert second outbound data into the second outbound symbol stream, convert the first inbound symbol stream into first inbound data, and to convert the second inbound symbol stream into second inbound data.

Abstract: A radio apparatus capable of correcting a direct current offset with high accuracy in a short time is provided. A radio apparatus according to an embodiment includes a first amplifier amplifying a signal inputted to an input terminal with amplification gain determined by a variable resistor to generate a first amplified signal, and a second amplifier amplifying the first amplified signal to generate a second amplified signal. Further, the radio apparatus includes a first correcting unit correcting a direct current offset of the first amplifier, and a second correcting unit correcting a direct current offset of the second amplifier.

Abstract: A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.

Abstract: A power converter system for managing power between a power supply and a load, the system including: a first buck-boost circuit connected to the power supply; and a capacitor provided between the buck-boost circuit and the load to buffer power supply for the load. The system may include a second buck-boost circuit between the capacitor and the load. In another embodiment, a power converter system includes: a boost circuit connected to the power supply; a buck circuit connected to the load; and a capacitor provided between the boost circuit and the buck circuit to manage the supply of power to the load.

Abstract: A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA.

Abstract: A radio frequency (RF) power amplifier system adjusts the supply voltage provided to a power amplifier (PA) adaptively, responsive to the measured or estimated power of the RF output signal of the PA. The RF PA system includes a power amplifier (PA) which receives and amplifies an RF input signal to generate an RF output signal at a level suitable for transmission to an antenna. A PA supply voltage controller generates a supply voltage control signal, which is used to control the supply voltage to the final stage of the PA. The supply voltage control signal is generated responsive to the measured or estimated power of the PA RF output signal, and also may be responsive to a parameter indicative of impedance mismatch experienced at the PA output. By controlling this supply voltage to the RF PA, the efficiency of the PA is improved.

Abstract: An automatic gain control (“AGC”) system. The system includes a first multiplier, an envelope detector, a summation module, a filter module, a convergence module, and a feedback module. The convergence module includes a convergence control module and a second multiplier. The feedback module includes an accumulator, a scalar multiplier module, and a third multiplier. The system is configured to adjust or modify its convergence speed according to the state of convergence of the AGC system, and the convergence speed of the AGC system is substantially independent of a signal level of the received signal.

Abstract: A combination equalizer and automatic gain control (AGC) is provided for high-speed receivers. The combination circuit comprises a first AGC having an input to accept a communication signal and an input to accept a first control signal. The first AGC modifies the communication signal gain in response to the first control signal, to supply a first stage signal at an output. An equalizer has an input to accept the first stage signal and an input to accept a second control signal. The equalizer modifies the frequency characteristics of the first stage signal in response to the second control signal, to supply an equalized signal at an output. A second AGC has an input to accept the equalized signal and an input to accept a third control signal. The second AGC modifies the equalized signal gain in response to the third control signal, to supply a second stage signal at an output.

Abstract: A bicycle-use measuring apparatus includes a sensor, a signal amplifying section and a gain control section. The sensor is configured to be installed on a bicycle having a rotating part. The signal amplifying section amplifies an output of the sensor. The gain control section adjusts a gain of the signal amplifying section in accordance with changes in a rotational state of the rotating part.

Abstract: Systems, methods and apparatus are disclosed for amplifiers for wireless power transfer. In one aspect a method is provided for controlling operation of an amplifier, such as a class E amplifier. The method may include monitoring an output of the amplifier. The method may further include adjusting a timing of an enabling switch of the amplifier based on the output of the amplifier.

Abstract: A modulation device includes a signal input for receiving a data stream to be modulated and a first and a second signal output. At least one first complex component is derived from the data stream in a coding device. A first and a second high-frequency signal are output via the signal outputs. The first and second high-frequency signals are derived from the at least one first complex component and are distinguished by the fact that the second high-frequency signal has a phase shift of substantially 90° with respect to the first high-frequency signal.

Abstract: An apparatus and an associated method for automatic gain control (AGC) are provided to improve the ability to lock effective signal power when interference exists, thereby upgrading the receiver performance of a communication system. The apparatus includes a variable-gain circuit for adjusting the power level of an input signal. The apparatus also includes a gain adjustment circuit and a target value adjustment circuit. The gain adjustment circuit is for adjusting the gain of the variable-gain circuit according to the adjusted input signal and a target value, while the target value adjustment is for dynamically adjusting the target value according to the strength of the adjusted input signal.

Abstract: An apparatus comprising a first circuit configured to receive a signal and output a first output signal, a second circuit configured to receive the same signal and output a second output signal with a phase delay compared to the first signal, and a combiner configured to combine said first and second output signals to provide a combined signal, wherein said phase delay is controlled such that an amplitude of said combined signal is controlled.

Abstract: An automatic gain control circuit includes: an amplification degree control section for calculating power of a digital value of a received signal, and for controlling an amplification degree of an amplifier of a receiving apparatus so that a difference between the power and predetermined reference power is zero; a received signal quality measuring section for measuring quality of the received signal; a reference power adjusting section for, upon finding that the measured quality of the received signal is below a fixed level, adjusting the reference power for a predetermined period of time; and a reference power updating section for causing the reference power adjusting section to continue to adjust the reference power until the quality of the received signal recovers to be at a predetermined recovery level or above, and for updating the reference power so that the reference power takes on an optimally adjusted value.

Abstract: A received signal is amplified in an amplifier to create an amplified signal. The amplified signal is then filtered. The power of permanent common pilot sub-carriers present in the filtered amplified signal is calculated. A wideband power measurement is determined based on the amplified signal, and a narrowband power measurement is determined based on the filtered amplified signal. The first gain for the amplifier is controlled in dependence on the calculated power of the permanent common pilot sub-carriers, the wideband power measurement and the narrowband power measurement. The power of the permanent common pilot sub-carriers may be calculated in the frequency domain to mitigate fast switching of the controlled first gain. The filtered amplified signal may be amplified in a further amplifier, and a second gain can be controlled for the further amplifier in dependence on the calculated power of the permanent common pilot sub-carriers, the wideband power measurement and the narrowband power measurement.

Abstract: A mobile wireless communications device and associated method of making same includes a housing and circuit board having a ground plane. Radio frequency (RF) circuitry and a processor are carried by the circuit board and operative with each other. An antenna is carried by the housing and operative with the RF circuitry. Audio circuitry is carried by the circuit board and operative with the RF circuitry and processor. An audio transducer assembly such as a receiver is carried by the circuit board and engages audio circuitry for carrying audio signals between the audio circuitry and speaker. A filter is mounted at the speaker for blocking RF energy from the antenna through the speaker to the ground plane and decoupling the antenna from the speaker and any other components on the circuit board to minimize any detuning of antenna impedance match and degradation in antenna gain.

Abstract: There is provided a power amplifier capable of supplying variable bias to an amplifier circuit by accurately transferring the envelope components of an input signal during the supply of active bias power to the amplifier circuit. The power amplifier includes: an envelope detector detecting an envelope of an input signal; a bias power generator including at least one P-type MOSFET and one N-type MOSFET connected to each other in an inverter manner between a driving power terminal supplying driving power having a preset voltage level and a reference bias power terminal supplying preset reference bias power to generate bias power varied according to detection results from the envelope detector; and an amplifier amplifying the input signal according to the bias power level from the bias power generator.

Abstract: Methods and apparatus are disclosed for automatically adjusting antenna impedance match in a wireless transceiver employing phase-amplitude modulation. According to some embodiments of the invention, a wireless transceiver comprises a transmitter circuit and a receiver circuit connected to the antenna by a transmit/receive duplexer. An electronically adjustable matching network is located between the transmitter output and the antenna. To control the adjustable matching network, a directional coupler is located between the transmitter output and the matching network to separate transmit signals reflected from the antenna system, including the antenna, the matching network and the T/R duplexer. The reflected transmit signals are routed to the receiver circuit, which digitizes the reflected signal and determines an antenna reflection coefficient based on the digitized reflected signal and the modulation signal used to create the transmit signal.

Abstract: Techniques and devices are disclosed to provide multi-stage gain control in circuits or devices having two or more stages of signal amplification. A circuit with multi-stage gain control can include amplification stages coupled to receive an input signal and to produce an amplified output signal. Each amplification stage includes an amplifier that is adjustable in gain and a signal detector that is coupled to measure an output signal of the amplifier and to produce a detector signal indicative of a signal strength of the output signal of the amplifier. A gain control circuit is coupled to receive detector signals from the signal detectors in the amplification stages, respectively, and to control gains of the amplifiers of the amplification stages based on respective received detector signals, respectively.

Abstract: An automatic gain control apparatus for a wireless receiver, including multiple variable gain amplifiers, one variable gain amplifier provided for each one of multiple receive chains and a gain controller to control a gain of the variable gain amplifiers provided for the plurality of receive chains. The gain controller includes multiple output level measurement units to measure an output level of a corresponding receive chain; a common gain determination unit to determine a common gain for each of the variable gain amplifiers based on a statistical value obtained from the output levels; multiple adjusted gain determination units, each adjusted gain determination unit determining an adjusted gain independently for each variable gain amplifier within a range narrower than the range of the common; and a gain setting unit to set a gain to each of the variable gain amplifiers based on the common gain and the adjusted gain.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: A relationship is established between measurable characteristics of the DC power input to a power amplifier and the RF output power level. A power circuit is configured to measure the input supply current to the power amplifier and to utilize the relationship between the input supply current and the applied input supply voltage to the output power level, thereby normalizing the output power of an amplified communication signal.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Abstract: A digital power amplifier is disclosed. The digital power amplifier may comprise an amplifying stage configured for applying a first level of attenuation to an RF input signal in response to a desired output power level of the digital power amplifier; a reference loop configured for determining an average power of a sample of the RF input signal and providing a reference value at least partially based upon the average power of the sample of the RF input signal; a feedback loop configured for applying a second level of attenuation to a sample of an output of the amplifying stage and providing a feedback value indicating an average power of the attenuated sample of the output; and an error amplifier configured for providing a gain control adjustment signal to the amplifying stage, the gain control adjustment signal being determined based upon the reference value and the feedback value.

Abstract: A voltage detection circuit includes operational amplifiers, a battery, and a voltage circuit. The voltage circuit offsets the inverting input terminals and non-inverting input terminals of the operational amplifiers to the positive side with reference to a ground GND.

Abstract: A high frequency power amplifier maintains an excellent linearity regardless of a fluctuation of a load impedance and is downsized. The high frequency power amplifier detects an AC voltage amplitude at an output terminal of a final amplification stage transistor, and suppresses an input signal amplitude of a power amplifier when the voltage amplitude exceeds a predetermined threshold value.

Abstract: This document discusses, among other things, apparatus and methods for providing dynamic range compression. In an example, an amplifier can an first amplifier configured to receive a representation of an input signal and provide an amplified representation of the input signal to an output stage, an automatic gain control comparator configured to provide automatic gain control information to the first amplifier, a plurality of dynamic range compression comparators configured to provide a plurality of signals indicative of an amplitude of an output signal of the output stage, a first voltage divider configured to provide an automatic gain control threshold to the automatic gain control comparator, and a second voltage divider configured to receive the automatic gain control threshold and to provide a plurality of range compression thresholds to the plurality of dynamic range compression comparators.

Abstract: Embodiments of switched-capacitor gain stage circuits and methods of their operation are provided. The circuit includes an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state. In the sampling state, the switches are configured so that a first charge component representing an input signal is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor. In the gain state, the switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor. In the output state, the switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node.

Abstract: Aspects of a method and system for closed loop power control in wireless systems are provided. In this regard, an output power of an amplifier may be measured and an indication of the measured power may be compared to a reference signal. The results of the comparison are utilized to generate an error correction factor. The gain of a preamplifier may be adjusted utilizing the error correction factor, where the output of the preamplifier may be input to the amplifier. The error correction factor may be generated via a proportional integral derivative controller. The gain of the preamplifier may be adjusted via at least one control signal, where the at least one control signal may be generated based on a reference control word and the error correction factor. The indication of the measured power and the reference signal may be time aligned.

Abstract: A system for analyte measurement includes a programmable gain amplifier including a first input terminal operatively coupling to the output of a sensor for sensing an analyte, a second input terminal operatively coupling to a voltage source, and an output terminal for providing an output based on a difference between inputs on the first input terminal and the second input terminal A controller is operatively coupled to the programmable gain amplifier for configuring the operation range of the programmable gain amplifier and/or selecting the output of the programmable gain amplifier for analyte measurement. The method includes monitoring an output from a programmable gain amplifier operatively coupling to a sensor for sensing an analyte, and controlling the operation range of the programmable gain amplifier, and/or selecting the output of the programmable gain amplifier for analyte measurement.

Abstract: A F/2F waveform generator has a comparator and an analog multiplexer. In a low-cost magnetic card reader application, a magnetic track signal is amplified, filtered, and compared with a threshold signal to create a digital signal output. The analog multiplexer detects changes in state of the digital signal. When a change of state is detected, the analog multiplexer switches among dynamically tunable threshold signals. The selected threshold signal is used for comparison with the magnetic track signal. Switching level detection enables accurate F/2F waveform generation from relatively noisy magnetic track signals, thus improving the robustness of magnetic card readers. The analog implementation eliminates the need for expensive A/D conversion and processing and the design can be readily implemented in a very compact and low-cost package.