Abstract: Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.

Abstract: The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance amplifier (OTA) with a differential of transistors for receiving a differential input voltage, a bias current source coupled to the differential pair and a single-ended output, the first bias current generating stage with a differential pair of transistors coupled to receive the differential input voltage to produce an output current in an output current path in response to a positive differential input voltage, a second bias current generating stage with a differential pair of transistors coupled to receive the inverted differential input voltage to produce an output current in an output current path in response to a negative input voltage, wherein the output current paths of both bias current generating stages are combined in a common current path and the current in the common current path is mirrored to the bias current source of the single stage OTA, s

Abstract: A class AB operational amplifier is provided that includes first and second input transistors respectively coupled between first and second internal nodes and a first common node, first and second input stage load transistors diode connected and respectively coupled between a first voltage reference and the first and second internal nodes, first and second output transistors coupled in series between the first voltage reference and a second voltage reference, a tail current generator coupled between the first common node and the second voltage reference, an adaptive bias block coupled between the first and second voltage references and coupled to the first common node, and a positive feedback network coupled between the first voltage reference and the first and second internal nodes. Also provided is an integrated circuit having at least one such operational amplifier.

Abstract: An amplifier comprises: first and second supply terminals intended to receive a DC supply voltage; a first branch coupled between the first and second supply terminals and including a first terminal of application of a differential signal to be amplified; a second branch coupled between the first and second supply terminals and including a second terminal of application of the differential signal to be amplified; a third branch coupled between the first and second supply terminals and including a first amplifier having an input terminal connected to the second branch and having an output terminal configured to be coupled to a load, and a measurement element configured to measure a current in the third branch; and a fourth branch coupled between the first and second supply terminals and including a second amplifier having an input terminal connected to the first branch, and a copying element configured to copy the current measured in the third branch.

Abstract: A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit.

Abstract: A differential amplifier has improved power efficiency, reduced offset penalty and a symmetrical output differential signal. Such a differential amplifier may include: (a) a bias circuit that has a first input device and a second input device; (b) a first load device and a second load device, each biased by a bias voltage from the bias circuit; and (c) a third input device and a fourth input device that are connected in series with the first load device and the second load device, respectively. In that differential amplifier, the differential input signal is applied across the first and second input devices, as well as across the third and the fourth input devices. The first, second, third and fourth input devices are sized such that a total current in the first and second input devices bears a predetermined ratio to a total current in the third and fourth input devices.

Abstract: Described herein is technology for, among other things, input bias current cancellation. The technology includes a bipolar differential pair coupled with a supply voltage (VCC). The bipolar differential pair includes a first transistor and a second transistor. The technology further includes an input bias current cancellation circuit coupled with the bipolar differential pair and including a third transistor. The third transistor has a collector-emitter voltage VCE, and the bipolar differential pair is operable to receive an input voltage greater than VCC?2VCE without causing the third transistor to operate in the saturation region.

Abstract: Provided herein are input stages, and operation amplifiers including input stages. In an embodiment, an input stage includes a complimentary differential input transconductor, first and second npn-pnp current mirrors, and first and second pnp-npn current mirrors. The complimentary differential input transconductor includes a pair of differential inputs that accept a pair of voltage signals, a first pair of complimentary differential outputs that output current signals I1 and I2, and a second pair of complimentary differential outputs that output current signals I3 and I4. Each current mirror accepts one of the current signals I1, I2, I3 and I4, and outputs a pair of current signals (e.g., I1? and I1?) that are proportional to the accepted current signal (e.g., I1). Current signals I1? and I3? are added to produce a first output current (Iout) of the input stage. Current signals I2? and I4? are added to produce a second output current (Iout_bar) of the input stage.

Abstract: A common mode feedback circuit includes a first capacitor connected between a common mode feedback terminal and a first output terminal, a second capacitor connected between the common mode feedback terminal and a second output terminal, a first cell having a third capacitor sharing charges with the first capacitor and a fourth capacitor sharing charges with the second capacitor in response to a first clock control signal, and a second cell having a fifth capacitor sharing charges with the first capacitor and a sixth capacitor sharing charges with the second capacitor in response to a second clock control signal. The first clock control signal and the second clock control signal have respective logic states that do not overlap in time.

Abstract: An adaptive biasing input stage includes pairs of differentially coupled amplifying and sensing field effect transistors having gates with differential inputs applied thereon. In addition, a static current source is coupled to sources of the amplifying and sensing field effect transistors at a predetermined node. Also, current mirrors are coupled to the sensing field effect transistors for forming loop mechanisms for increasing the current through the predetermined node when the differential inputs have a non-zero difference.

Abstract: A voltage regulator having an input voltage and adapted to supply a regulated output voltage, the regulator including an AB class amplifier and a power transistor having a non-drivable terminal coupled to the input voltage, a non-drivable terminal coupled to a reference voltage and a drivable terminal coupled to the output terminal of the amplifier; the amplifier is adapted to amplify the voltage difference between a further reference voltage and a fraction of the regulated voltage.

Abstract: An operational amplifier according to an embodiment of the invention includes: a control signal input terminal receiving a digital control signal from an external device; first and second transistors as a differential pair of a differential amplifier circuit; a constant current circuit supplying a predetermined current to the differential pair; a first resistor provided between the constant current circuit and the first transistor and involving a first potential difference; and a second resistor provided between the constant current circuit and the second transistor and involving a second potential difference, the operational amplifier changing a resistance value ratio between the first resistor and the second resistor in accordance with the control signal input to the control signal input terminal.

Abstract: An amplifier includes a differential amplifier stage, a voltage amplification stage and a power output stage. The bias level of the output stage is proportional to current through the voltage amplification stage. The voltage amplification stage includes a current mirror whereby controlled current through a first leg of the current mirror controls current through the remaining, second leg, which, in turn, determines the bias level of the power output stage. Control circuitry senses a parameter of the amplifier, such as DC bias or input signal level to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.

Abstract: An operational amplifier including an input stage. The input stage may include first and second differential input circuits and a first current mirror. When an input terminal of the operational amplifier is at a positive voltage rail, the first differential input circuit may be activated. When the input terminal is at a negative voltage rail, the second differential input circuit may be activated. In either case, this may cause the first current mirror to provide a current of a predetermined value to each of first and second input terminals of a control circuit, and to each of first and second nodes coupled to a rail-to-rail output stage. The input stage may maintain the current provided to each of the input terminals of the control circuit and to each of the nodes coupled to the rail-to-rail output stage constant over the full input voltage range from the negative voltage rail to the positive voltage rail.

Abstract: A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level.

Abstract: Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.

Abstract: A fully differential amplifier with a high common mode rejection ratio with an independent output voltage setting is disclosed. The amplifier may be arranged with a single ended output or a differential output. The gain may be set by adjusting a resistor without affecting bandwidth of the circuit. The circuit exhibits high speed and may be implemented with various electronic component types. The DC voltage of the output, single ended or differential, may be adjusted by adjusting a reference voltage, wherein the output voltage adjustment does not substantially affect the performance of the differential amplifier.

Abstract: Provided is an operational transconductance amplifier (OTA). An existing Nauta transconductor used to implement a high frequency Gm-C filter integrated circuit (IC) is analyzed by a new method and from a new perspective to remove extra components and divide roles of remaining inverters for more simple and efficient circuit structure. In an existing Nauta transconductor, a common mode signal from an input terminal is amplified and appears at an output terminal, while in the inventive Nauta transconductor the common mode signal from an input terminal does not appear at the output terminal and is effectively eliminated. These enhanced characteristics can be achieved with a smaller number of inverters than an existing Nauta transconductor. Frequency characteristics of the filter can be effectively enhanced by independently controlling the quality factor without affecting the transconductance value required for frequency characteristics of the filter.

Abstract: To eliminate common-mode components in differential input signals without the necessity of introducing a transformer and a special feedback loop for eliminating common-mode components, a differential amplifier (1) comprises a first input stage (11) for receiving differential input signals comprising common-mode signals and for outputting first differential intermediate signals, a second input stage (12) for inverting the common-mode signals and for combining inverted common-mode signals and the first differential intermediate signals into second differential intermediate signals, and an output stage (13) for receiving the second differential intermediate signals and for outputting differential output signals.

Abstract: An analog transconductance amplifier includes an input stage including a first transistor and a second transistor connected in series to the first transistor. The first and second transistors are connected between positive and negative voltages and are respectively controlled by an input voltage and a first control voltage for generating a normalized drive voltage. An amplification stage includes a first conduction path including an amplification transistor controlled by the normalized drive voltage. A first load transistor is connected in series to the amplification transistor and is controlled by a second control voltage. A second conduction path includes at least one second load transistor controlled by a third control voltage. A current mirror forces through the second conduction path a replica of current flowing through the first conduction path. An output stage transistor delivers an output current, and is controlled by a voltage on the second load transistor.

Abstract: In one system embodiment, the system is characterized by: a differential amplifier including but not limited to at least one amplifying transistor having an emitter coupled directly to a ground. In one embodiment of a method of making a system, the method is characterized by: operably coupling at least one amplifying transistor of a differential amplifier directly to a ground. In one embodiment of a method of driving a system, the method is characterized by: driving at least one amplifying transistor of a differential amplifier with an emitter-follower feedback loop. In one system embodiment, the system is characterized by: a differential amplifier including but not limited to a first amplifying transistor having a base operably coupled with a first emitter-follower feedback loop.

Abstract: There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is configured to operate as an inverter when a supply voltage is below a predetermined threshold.

Abstract: Provided herein are input stages, and operation amplifiers including input stages. In an embodiment, an input stage includes a complimentary differential input transconductor, first and second npn-pnp current mirrors, and first and second pnp-npn current mirrors. The complimentary differential input transconductor includes a pair of differential inputs that accept a pair of voltage signals, a first pair of complimentary differential outputs that output current signals I1 and I2, and a second pair of complimentary differential outputs that output current signals I3 and I4. Each current mirror accepts one of the current signals I1, I2, I3 and I4, and outputs a pair of current signals (e.g., I1? and I1?) that are proportional to the accepted current signal (e.g., I1). Current signals I1? and I3? are added to produce a first output current (Iout) of the input stage. Current signals I2? and I4? are added to produce a second output current (Iout bar) of the input stage.

Abstract: An operational amplifier and a scanning electron microscope which are capable of dealing with high voltage and large current, and which allow implementation of stable and precise amplification, the operational amplifier having a first-stage amplification unit including a differential pair, a base-grounded amplification circuit, and an active load, the base-grounded amplification circuit being cascode-connected to the differential pair a second-stage amplification unit including an inverter having an emitter follower circuit and a constant-current load circuit, and a third-stage amplification unit including a source follower circuit or an emitter follower circuit.

Abstract: A differential amplification circuit is constituted of a differential transistor pair including a pair of n-channel MOS transistors whose sources are connected together, a constant current source circuit which is connected to the sources of the differential transistor pair, a current-mirror load circuit including a pair of p-channel MOS transistors whose gates are connected together, and a bias generation circuit which generates a gate bias voltage and a drain bias voltage applied to the current-mirror load circuit in such a way that the same potential is set to both the drains of the p-channel MOS transistors. Thus, it is possible to reduce the input offset voltage without reducing the margin of operation voltage and without increasing the overall chip size.

Abstract: The LVDS receiver circuit comprises a differential-input transistor pair, a control transistor pair, a current-mirror-load circuit, a first feedback inverter and a second feedback inverter. The first feedback inverter, the second feedback inverter and the control transistor pair constitute a feedback loop. The voltage change of the input voltage of the first feedback inverter is suppressed, and the input voltage is controlled around the threshold voltage of the first feedback inverter.

Abstract: In a method and apparatus for rapidly recovering an improved amplifier from an overload condition, a cascode amplifier (CASA) having a pair of inputs and an output is coupled to an overload recovery circuit (ORC). The pair of inputs is coupled to receive a differential input signal. A deviation in the differential input signal that is greater than a threshold causes a deviation in a current provided to at least one transistor included in the CASA. The deviation in the current causes the CASA to operate in an overload condition (OC). The ORC includes a makeup current circuit operable to generate an overload current in response to the OC and a controller operable to control a voltage at the output during the OC. The controller coupled to the makeup current circuit provides the overload current to the CASA to enable the rapid recovery from the OC.

Abstract: A rail-to-rail class-AB operational amplifier includes a first differential pair unit for receiving a pair of differential signals and generating a first control signal; a second differential pair unit for receiving the pair of differential signals and generating a second control signal; and an output stage for receiving the first control signal and the second control signal and then generating an output voltage. The first differential pair unit includes a first active load, a first transistor differential pair and a first current source. The second differential pair unit includes a second current source, a second transistor differential pair and a second active load.

Abstract: An operational amplifier includes a differential amplifier, an output stage, and a control unit. The differential amplifier generates a first current through a first output node and a second current through a second output node in response to a voltage difference between a first input signal input through a first input terminal and a second input signal input through a second input terminal. The output stage generates an output signal through an output node. The control unit receives a voltage of the first output node and a voltage of the second output node, as bias voltages, and controls an output current of the output stage to determine the output signal of the output stage in response to the received voltages of the first and second output nodes.

Abstract: An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT 1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively.

Abstract: A gain-controlled amplifier is disclosed including: a set of switches; first and second transistors whose second terminals are coupled to each other via a resistive element; a first current mirror, coupled to a first terminal of the first transistor, for providing a set of first currents; a second current mirror, coupled to a first terminal of the second transistor, for providing a set of second currents; a first resistive network, coupled to the second terminal of the first transistor via a current source, for providing a first output signal; and a second resistive network, coupled to the second terminal of the second transistor via another current source, for providing a second output signal. Both the first and second resistive networks have a plurality of taps, coupling to either a first current or a second current through a switch of the set of switches.

Abstract: A differential amplifier of the present invention comprises transistors where to each of which one of two inputs to said differential amplifier is provided; current mirror circuits where each of which delivers one of the outputs of the differential amplifier to the load side; and cut-off prevention units where each of which is connected to the connecting point of a transistor to which a monitor current of one of the current mirror circuits flows, and one of the transistors to which the inputs are provided, and applies a current for preventing cutting off the transistor to which the monitor current flows, when the input to the transistor to which the input is provided is L.

Abstract: An integrated circuit system is provided including forming a differential pair; reducing a mismatch in the differential pair by: coupling an amplifier to the differential pair; and coupling a local feedback network to the amplifier in which referencing the local feedback network includes coupling a first voltage; and driving an output transistor by the amplifier.

Abstract: Disclosed herein is technology for, among other things, a current feedback fully differential amplifier. The amplifier includes an input stage operable to sense an input current at a first terminal and a second terminal. The input stage includes a first buffer having an input coupled with the first terminal and an output coupled with said the terminal. The input stage further includes a second buffer having an output coupled with the first terminal and an input coupled with the second terminal.

Abstract: A differential amplifying system has a differential amplifier for amplifying a voltage signal inputted from an input terminal and outputting the amplified voltage signal through an output terminal; an amplitude detection circuit for detecting an amplitude of said voltage signal inputted to said differential amplifier and outputting a detected current corresponding to the amplitude; a compensation circuit having: a current mirror circuit for outputting a compensating current at a desired mirror ratio for an input of said detected current; and a feedback circuit for changing a mirror ratio of said current mirror circuit in order to control a magnitude of the compensating current according to an amplitude of the voltage signal detected by said amplitude detection circuit; and a bias circuit for supplying bias voltage to said differential amplifier in order to add a bias value to inputted said voltage signal based on the magnitude of said compensating current.

Abstract: An amplifier has a voltage to current converter coupled between a first potential and a reference potential and includes a control input coupled to a voltage at an input of the amplifier for converting the voltage at the amplifier input into a corresponding output current. A current multiplier is fed by the output current for producing an increased current. The increased current is fed to a control electrode of a transistor. A feedback element provides the first potential to the voltage to current converter by coupling a voltage produced by the feedback element in response current through the transistor to the voltage to current converter.

Abstract: A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and second input conductors. An input of a first current mirror is coupled to the first input conductor, and an input of a second current mirror is coupled to the second input conductor. Outputs of the second and first current mirrors are coupled to collectors of the first and second cascode transistors, respectively, and also to first and second outputs, respectively, of the differential current follower. A third current mirror converts a differential output current in the first and second output conductors to a corresponding single-ended output voltage on the second output conductor.

Abstract: A differential gain boosted amplifier is provided. The differential amplifier includes at least one current mirror, at least one differential pair, at least one cascode, at least one differential gain boosting amplifier for differential current mirror voltage control, and at least one common mode amplifier comprising a common mode voltage to control the output common mode of the differential gain boosting amplifier. The common mode voltage includes a mirrored bias voltage. The mirrored bias voltage feeds directly into the common mode amplifier. A differential input voltage feeds directly into the differential gain boosting amplifier and the differential pair. A gain of the current mirror is boosted by the differential gain boosting amplifier. A differential output voltage is indicative of the differential input voltage with an increase in gain. The differential output voltage is connected to the cascode.

Abstract: An apparatus for supplying a load current. The apparatus comprises a first differential amplifier producing a differential output signal and an output buffer comprising a first and a second parallel emitter follower transistors each producing a current responsive to the differential output signal. A second differential amplifier responsive to the differential output signal controls current mirror masters that in turn control current source mirrors. Current supplied by each of the current sources mirrors in cooperation with the current produced by each of the first and second transistors produce the load current.

Abstract: A linearized bipolar differential input stage that contains two high gain current mirrors coupled in series with the input voltage signal through the input transistors to allow the output differential current to greatly exceed the DC output current in a Class AB fashion. The extended output current range over and above the DC current significantly lowers the percentage of effects for both DC offset and noise in the output signal path. Non-linearity cancellation is also optimized for the lowest level of input distortion through adjusting transistor area ratios.

Abstract: A differential signal generator circuit includes: a first amplifier for comparing an input signal with a threshold voltage and outputting differential signals; and a second amplifier for adjusting the threshold voltage in response to the differential signals. The second amplifier includes: a first transistor and a second transistor forming a differential pair, the gate of each transistor receiving a respective one of the differential signals; a third transistor and a fourth transistor forming a current mirror, the third transistor being connected between the drain of the first transistor and a reference potential point, the fourth transistor being connected between the drain of the second transistor and the reference potential point; a current source connected to the sources of the first and second transistors; and an adjusting section for adjusting drain current of the first transistor in response to an externally applied current or voltage.

Abstract: An operational amplifier includes a differential amplifier circuit, receiving a low voltage signal, and a current mirror circuit provided on the downstream. The differential amplifier circuit also includes low withstand voltage N-channel transistors, connected to respective input terminals, and high withstand voltage N-channel transistors, connected to the drain electrodes of the low withstand voltage transistors via junction points, respectively. To the gate electrodes of both the high withstand voltage transistors supplied is a bias voltage. The source electrodes of the low withstand voltage transistors are connected to the drain electrode of another low withstand voltage transistor, which has its gate electrode supplied with a bias voltage so as to operate as a current source. Those low withstand voltage transistors are smaller in size than the high withstand voltage transistors.

Abstract: A receiver circuit includes an attenuator that receives a received signal and attenuates the received signal, a DC level shifter that shifts a DC level of an attenuated signal from the attenuator, an amplifier section that has frequency characteristics of a band-pass filter and amplifies a signal from the DC level shifter that has been shifted with respect to the DC level, and a control circuit that controls an attenuation of the attenuator based on a signal output from the amplifier section. The control circuit controls the attenuation of the attenuator by changing filter characteristics of the attenuator corresponding to an amplitude of the signal output from the amplifier section so that the signal output from the amplifier section has a constant amplitude even when an amplitude of the received signal has changed.

Abstract: Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.

Abstract: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, a device comprising a differential pair is provided. A self-biased transistor and a component are coupled to the differential pair. At least one of the self-biased transistor and the component supply a current to the differential pair, wherein the component supplies substantially all of the current when the self-biased transistor is operating in a triode state.

Abstract: Methods and apparatus to provide increased current to a cascode amplifier to maximize slew rate are disclosed. The amplifier has a first input coupled to an input switch and a load circuit for amplifying an input voltage on the first input. A slewing input voltage to the amplifier is detected. Current is increased to the load circuit to increase the slew rate of an output voltage.

Abstract: An amplifier stage includes a first and a second signal path having a series connection of a first transistor of a first conduction type which forms a control input for receiving an input signal to the amplifier stage and a second transistor of a second conduction type. The amplifier stage further includes a first and second signal output which are formed by a respective connection node of the respective first and second transistors. For each of the first and the second signal path, the amplifier stage includes a third transistor of the second conduction type which is connected to the respective second transistor as current mirror, and a fourth transistor of the first conduction type which is connected to the respective first transistor as a current mirror and which is for controlling the third transistor of the other signal path, respectively.

Abstract: A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

Abstract: Disclosed are a multi-level differential amplifier that includes first to third input terminals; an output terminal; first to third differential pairs; a current source circuit for supplying currents to the respective first to mth differential pairs; a load circuit connected to first and second nodes to which first and second outputs of each of output pairs of the first to third differential pairs are connected in common; an amplifier stage receiving a signal from at least one node of the first and second nodes as an input and having its output connected to the output terminal; and a capacitance element. A data output period includes first and second periods.