Abstract: A differential amplifier comprises a left amplifier having transistors, a right amplifier having transistors, a negative feedback network having a resistor, and a negative feedback network having a transformer with a center tap. Phase compensation networks comprising a capacitor and a resistor, a capacitor and a resistor, and a capacitor and a resistor are further added to the amplifier. Both ends of a secondary winding of the transformer are connected to the output terminals of the right and left amplifiers, and the center tap of the secondary winding is grounded, so that a differential amplified output signal can be fed back to a single-phase input using one transformer, thereby reducing a cost and an area.

Abstract: Disclosed is a differential amplifier system that maintains high speed characteristics of the differential amplifier while providing stability from a common-mode loop by using dominant pole compensation. The disclosed system includes a first and second transconductance stage, a circuit having high impedance, and a compensation circuit.

Abstract: Common mode management between a DAC, such as a current-steering DAC, and a transconductance filter in a high-frequency transmission system. In one aspect of the invention, a transmission circuit includes a DAC that provides an analog signal from an input digital signal, and a filter such as a transconductance filter connected to the DAC, the filter receiving the analog signal and filtering the analog signal for transmission. A common mode management circuit connected to the DAC and the transconductance filter provides common mode compatibility in the interface connecting the DAC and the transconductance filter.

Abstract: An integrated circuit device may include an amplifier having an amplifier input configured to receive an input signal with the amplifier being configured to provide an amplifier output signal at an amplifier output responsive to the input signal received at the amplifier input. A capacitor may be coupled to the amplifier output, and a buffer may be coupled to the capacitor so that the capacitor is coupled in series between the amplifier output and an input of the buffer with an output of the buffer being coupled to a buffered signal terminal. A variable resistive feedback circuit may be coupled between the input and output of the buffer with the variable resistive feed back circuit providing a variable resistance between the input and output of the buffer.

Abstract: A first to a fourth sampling switch (1a to 1d), a first to a fourth sampling capacitance (4 to 7), and a first and a second charge redistribution switch (2a, 2b) are provided on the input side of a differential amplifier (8). A first and a second reset switch (3a, 3b) are provided between inputs and outputs of the differential amplifier (8). A positive-polarity input signal voltage (Vinp), a negative-polarity comparison reference voltage (Vrefn), a positive-polarity comparison reference voltage (Vrefp), and a negative-polarity input signal voltage (Vinn) are applied via the first to fourth sampling switches (1a to 1d) to one ends of the first to fourth sampling capacitances (4 to 7), respectively. During a reset period, the reset of the differential amplifier (8) is released after sampling of the voltages. During a comparison period, the first and second charge redistribution switches (2a, 2b) are caused to be in a conduction state.

Abstract: An integrated circuit system is provided including forming a differential pair; reducing a mismatch in the differential pair by: coupling an amplifier to the differential pair; and coupling a local feedback network to the amplifier in which referencing the local feedback network includes coupling a first voltage; and driving an output transistor by the amplifier.

Abstract: An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that that detects the offset of the amplifying unit outputs a signal for correcting the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value and includes a bias varying portion for varying a bias of the amplifying unit based on the output of the counter.

Abstract: Bias current generation circuits and systems are disclosed. In one embodiment, a gain boosting cascode system comprises a cascode based on a transconductance amplifier and a current buffer and a gain booster circuit coupled to the cascode optimally boosting a gain of the cascode by maintaining the transconductance amplifier and the current buffer in their respective saturation regions. The gain booster circuit is based on one or more feedback amplifiers coupled in series with a main voltage control transistor. The main voltage control transistor is maintained in a triode region, and the voltage at the drain of the main voltage control transistor can be set by passing an appropriate amount of current through the main voltage control transistor. This in turn would keep the transconductance amplifier and the current buffer in their respective saturation regions, thus generating the optimal gain for the gain boosted cascode system.

Abstract: In a first operational amplifier, an input signal is input to the negative input terminal, a reference voltage is input to the positive input terminal, a feedback path from the output terminal to the negative input terminal is formed, and the input signal is amplified by a predetermined amplification factor. In a second operational amplifier, an output from the first operational amplifier is input to the positive input terminal, the reference voltage is input to the negative input terminal, and a pair of outputs having opposite polarities to each other and used for performing BTL drive of a load are obtained at the output terminal. Using the above arrangement, a low-frequency signal can be amplified.

Abstract: An amplifier is described which amplifies an input signal according to a defined amplification factor, and which generates an output signal. To reduce an offset fraction of the output signal the amplifier comprises a feedback path which has lowpass characteristics and which returns the output signal in a lowpass-filtered state to an input of the amplifier. The feedback path comprises an amplifier stage as well as at least one Miller capacitance connected between an input and an output of the amplifier stage.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

Abstract: The present invention relates to a differential feedback amplifier circuit with cross coupled capacitors. Wherein, the first and second input terminals of a source follower are respectively coupled to the first and second output terminals of a differential amplifier, and a resistor is respectively coupled between the first output terminal of the source follower and the first input terminal of the differential amplifier and between the second output terminal of the source follower and the second input terminal of the differential amplifier in order to form a feedback loop. In addition, a capacitor is respectively coupled between the first end current source gate of the source follower and the second input terminal of the source follower and between the second end current source gate of the source follower and the first input terminal of the source follower, so as to improve the circuit gain and bandwidth.

Abstract: A differential transimpedance amplifier circuit comprises a first amplifier, a second amplifier and a first resistance having one end that communicates with the input of the first amplifier. A second resistance has one end that communicates with the second amplifier. A fourth amplifier has an input that communicates with the output of a third amplifier. Third and fourth resistances communicate with the input and output of the third and fourth amplifiers, respectively. Fifth and sixths amplifiers have an input that communicates with the output of the second and fifth amplifiers, respectively. Seventh and eighth amplifiers have an input that communicates with the output of the fourth, seventh amplifier. An opposite end of the first resistance communicates with the output of the eighth amplifier, and an opposite end of the third resistance communicates with the output of the sixth amplifier.

Abstract: A differential amplifier with a rail-to-rail input stage includes a feedback circuit that maintains the output common mode voltage of the amplifier within a narrow range of an externally supplied value. To reduce harmonic distortions and to further stabilize the output common mode voltage of the amplifier, current is controllably drawn from a biasing circuit coupled to an intermediate stage of the amplifier. Optionally, to reduce harmonic distortions and to further stabilize the output common mode voltage of the amplifier, current is controllably supplied to the intermediate stage of the amplifier.

Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).

Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: Provided is an operational transconductance amplifier (OTA). An existing Nauta transconductor used to implement a high frequency Gm-C filter integrated circuit (IC) is analyzed by a new method and from a new perspective to remove extra components and divide roles of remaining inverters for more simple and efficient circuit structure. In an existing Nauta transconductor, a common mode signal from an input terminal is amplified and appears at an output terminal, while in the inventive Nauta transconductor the common mode signal from an input terminal does not appear at the output terminal and is effectively eliminated. These enhanced characteristics can be achieved with a smaller number of inverters than an existing Nauta transconductor. Frequency characteristics of the filter can be effectively enhanced by independently controlling the quality factor without affecting the transconductance value required for frequency characteristics of the filter.

Abstract: An auxiliary current source is provided that includes MOS transistors feeding startup auxiliary current to the input portion of an output common mode voltage generation circuit amplifying the output of a differential amplifier and generating an output common voltage, and a correction current source is provided that includes MOS transistors feeding correction current corresponding to the auxiliary current to a common mode feedback comparator. Thereby, a control loop that controls the output common voltage to a predetermined voltage even when the input of the differential amplifier is outside the dynamic range at the beginning is correctly started up, thereby stabilizing the output common voltage at a desired voltage.

Abstract: In a double-loop negative feedback low noise amplifier having double negative feedback paths by a feedback transformer and a feedback resistor added to a cascode amplifier comprising transistors and a resistor, a phase compensation circuit comprising a capacitor and a resistor is added between the output terminal of the double-loop negative feedback low noise amplifier and the input terminal of the cascode amplifier, i.e., the input terminal of the input transistor, and a phase compensation circuit comprising a capacitor and a resistor is added to the upper-stage transistor of the cascode amplifier, i.e., the input terminal of the upper-stage transistor. Those phase compensation circuits enable a low noise negative feedback amplifier which maintains a high feedback loop gain to a high frequency band, has a wider bandwidth than a conventional one, and has a high dynamic range.

Abstract: Apparatuses and methods for providing offset compensation include a primary amplifier which includes a first output, a second output, a first load input, and a second load input, a first feedback loop connected to the primary amplifier and which includes a first switch located between the first output of the primary amplifier and the first load input, and a first sampling capacitor coupled to the first switch between the first switch and the first load input and a second feedback loop connected to the primary amplifier and which includes a second switch located between the second output of the primary amplifier and the second load input, and a second sampling capacitor coupled to the second switch between the second switch and the second load input.

Abstract: Disclosed is a differential amplifier including: first and second transistors each having a first gate, a second gate, a source, and a drain open to a drain side, the first gate and the second gate being controlled independently, a differential input being supplied to between the first gates of the first and second transistors, and the sources of the first and second transistors being connected in common to a first reference potential; first and second load circuits each connected to each of drain sides of the first and second transistors; a detection circuit detecting a common-mode voltage between ones of drain sides of the first and second transistors; and a comparison and amplification circuit amplifying the common-mode voltage in comparison with a second reference potential and supplying an output signal thereof to both of the second gates of the first and second transistors.

Abstract: A differential amplification circuit and a method corrects an offset voltage derived from a variance in resistances. With first and second input terminals brought to the same potential and set to a potential different from a reference potential, the resistance value of resistors is adjusted so that an output potential and the reference potential will be substantially equal to each other.

Abstract: Circuits and methods to achieve a voltage-to-current converter having low noise and a high linearity are disclosed. In a preferred embodiment the converter has been used as a Gm integrator. The core of the invention is an operational transconductance amplifier (OTA) having additional DC current sources allowing a common mode voltage shift. The feedback currents and output currents are decoupled by means of current mirrors. The feedback currents are higher than the output currents thus allowing lower integration resistor size. A common mode decoupling of input and output has been achieved by current mirrors.

Abstract: A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Abstract: An RF amplifier can include multiple gain stages, wherein each gain stage can be DC coupled to an adjacent gain stage. Each input gain stage can include either n-type gain transistors or p-type gain transistors. Multiple input gain stages can be designed/built by interleaving input gain stages of different types. Notably, an input gain stage including n-type gain transistors has a p-type bias transistor. Similarly, an input gain stage including p-type gain transistors has an n-type bias transistor. In this configuration, the bias transistor is the same type as the downstream gain transistors. Therefore, each bias transistor can accurately track the behavior of the transconductance devices of the next gain stage.

Abstract: Disclosed is a differential amplifier comprising first and second terminals for receiving signals; a third terminal for outputting a signal; first and second differential pairs, each having an input pair and an output pair, said first and second differential pairs being supplied with currents from current sources associated therewith, respectively; a load circuit connected to output pairs of said first and second differential pairs; an amplifier stage for receiving, as an input, a signal of at least one connection node of a connection node pair of said load circuit and output pairs of said first and second differential pairs, said amplifier stage having an output connected to said third terminal; and a connection switching circuit for controlling the switching between a first connection state in which first and second inputs of the input pair of said first differential pair are connected to said first terminal and said third terminal, respectively, and in which first and second inputs of the input pair of sai

Abstract: An amplifier circuit that is less likely to cause an error in a gain and a DC offset voltage and is suitable for reducing a size and power consumption is offered. A first resistor and a second resistor are connected in series between an input terminal and an output terminal. A third resistor and a fourth resistor are connected in series between a VREFL terminal and a VREFH terminal. A ratio of a resistance of the first resistor to a resistance of the second resistor is equal to a ratio of a resistance of the third resistor to a resistance of the fourth resistor. A voltage at a connecting node between the first resistor and the second resistor is applied to a first differential input terminal (?) of an operational amplifier, while either a voltage at a connecting node between the third resistor and the fourth resistor or VREFH is selectively applied to a second differential input terminal (+) of the operational amplifier.

Abstract: Embodiments disclosed herein relate to an amplifier stage or circuit for providing a signal boost. The circuit includes an emitter-follower pair and a cross coupled differential pair. The cross coupled differential pair provides a feedback signal that provides a boost to a signal output by the emitter follower pair. In some embodiments, a capacitor of the cross coupled differential pair may be adjustable in order to vary the amount of boosting provided. In other embodiments, a current source of the cross coupled differential pair may be adjustable in order to vary the amount of boosting provided.

Abstract: A variable gain amplifier circuit capable of eliminating circuit elements and the area for circuits when formed into an integrated circuit is disclosed. The circuit includes plural differential circuits, one of the input terminals of each of the differential circuits being connected in common to a signal input terminal, any one of the differential circuits being selected to operate; an output circuit having an input terminal connected in common to each output terminal of the differential circuits, the output circuit inputting an output signal of any of differential circuits and outputting an output signal from the signal output terminal; and plural resistors connected in series between the signal output terminal and a reference voltage terminal, in which each of junctions between the resistors is connected to one of the other input terminals of the differential circuits.

Abstract: An amplifier circuit comprises an amplifier circuit input and a first amplifier having an input that communicates with the amplifier circuit input and an output. A second amplifier has an input that communicates with the output of the first amplifier and an output. A first resistance has one end that communicates with the input of the first amplifier. An inverter that has an input that communicates with the output of the second amplifier and an output that communicates with an opposite end of the first resistance.

Abstract: A pre-amplifier for a receiver is provided. The pre-amplifier includes a first and a second input operational amplifiers, an output module, a first and a second feedback circuits. The first and the second input operational amplifiers amplify an input differential voltage pair to output a first and a second differential voltage pairs. The output module includes a first and a second output operational amplifiers and an inverter. The first and the second output operational amplifiers amplify the first and the second differential voltage pairs to output a first and a second output amplified voltages. The inverter pulls an output voltage high or low based on the first and the second output amplified voltages. The first and second feedback circuits are respectively for pulling up the first differential voltage pair or pulling down the second differential voltage pair, such that the first and the second output operational amplifiers are not disabled.

Abstract: A differential amplifying circuit capable of reducing amplitude-difference deviation over a full range of grayscale voltages inclusive of voltages in the vicinity of power-supply voltage includes first and second differential pairs of mutually different polarities, in which the outputs of the differential pairs are coupled by a coupling stage. One of the first and second differential pairs receives an input signal from an input terminal and a feedback signal from an output terminal at a pair of inputs thereof, and the other differential pair receives reference signals (which may be of the same voltage), which have voltage levels that set the other differential pair transistors to an on-state, at a pair of inputs of the other differential pair.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell.

Abstract: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting a second output signal according to the first output signal. The second-stage signal amplifier includes a first output transistor for outputting the second output signal. The gain control unit includes a first variable resistance device coupled to an input terminal of the first output transistor for adjusting voltage gain of the second output signal.

Abstract: A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

Abstract: A variable gain amplifying circuit comprises two stages, a first stage and a second stage with a common voltage-to-current converter. Each stage comprises two BJTs, two voltage controlled current sources, a variable resistor with a variable resistance, and the common voltage-to-current converter. The two BJTs construct a differential amplifier for amplifying a pair of differential signals. The variable resistor with the variable resistance is connected between the emitters of the two BJTs wherein the variable resistance of the variable resistor is represented as RE. The variable resistance RE is controlled by a control voltage Vctrl. The two voltage controlled current sources are respectively connected between the corresponding emitter of BJTs and ground. The currents respectively through the voltage controlled current sources are equal to each other and represented as IE. The current IE is controlled by the common voltage-to-current converter according the control voltage Vctrl.

Abstract: A CMOS amplifier of a filter for an ultra wideband application and a method of the same are provided. In the CMOS amplifier, an active load circuit adds a Zero location and increases a gain by MOSFETs, feeding back operation, and has a property of a high gain and a wide bandwidth. When the CMOS amplifier is applied to a biquad LPF, a high voltage linearity over about 200 mV peak-to-peak and an suitable ultra wideband property over about 320 MHz of an cutoff frequency may be achieved.

Abstract: An integrated circuit system is provided including forming a differential pair; reducing a mismatch in the differential pair by: coupling an amplifier to the differential pair; and coupling a local feedback network to the amplifier in which referencing the local feedback network includes coupling a first voltage; and driving an output transistor by the amplifier.

Abstract: An amplifier has a voltage to current converter coupled between a first potential and a reference potential and includes a control input coupled to a voltage at an input of the amplifier for converting the voltage at the amplifier input into a corresponding output current. A current multiplier is fed by the output current for producing an increased current. The increased current is fed to a control electrode of a transistor. A feedback element provides the first potential to the voltage to current converter by coupling a voltage produced by the feedback element in response current through the transistor to the voltage to current converter.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: A gain-boosted telescopic amplifier (100) includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (MP1, MN1), a pair of NMOS gain-boosted cascode transistors (MP2, MN2) and a pair of PMOS gain-boosted cascode transistors (MP3, MN3). The amplifier includes first and second clamping circuits driving the gate terminals of the pair of PMOS cascode transistors, respectively. The clamping circuits limit the gate voltage of the PMOS cascode transistors to be within a threshold voltage from the desired bias voltage. Each clamping circuit can include only a pull-down device, a pull-up device or both. In another embodiment, the amplifier includes clamping circuits driving the gate terminals of the pair of NMOS cascode transistors for limiting the gate voltage of the NMOS cascode transistors to be within a threshold voltage of the desired bias voltage.

Abstract: A transimpedance amplifier circuit comprises a first amplifier having an input, an output and a first transconductance. A second amplifier has an input that communicates with the output of the first amplifier, an output and a second transconductance. A first resistance has one end that communicates with the input of the first amplifier. A third amplifier has an input that communicates with the output of the second amplifier, an output and a third transconductance. A fourth amplifier has an input that communicates with the output of the third amplifier, an output and a fourth transconductance. An inverter has an input that communicates with the output of the fourth amplifier and an output that communicates with an opposite end of the first resistance.

Abstract: A differential transimpedance amplifier (TIA) circuit comprises first, second, third, fourth, fifth and sixth transconductance amplifiers having an input, an output and first, second, third, fourth, fifth and sixth transconductance gains, respectively. A first resistance communicates with said third transconductance amplifier and with said second transconductance amplifier. A second resistance communicates with said third transconductance amplifier and said third transconductance amplifier. A third resistance communicates with said sixth transconductance amplifier and said fifth transconductance amplifier. A fourth resistance communicates with said sixth transconductance amplifier and with said sixth transconductance amplifier. A fifth resistance communicates with said third transconductance amplifier and said fourth transconductance amplifier. A sixth resistance communicates with said sixth transconductance amplifier and said first transconductance amplifier.

Abstract: A balanced, differential, cross-coupled amplifier including an input stage for receiving a differential input and including an input transconductance differential pair and a feedback transconductance differential pair; and an output stage responsive to the input stage for providing a differential output; the differential input being connected to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair, the differential output being fed back to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair for balancing the currents in the transconductance differential pairs over the input range.

Abstract: The invention relates to an amplifier circuit comprising supply terminals (12, 14) for supplying the circuit with first and second supply potentials (Vdd, Vss); a current path, which runs from the first supply terminal (12) via a first biased transistor (P1a, P1b), a first node (K1a, K1b), an input transistor (Q1a, Q1b), a second node (K2a, K2b) and a second biased transistor (N1a, N1b) to the second supply terminal (14), wherein a control terminal of the input transistor is loaded with an input signal (inp-inn), and wherein the second node (K2a, K2a) forms a pick-up in a resistor chain (R2a, R1, R2b), at whose ends is supplied an output signal (outp-outn) as a voltage drop; and a feedback stage enabling the current to flow the resistor chain (R2a, R1, R2b) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q1a, Q1b) is essentially independent of the input signal (inp-inn), wherein the feedback stage has a pair of complementarily coupled transistors (P3a, N3a, P3

Abstract: Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line.

Abstract: An amplifier comprises an input circuit that receives an input to the amplifier. A start-up circuit communicates with the input circuit, generates a start-up signal, and turns off the start-up signal when an output of the amplifier reaches a threshold voltage. The start-up circuit includes a first transistor having first and second terminals and a base terminal and a second transistor having first and second terminals and a base terminal. The base terminals of the first and second transistors receive a bias input, the first terminals of the first and second transistors communicate with each other and with a first current source, and the second terminals of the first and second transistors communicate with the input circuit.

Abstract: Disclosed is a multi-level output differential amplifier which includes a first differential pair; a second differential pair; a load circuit commonly connected to output pairs of the first and second differential pairs; first and second current sources for supplying current to the first and second differential pairs, respectively; an amplifier stage for receiving a common output signal of the first and second differential pairs and driving an output terminal by a charging or discharging operation; and a control circuit for controlling changeover of signal inputs to the first and second differential pairs. The data output period includes first and second time periods.