Abstract: A reference circuit having a variable-impedance function for reducing current consumption is provided. By switching an output impedance of the reference circuit so that the output impedance is large when transmitting a high-frequency signal to a sensor coil, and the output impedance is small when receiving a response signal from the sensor coil, current consumption is reduced. The reference circuit includes a loop gain adjusting circuit having a switch for switching a gain. The magnitude of the output impedance of the reference circuit is switched by opening and closing the switch to switch the gain.

Abstract: A system of connecting errors in the control loop using multiple additional loops. A first loop carries out control in a desired way, and the additional loops are provided for the purpose of determining a specified error value. That specified error value may be, for example, a quiescent current. The specified error value is then used to correct for errors in the first loop.

Abstract: The invention pertains to an integrated circuit arrangement, in particular, in accordance with the CMOS technology, with at least one transconductance amplifier (1) in order to generate a current signal (outp, outm) from an input voltage signal (inp−inm), wherein the transconductance amplifier consists of a first transconductance stage (gm1) and a second transconductance stage (gm2) that are connected in parallel, wherein the first transconductance stage (gm1) has a transconductance that is essentially defined by an ohmic resistance and the second transconductance stage (gm2) has an adjustable transconductance that is essentially defined by a transistor arrangement, and wherein the transconductance of the first transconductance stage (gm1) is higher than the transconductance of the second transconductance stage (gm2).

Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier.

Abstract: A circuit for tuning a transconductance amplifier includes a first transconductance amplifier outputting a first current from its output, a second transconductance amplifier outputting a second current from an output that is coupled to the output of the first transconductance amplifier, and a feedback loop. The feedback loop provides a control signal that varies with a difference between the first current and the second current and is used to adjust the transconductance of the second transconductance amplifier.

Abstract: A low noise differential amplifier structure comprising a first amplifier provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. A second amplifier is provided with an output stage with a Miller capacitor having a first electrode and a second electrode connected to the input and the output of the output stage, respectively. The structure is characterized in that it comprises: at least a first trimming capacitor having a first electrode connected to the first electrode of the first Miller capacitor; at least a second trimming capacitor having a first electrode connected to the first electrode of the second Miller capacitor; and a cascode stage having an input receiving the output common mode voltage and an output connected to the second electrode of the first and second trimming capacitors.

Abstract: The present invention relates generally to an amplifier such as that with the radio frequency (RF) spectrum having a nonlinear feedback loop to cancel out distortions in the input signal, and method therefor.

Abstract: A cascode stage includes a gain boost circuit arrangement in a folded cascode type of operational amplifier. The gain boost circuit arrangement improves the overall DC gain of the operational amplifier while maintaining good low noise performance with the resistive loads. The cascode stage includes a current mirror circuit, resistive loads, and a regulated (or gain boosted) cascode circuit. The resistive loads are arranged to minimize thermal noise, while the regulated cascode circuit is arranged to increase the output impedance of a current mirror The increased output impedance results in higher DC gain in the operational amplifier. The increased DC gain and low noise characteristics may be implemented in bipolar and FET technologies.

Abstract: An amplifier with Miller-effect frequency compensation in which the Miller feedback capacitor is connected to an internal terminal of the amplifier having a low impedance, and shunt compensation circuitry is connected to an intermediate signal terminal that drives the output amplifier stage. The compensation circuitry, which includes serially coupled capacitive and resistive circuit elements, introduces a high frequency zero to cancel one of the high frequency complex poles introduced by the Miller feedback capacitor connection.

Abstract: An operational amplifier (op-amp) having a stage in parallel, dummy stage (212), with a final output stage (208) coupled to an initial stage (206). The dummy stage provides a desired Miller capacitance to the initial stage to isolates noise coupling between the power supply (214) and the output (204) and to improve the stability of the op-amp. By providing the dummy stage, the total capacitance required to achieve the desired noise isolation and stability is reduced thereby reducing the area required to implement the op-amp on an integrated circuit die.

Abstract: Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differential amplifier circuit, and to vary the common mode input voltage with the voltage threshold.

Abstract: The present invention provides a line termination circuit for matching the characteristic impedance of a transmission line, or more generally, a network. The present invention receives the voltage as present on the transmission line and attenuates it such that circuit components rated for lower voltages may be used to produce the reflected impedance. The attenuated voltage is placed across a scaled impedance which results in a reflected impedance substantially equal to the characteristic impedance of the transmission line. The line termination circuit uses a feedback loop to reflect the ground referenced scaled impedance across the transmission lines. The circuit generates a current having a value of one over the characteristic impedance of the network, which ensures that the reflected impedance, from the network, is substantially equal to the characteristic impedance of the network.

Abstract: A transconductance amplifier and method for improving the phase response and linearity. A differential amplifier circuit receives differential signals for amplification on respective bases of input bipolar transistors. The transistors amplify a small signal received on the based connections to produce an amplified output current. The differential amplifier circuit is connected to load impedances which form a cascode transconductance amplifier output stage. Feedback transistors provide a feedback voltage from the emitters of each of the different bipolar transistors to the base, improving the linearity of the differential amplifier. Phase compensation is provided by cross coupling through first and second capacitors a portion of each individual differential signal component to the base connections of the differential amplifier input transistor.

Abstract: The present invention discloses active unit cell topologies for quasi-optic grid array structures that make use of combinations of one of several broadband or frequency-selective positive (or regenerative) feedback networks, as well as multiple transistor configurations in order to enhance the gain of the grid array amplifier. These new topologies yield higher gain, extending the utility of the grid array amplifier to both new applications requiring higher gain, as well as to higher frequencies where the intrinsic gain of the active devices is lower. They also offer greater flexibility in impedance matching, improving the bandwidth and manufacturability of the design.

Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A differential transimpedance amplifier includes a differential transconductance stage to provide a current to a differential transimpedance stage. The differential transimpedance stage includes two gain stages and provides a voltage. A first feedback element is coupled in parallel with the differential transimpedance stage.

Abstract: A high gain amplifier includes an intermediate gain stage; an output gain stage driven by the intermediate gain stage; an input stage, for driving the intermediate gain stage, which is balanced between positive and negative feedback in normal operation; bias means for driving the input stage to maintain balance between positive and negative feedback in normal operation; and a resistance for limiting the output current of the intermediate stage in response to the input stage being overdriven into positive feedback.

Abstract: A current feedback amplifier is disclosed for providing a differential output based on a single-ended or differential input signal, having first and second low impedance inputs to receive first and second input signals, and first and second phase shifting systems providing first and second phase shifted input signals based on the second and first input signals. A first intermediate system provides a first intermediate signal comprising the first input signal and the first phase shifted input signal, and a second intermediate system provides a second intermediate signal comprising the second input signal and the second phase shifted input signal, wherein gains may be applied to one or more of the input and/or phase shifted signals. The amplifier further comprises first and second output buffers providing first and second differential output signals based on the first and second intermediate signals, respectively.

Abstract: Summarizing, the present invention provides an IVC (100), comprising an operational amplifier (110) with an inverting input (112) and an output (113), and a feedback resistor ladder network (120) coupled between the output (113) and the inverting input (112). The feedback resistor ladder network (120) comprises a main chain (121) composed of a plurality of substantially identical unit resistors (RU) connected in series, and a plurality of branches (124i), each branch (124i) coupling a node (Xi) in the main chain (121) to the inverting input (112) of the operational amplifier (110), each branch (124i) comprising a selectable feedback switch (123i). Further, some of the branches (124i) comprise a non-unit resistor (RNUi) coupled in series with the corresponding selectable feedback switch (123i). Further, the present invention provides a circuit comprising a FIRDAC (20) and a bias block (30) for providing at least one bias current for the FIRDAC (20).

Abstract: The differential amplifier circuit of the invention comprises operational amplifiers 3 and 4 having the negative inputs connected to input terminals 1 and 2 respectively, transistors 21 and 22 having the bases connected to each of the outputs of the operational amplifiers 3 and 4 respectively, constant current sources 41 and 42 connected between each emitter of the transistors 21 and 22 and a ground terminal 8 respectively, constant current sources 43 and 44 connected between each collector of the transistors 21 and 22 and a power supply terminal 7 respectively, a resistor 31 connected between the collectors of the transistors 21 and 22, transistors 23 and 24 having the emitters connected to each emitter of the transistors 21 and 22 respectively and the bases commonly connected to each other, and load resistors 32 and 33 connected between each collector of the transistors 23 and 24 and the power supply terminal 7 respectively.

Abstract: A differential linear amplifier includes a main differential amplification circuit, coupled to receive a differential input signal at the input of the amplifier and to generate a differential output signal at the output of the amplifier. Odd- and even-order compensation circuits respectively sample odd- and even-order harmonic currents in the main differential amplification circuit and amplify the sampled currents so as to generate odd- and even-order compensation signals for subtraction from the differential output signal. A filter provides phase matching of second- and third-order harmonic components at a desired frequency at the output of the amplifier between the differential output signal and the even- and odd-order compensation signals.

Abstract: A differential-input, differential-output CMOS amplifier having a first differential pair with a first transistor folded with a first cascode transistor, and a second differential pair with a first transistor folded with a second cascode transistor, and having a first auxiliary amplifier to provide negative feedback to the first and second cascode transistors to boost amplifier gain, where the first and second cascode transistors have gates at the same potential. The first differential pair has a second transistor folded with a third cascode transistor, and the second differential pair has a second transistor folded with a fourth cascode transistor, where a second auxiliary amplifier provides negative feedback to the third and fourth cascode transistors to boost amplifier gain, where the third and fourth cascode transistors have gates at the same potential.

Abstract: A system of connecting errors in the control loop using multiple additional loops. A first loop carries out control in a desired way, and the additional loops are provided for the purpose of determining a specified error value. That specified error value may be, for example, a quiescent current. The specified error value is then used to correct for errors in the first loop.

Abstract: An apparatus and method for utilizing a correction loop amplifier in conjunction with a main amplifier to produce signal amplification with low total harmonic distortion. The correction amplifier preferably has one input directly coupled to a first input of the main amplifier, and an output coupled to a second input of the main amplifier via a resistor. The second input of the correction amplifier is preferably coupled to a signal input via a voltage divider or RC network. A preferred embodiment configuration provides a power amplifier with improved THD over prior art circuits. The circuit is very flexible, and may incorporate low, high or band pass filter functions if desired. In addition, the power amplifier may be implemented in any combination of single or differential inputs and outputs.

Abstract: A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Abstract: The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1+A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.

Abstract: Several embodiments of an intermediate frequency (IF) amplifier, which exhibit improved distortion characteristics, are disclosed for use in an integrated transceiver circuit. The amplifier has a differential stage comprising two transistors which compare a voltage derived from an amplifier input signal with a voltage derived from the amplifier output signal to determine the portion of a bias current which will be supplied to one or more current mirrors. Output current from the one or more current mirrors is further used to bias an output transistor which drives a load impedance.

Abstract: The object of this invention is to realize high-speed rise and/or fall characteristics for amplifier without increasing transistor size or current consumption. A first rise sensing circuit 42 and a second a sensing circuit 44 are connected to main circuit 40. The first sensing circuit 42 has a PMOS transistor which functions as a rise sensing transistor, a pair of NMOS transistors 48 and 50, which form a current-mirror circuit, and a PMOS transistor 52, which drives the PMOS transistor 46 used for speed up in main circuit 40. The second sensing circuit 44 has a PMOS transistor 54, which functions as a fall sensing transistor, a pair of NMOS transistors 56 and 58, which form a current-mirror circuit, and a PMOS transistor 60 used for driving the PMOS transistor used for speed up in main circuit 40.

Abstract: A feedback system includes an emitter-follower as a gain stage in the forward path. The emitter-follower has a very wide band width and does not, by itself, effectively narrow the bandwidth of an information channel in which it is used. Emitter-followers are frequently used as buffers in many gain systems so using an emitter-follower which is already present effectively reduces die area for the feedback system. In an embodiment, the feedback system includes a differentiator with a programmable zero in the feedback path. The zero in the feedback path creates a pole in the forward path and the programmed location of the zero influences the pole and controls the bandwidth of the forward path. The emitter-follower also buffers the differentiator so that it does not effect the operation of any prior gain stages in which the feedback system is used.

Abstract: A buffer amplifier comprising a source follower-common drain circuit with a feedback path from the output of the drain follower to the input gate of the source follower. The feedback circuit is designed such that the output of the drain follower can be guaranteed to be at a voltage midway between the positive and the negative voltage supply of the circuit. This is the optimum operating point since it allows the largest signal swing. A small transconductance is realized by biasing the transistors of the feedback amplifier with very low currents; preferably by operating them in their weak inversion region. Feedback through the feedback amplifier is only present at DC (direct current) and at very low frequencies. This stabilizes the DC voltage at the drain of the common drain transistor, which, via an output capacitor, is also the output of the buffer amplifier.

Abstract: To provide an amplifier excellent in temperature characteristic and providing an output signal having small crossover distortion in a wide power source voltage range, voltage values provided to positive phase input terminals of a second and a third amplifier 2 and 3 are made to correspond to voltages between sources and drains of a second P-channel MOS transistor Tr3 and a second N-channel MOS transistor Tr4, a first P-channel MOS transistor Tr1 and a first N-channel MOS transistor Tr2 constituting a power buffer 4, are driven by an output signal of a first operational amplifier 1 via the second and the third amplifiers 2 and 3 and therefore, there can be provided idling currents independently from power source voltage from low power source voltage, there can be provided an output signal having small crossover distortion in a wide power source voltage range and temperature dependency thereof can be improved.

Abstract: A fully balanced transimpedance amplifier for high speed and low voltage applications is provided. An input stage of the amplifier uses a matched pair of common source connected transistors with sources tied directly to ground to eliminate the Vds overhead usually found in differential pairs. The ground connection minimizes a source resistance noise component, while matching minimizes power supply noise generation and susceptibility for an array of amplifiers. Feedback resistors along with diode connected MESFETS determine the transimpedance of the amplifier. The nonlinearity of diodes helps to soften clipping. Transresistance also determined the noise generated by the amplifier, and the diode connected MESFETS offer lower noise than resistors for the same impedance. Stability is achieved through use of only a single stage of gain in a loop of the input stage, while additional gain is achieved through cascading in the input stage.

Abstract: A differential amplifier includes two channels. Each channel has an input, an output, an emitter transistor, and a first current source. The channels are connected to one another via a resistor. In at least one of the two channels, a potential-shifting device is assigned to the first current source. A voltage-controlled, second current source is provided for linearization purposes. A third current source forms the output of the differential amplifier.

Abstract: A transconductance amplifier circuit, which may used in a subscriber line interface circuit, transforms a single ended input voltage into a precise, single ended output current, in a manner that is effectively independent of respective voltage supply rails, and which can be operated at a very low quiescent current. An operational amplifier is configured as a unity gain buffer whose output stage is coupled in circuit with first current flow paths of first and second current mirrors. A single ended output of the output stage serves as an input terminal and is coupled via a negative feedback path to a first, inverting input of the operational amplifier. Second current flow paths of the pair of current mirrors are coupled to an output port, which supplies an output current linearly proportional to the composite input voltage applied to the input terminal.

Abstract: A precision, low power operational amplifier employs a transconductance amplifier architecture to provide wide operational bandwidth at any closed looped gain, and maintain DC precision. A single ended output node/port, to which current paths of first and second current mirrors of the transconductance amplifier are coupled serves as a ‘non-inverting’ terminal. The first and second current mirrors include additional current mirror stages whose outputs are coupled to respective third and fourth auxiliary current mirrors. The outputs of the third and fourth current mirrors are coupled to an ‘inverting’ terminal. An output amplifier stage has its non-inverting input coupled to ground and its inverting input coupled to a feedback port. A gain-defining feedback resistor is coupled between the output and the feedback port of the output amplifier stage.

Abstract: There is disclosed a differential difference amplifier for amplifying an input signal close to a negative supply voltage and adding an offset voltage to the amplified input signal. The differential difference amplifier comprises: 1) a first non-inverting input terminal coupled to the input signal; 2) a first inverting input terminal coupled to the negative supply voltage; 3) a second inverting input terminal coupled to a feedback resistor coupled to an output of the differential difference amplifier; and 4) a second non-inverting input terminal coupled to the offset voltage.

Abstract: A semiconductor device includes a plurality of resistors each of which has a resistance that varies depending on voltage applied between contacts of the resistor. The semiconductor device includes a first resistor including a first resistive layer connected at a first contact to a first input wire and connected at a second contact to a first output wire, the first output wire having a first shielding portion which is connected to the second contact and shields the first resistive layer. A second resistor includes a second resistive layer connected at a third contact to a second input wire and connected at a fourth contact to a second output wire, the second output wire having a second shielding portion which is connected to the fourth contact and shields the second resistive layer.

Abstract: A class AB output stage includes an amplifying stage adapted to produce first (9) and second (10) output signals which incrementally increase and decrease in response to an incremental increase and decrease, respectively, of a first input signal (Iin1) and/or a second input signal (Iin2) A gate of a pull-up transistor (14) is coupled to receive the second signal (10), and a gate of a pull-down transistor (12) is coupled to receive the first signal (9). A first feedback circuit includes a first current sensing transistor (11) having a gate and source connected to the gate and source, respectively, of the pull-down transistor (12) and a drain coupled to a first control input (7) of the amplifying stage and operative to increase the gate voltage of the first current sensing transistor (11) only until its drain current increases to a first predetermined value representative of a minimum desired quiescent current in the pull-down transistor (12).

Abstract: The common-mode feedback circuit generates currents representing the output voltages of a fully differential amplifier, and sums these current to produce a summation current. Based on the comparison of the summation current to a reference current, the common-mode feedback circuit generates a feedback voltage for stabilizing the fully differential amplifier.

Abstract: A balanced type DDA 1 is combined with a single end type DDA 2 to form a differential amplifier circuit 3 which is a balanced type DDA. The balanced type DDA 1 has four input terminals VPP, VPN, VNN and VNP which are input terminals of two differential input stages, and two output terminals VoutP and VoutN which are output terminals of two output stages. These terminals are four input terminals and two output terminals of the differential amplifier circuit 3. The single end type DDA 2 has four input terminals, which are input terminals of two differential input stages and which are connected to the four input terminals of the differential amplifier circuit 3, respectively. The single end type DDA 2 also has an output terminal Vout of one output stage, which serves as a control output terminal for the feedback control of the differential amplifier circuit 3.

Abstract: In transconductance amplifier arrangements used in CATV systems, it is often desirable to set the value of the output impedance to a value equal to the system impedance that is often 75&OHgr;. prior art transconductance amplifiers often comprise an amplifier (6) with a current output using a feedback network (8) to set the gain value. An input of the feedback network (8) is coupled to the current output of the amplifier (6) and an output of the feedback network (8) is coupled to the input of the amplifier (6). In these prior art transconductance amplifier arrangements the output impedance decreases with increasing gain of the amplifier (6) used in the amplifier arrangement. This output impedance is normally very low (a few &OHgr; or lower). By adding a further output current (i/N) to the output of the feedback network, it is obtained that the current through the feedback network (8) becomes dependent on the output current (i) of the amplifier. This dependence results in an increased output impedance.

Abstract: A burst receiving circuit and a control method thereof whose unstable state of an output is able to be avoided without bringing about the decrease of the receiving level sensitivity and the deterioration of the output duty are provided. An offset which corresponds to the size of a receiving signal is given to the receiving signal and the offset is made to “0 ” at the time when the burst signal is received and the burst signal is taken out by shaping the receiving signal given offset based on a predetermined threshold value. And the offset is continued to be “0” until predetermined time has passed after finishing the burst signal. The offset is kept in “0” during the time from the start of the burst signal until predetermined time has passed after the finishing of the burst signal or until the finishing of the burst signal informed by the outside.

Abstract: An input signal is supplied to an adder circuit via a gain control amplifier and integrating amplifier and output signals of the gain control amplifier and the integrating circuit are added together by the adder circuit. An output signal of the adder circuit is supplied to a driving current generating circuit. The driving current generating circuit is constituted by first and second transistors whose bases and emitter are commonly connected. An externally attached resistor monitors a driving current flowing in the collector of the transistor constructing the driving current generating circuit and feeds back the current to the gain control amplifier. Therefore, the current control operation of high precision can be attained by use of a part of the driving current.

Abstract: A variable transconductance amplifier comprises transistors and whose emitters are connected via resistors and to a constant current source to form a differential or long tail pair. A feedback amplifier whose transconductance is controllable has inputs connected to the collectors of the transistors and outputs connected to the emitters thereof. The feedback amplifier thus supplies a differential current to the emitters of the transistors which corresponds to the product of the differential output signal of the transistors and the variable transconductance of the feedback amplifier.

Abstract: A self compensating operational amplifier (10) including a differential amplifier input stage (18) and a current mirror (24) having an input and an output coupled to the respective outputs (20, 22) of the differential amplifier input stage is provided that uses a feedback amplifier (28) which senses any voltages differences between the input and outputs of the current mirror as current is sourced or sank at the output (32) of the operational amplifier. The feedback amplifier produces a feedback current to the input side (20) of the current mirror wherein the voltage at the input side of the current mirror tracks the voltage swing at the output side of the current mirror so that the voltages track and are substantially matched.

Abstract: An amplifier circuit is responsive to an input data signal which is substantially DC balanced. The amplifier circuit is operative to generate an amplified data signal, and includes: a limiting amplifier responsive to the input data signal and to an error correcting signal, the limiting amplifier being operative to generate the amplified data signal; a feed back circuit responsive to a signal proportional to the amplified data signal, the feed back circuit being operative to generate the error correcting signal. The feed back circuit includes: a low pass filter responsive to the signal proportional to the amplified data signal, and operative to generate a filtered signal; and an error amplifier responsive to the filtered signal, and operative to provide the error correcting signal to the limiting amplifier; whereby offset voltage caused by process characteristics of the limiting amplifier, and temperature variations in the limiting amplifier are canceled by the error correcting feedback signal.

Abstract: A method and apparatus for a variable gain amplifier has a well-regulated common mode output. The invention has particular applications to CMOS integrated circuits and has other applications. In a specific embodiment, the invention is used with a regulated voltage source that has good stability over a wide bandwidth of load changes.

Abstract: A precision op amp test circuit employs latching relays, the contacts of which are latched open or closed as necessary to make test measurements. The relays' metal contacts ensure low resistance conductive paths, and because the coil of a latching relay need be energized only briefly to latch the contacts, the heating duty cycle of the coils can be kept low to substantially eliminate the accuracy-degrading thermal E.M.F. generated by the heat from the energized coil of a conventional relay. The test circuit is advantageously used for testing both VOS and IB for high precision, low-VOS op amps.

Abstract: A low noise, low current, high bandwidth differential amplifier circuit (30), including a first amplifier (44) driving a first transistor X1 and having a first current source I2 coupled to an input of the first amplifier (44). A first feedback resistor R3 is coupled between the first current source I2 and the first transistor X1, and a second resistor R4 is coupled to the first resistor R3. A second amplifier (46) drives a second transistor X2, and has a second current source I3 coupled to an input of the second amplifier 46. A third feedback resistor R5 is coupled between the second current source I3 and the second transistor X2. A fourth resistor R6 is coupled to the third resistor R5. The first R3 and third R5 feedback resistors are driven by the first I2 and second I3 current sources rather than by the first (44) and second (46) amplifiers, respectively, allowing the first and second amplifiers (44, 46) to be single stage amplifiers.