And Particular Biasing Arrangement Patents (Class 330/267)
  • Patent number: 10212383
    Abstract: The invention discloses a standby control circuit and a display device. The standby control circuit includes a standby module, at least one power board, and a transistor switch control module comprising at least one transistor switch whose number is equal to that of the at least one power board, each transistor switch is connected between one power board and a mains supply input terminal, the standby module is configured to generate a trigger signal and send the generated trigger signal to each transistor switch, and each transistor switch is configured to be turned on upon receipt of the trigger signal sent from the standby module so as to connect the power board connected thereto with the mains supply input terminal.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE MULTIMEDIA TECHNOLOGY CO., LTD.
    Inventors: Jiajian Zhang, Jianting Wang, Junning Su, Naijia Guo
  • Patent number: 10075174
    Abstract: A phase rotator apparatus has phase interpolation and transimpedance amplifier (TIA) stages. This separates gain and bandwidth as degrees of design freedom, facilitating a reduction in power consumption while enabling the data link to transmit and receive higher speed data. Four phases of an incoming signal are combined by the phase interpolation stage using weighting currents and current-source loads to produce a phase shifted current based signal that the TIA stage receives as input. The TIA stage then converts the signal to a voltage based signal. The quiescent operating voltage of the stage outputs can be maintained with common mode feedback circuits and injector currents.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William L. Bucossi, Hayden C. Cranford, Jr., Vivek K. Sharma, Fengqi Zhang
  • Patent number: 9859932
    Abstract: A receiver circuit may be provided. The receiver circuit may include a first duty cycle adjuster configured to correct a duty cycle of a first output signal pair. The receiver circuit may include a second duty cycle adjuster configured to correct a duty cycle of a second output signal pair, based on the first output signal pair, after the first duty cycle adjuster performs a correction on the duty cycle of the first output signal pair.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 9819309
    Abstract: The invention relates to a class AB amplifier for receiving an input current and generating an amplified output current and having first and second output transistors connected to provide the output current, wherein if the input current is less than a threshold the first output transistor is enabled and the second output transistor is disabled, and if the input current exceeds a threshold the second output transistor is enabled.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: November 14, 2017
    Assignee: SnapTrack, Inc.
    Inventor: Martin Wilson
  • Patent number: 9768743
    Abstract: A circuit includes a reference voltage circuit, a filter circuit configured to receive an output of the reference voltage circuit, and a voltage follower configured to receive an output of the filter circuit and generate a bias voltage. The filter circuit is configured to combine signals on a reference ground with the output of the reference voltage circuit. A method of providing a bias voltage includes generating a reference voltage using a reference voltage circuit, filtering the reference voltage to generate a second voltage using a filter circuit, and generating the bias voltage according to the second voltage using a voltage follower circuit. Filtering the reference voltage includes combining a fluctuation of the reference ground with the reference voltage.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: September 19, 2017
    Assignee: Marvell International Ltd.
    Inventors: Sai-Wang Tam, Philip Godoy, Ming He, Renaldi Winoto
  • Patent number: 9733662
    Abstract: Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: August 15, 2017
    Assignee: NXP B.V.
    Inventors: Kevin Mahooti, Sanket Gandhi
  • Patent number: 9581633
    Abstract: A relative angle detection apparatus includes a first magnetometric sensor and a first voltage amplifier that output a signal corresponding to a relative rotation angle between a first rotation shaft and a second rotation shaft; a first amplifier circuit that amplifies the output signal of the first voltage amplifier; a second magnetometric sensor and a second voltage amplifier that output a signal that corresponds to the relative rotation angle; a second amplifier circuit that amplifies the output signal of the second voltage amplifier; a first resistor that is provided between the first amplifier circuit and a power supply terminal, or between the first amplifier circuit and a GND terminal; and a second resistor that is provided between the second amplifier circuit and the power supply terminal, or between the second amplifier circuit and the GND terminal.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: February 28, 2017
    Assignee: SHOWA CORPORATION
    Inventor: Hiroyuki Muto
  • Patent number: 9473075
    Abstract: An amplifier system may include a current source, an impedance element responsive to a current change, and a feedback controller generating a control signal based on impedance element response. Current source may supply current to a pair of output elements, one of which being controlled by an integrator, and a portion of the integrator. Impedance element may have terminals coupled to inputs of the output elements and may be configured to experience a change in voltage based on a change in current supplied to its input. Feedback controller may have a pair of inputs coupled to the terminals of impedance element and an output to control the current source based on a detected change in voltage across the impedance element. Current source may be varied based on the control signal to maintain a constant current supplied to the input of the impedance elements.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: October 18, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventor: Sandro Herrera
  • Patent number: 9362872
    Abstract: The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: June 7, 2016
    Assignee: Marvell World Trade, Ltd.
    Inventors: Jinho Park, Yuan Lu, Li Lin
  • Patent number: 9225303
    Abstract: An output circuit for a class AB push-pull amplifier includes an upper cascode output stage and a lower cascode output stage. The upper cascode stage includes first and second PMOS transistors connected in series between a positive power supply node and an output node, the first PMOS transistor configured to receive a first complementary input signal. The lower cascode output stage includes first and second NMOS transistors connected in series between a negative power supply node and the output node, the first NMOS transistor configured to receive a second complementary input signal. The output circuit also includes a bias circuit configured for providing a first bias voltage to a gate node of the second NMOS transistor and a second bias voltage to a gate node of the second PMOS transistor, in which the first and the second bias voltages being substantially proportional to the output voltage.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 29, 2015
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Jan-Harm Nieland
  • Patent number: 8773203
    Abstract: An amplifier circuit for actuating a light diode is provided. The amplifier circuit may have a small output impedance of approximately 3 Ohms, a large bandwidth having a lower threshold frequency of 200 kHz and an upper threshold frequency of 5 MHz, for example, and an amplitude of the output current of several 100 mA, for example. The amplifier circuit may have an entry stage for actuating a driver circuit that actuates the light diode by means of a direct current supply.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: July 8, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Robert Baumgartner, Andreas Kornbichler, Joachim Walewski
  • Patent number: 8766722
    Abstract: Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Broadcom Corporation
    Inventors: Sherif Galal, Alex Jianzhong Chen, Khaled Abdelfattah, Todd L. Brooks
  • Publication number: 20140132349
    Abstract: The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 15, 2014
    Applicant: MARVELL WORLD TRADE LTD.
    Inventors: Jinho Park, Yuan Lu, Li Lin
  • Patent number: 8692179
    Abstract: The invention discloses an optical communication system using grounded coplanar waveguide, comprising a current buffer and a transimpedance amplifier (TIA). Transmission lines of the optical communication system have grounded coplanar waveguide (GCPW) structures. The current buffer receives a current signal from a signal source, and outputs the current signal after reducing capacitance effects of the signal source. The TIA converts the current signal to a voltage signal, wherein a first end of the TIA receives the current signal, a second end of the TIAn outputs the voltage signal, and a shunt-shunt feedback circuit is coupled between the first end and the second end. Therefore, the present invention can minimize the circuit area and lower the power consumption as well.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: April 8, 2014
    Assignee: National Tsing Hua University
    Inventors: Wei-Han Cho, Chia-Hou Tu, Shawn S. H. Hsu
  • Patent number: 8665023
    Abstract: Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: March 4, 2014
    Assignee: Broadcom Corporation
    Inventors: Sherif Galal, Alex Jianzhong Chen, Khaled Abdelfattah, Todd L. Brooks
  • Patent number: 8624673
    Abstract: The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: January 7, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Jinho Park, Yuan Lu, Li Lin
  • Patent number: 8552802
    Abstract: An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided to an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 8, 2013
    Assignee: Onkyo Corporation
    Inventors: Tsuyoshi Kawaguchi, Norimasa Kitagawa, Mamoru Sekiya, Naofumi Shimasaki, Yu Takehara
  • Patent number: 8547175
    Abstract: Provided is an output circuit capable of allowing a more sufficient output current to flow. When a drain current of a PMOS transistor (12) is large, a PMOS transistor (13) operates in the non-saturation region. At this time, gate voltages of NMOS transistors (14 and 17) have risen to around a power supply terminal voltage. Therefore, a gate-source voltage of an NMOS transistor (17) increases, and a sufficient output current flows.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: October 1, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Tsutomu Tomioka
  • Patent number: 8536947
    Abstract: A class AB amplifier with resistive level-shifting circuitry is described. In one exemplary design, the class AB amplifier includes an input stage, a resistive level-shifting stage, a class AB output stage, and a bias circuit. The input stage receives an input signal and provides a first drive signal. The resistive level-shifting stage receives the first drive signal and provides a second drive signal. The output stage receives the first and second drive signals and provides an output signal. The bias circuit generates a bias voltage for the resistive level-shifting stage to obtain a desired quiescent current for the output stage. In one exemplary design, the resistive level-shifting stage includes a transistor and a resistor. The transistor receives the bias voltage and provides the second drive signal. The resistor is coupled to the transistor and provides a voltage drop between the first and second drive signals.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: September 17, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Cheng-Han Wang, Tzu-wang Pan, Roger Brockenbrough
  • Patent number: 8502605
    Abstract: An input terminal is connected to a positive-phase terminal of a differential amplification circuit. A negative-phase terminal of the differential amplification circuit is connected to an emitter electrode of a transistor, and an output terminal thereof is connected to a base electrode of the transistor. An input side resistor is connected between a collector electrode of the transistor and the input terminal, and a secondary input side resistor is connected between the input terminal and a ground conductor. An output side resistor is connected between the emitter electrode of the transistor and the ground conductor. The collector electrode of the transistor is connected to a load terminal.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: August 6, 2013
    Inventor: Akira Fukushima
  • Patent number: 8497736
    Abstract: A power amplifier having a driver stage and an output stage is configured to provide an amplified RF input signal. The driver stage of the power amplifier consists of one or more driver circuits consisting of a network of transistors, current sources, capacitive elements and resistive elements. An RF input signal is fed into the driver stage which is configured to provide a dynamic DC bias and an RF signal gain to a base terminal of a Bipolar Junction Transistor (BJT) power device present in the output stage. The output stage includes of a network of transistors, capacitive and resistive elements and when driven by the DC bias and the RF signal from the driver stage produces an amplified RF input signal at an output side of the output stage.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 30, 2013
    Assignee: Anadigics, Inc.
    Inventors: Dirk Leipold, Wade Allen, Gary Hau
  • Patent number: 8493051
    Abstract: A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: July 23, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Vadim V. Ivanov, Harish Venkataraman, Susan A. Curtis
  • Patent number: 8487687
    Abstract: An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: July 16, 2013
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Xie-Ren Hsu, Ji-Ting Chen
  • Patent number: 8441319
    Abstract: An amplifier comprises: an input stage for receiving incoming signals; a high gain stage coupled to the input stage and providing driving signals in response to the incoming signals to an output driver stage; and an output terminal coupled to the output driver stage. The output driver stage comprises a high side driver circuit having a first terminal receiving a first driving signal pdrive from the high gain stage, a second terminal coupled VDD through a first voltage drop, and a third terminal coupled to the output terminal of the amplifier.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 14, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Aidan Cahalane
  • Patent number: 8405460
    Abstract: Integrated circuits with amplification circuitry are provided. The amplification circuitry may have an input terminal, an output terminal, a positive power supply terminal, and a ground terminal. The amplification circuitry may include first, second, and third stages. The first stage may provide biasing for the second stage. The second stage may provide biasing for the third stage. The second stage may provide paths for conveying an input signal from the input terminal to the third stage. The second stage may bias the amplifier to have low quiescent current and low shoot-through current. The second stage may prevent PVT variations such as supply voltage variations from affecting the quiescent current and shoot-through current of the amplifier. To increase the high-frequency response of the amplifier, capacitors may be added to the paths for conveying the input signal from the input terminal to the third stage.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: March 26, 2013
    Assignee: Aptina Imaging Corporation
    Inventor: Ken Hunt
  • Patent number: 8400221
    Abstract: An apparatus and method for biasing each amplifier of an amplification stage provides that the voltage across each current sensing element of each amplifier of the amplification stage is measured. For each pair of voltage measurements taken, a sum and difference is calculated, where the sum is processed to determine minima peaks and the difference is averaged. A portion of the sum term and the average of the difference term are summed to yield the individual bias current conducted by a first amplifier of the amplification stage. The difference between a portion of the sum term and the average of the difference term is calculated to yield the individual bias current conducted by the second amplifier of the amplification stage. The bias current conducted by the first and second amplifiers may then be individually modified manually, or conversely, may be modified automatically based upon the bias current measurements taken.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: March 19, 2013
    Assignee: Fender Musical Instruments Corporation
    Inventor: Charles C. Adams
  • Patent number: 8373505
    Abstract: An apparatus comprises an amplifier circuit and a detection circuit. The amplifier circuit includes a high voltage supply rail, a low voltage supply rail, and an output stage. The detection circuit is electrically coupled to the amplifier output stage and generates an indication when the output voltage at the output stage exceeds a specified output voltage threshold value. The amplifier circuit further includes a bias circuit configured to bias the amplifier circuit with a first bias current value when the output voltage is less than the specified output voltage threshold value, and bias the amplifier circuit with a second bias current value when the output voltage exceeds the specified output voltage threshold value.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: February 12, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Carmine Cozzolino
  • Patent number: 8354886
    Abstract: A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, ?). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: January 15, 2013
    Assignee: NXP B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans
  • Patent number: 8331893
    Abstract: A receiver has an input stage (LNA) that comprises, in a signal direction from an input (SI) to an output (SO), an input transistor (Q1) and an attenuator (D1, D2, R7-R12, C2-C5). The attenuator provides an attenuation that depends on a control signal (VDC). The input stage comprises a transistor-biasing circuit (R2) that biases the input transistor in dependence on the control signal.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: December 11, 2012
    Assignee: NXP B.V.
    Inventor: Efthimios Tsilioukas
  • Patent number: 8310307
    Abstract: The first emitter follower circuit and the second emitter follower circuit can increase an input impedance on the side of the inverting input terminal in the amplifying circuit. As a result, when a feedback circuit is connected between the inverting input terminal and the output terminal of the amplifying circuit, a fluctuation in a gain of the amplifying circuit according to a configuration of the feedback circuit can be suppressed.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 13, 2012
    Assignee: Onkyo Corporation
    Inventors: Tsuyoshi Kawaguchi, Mamoru Sekiya, Yu Takehara, Norimasa Kitagawa
  • Patent number: 8294518
    Abstract: Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: October 23, 2012
    Assignee: Broadcom Corporation
    Inventors: Sherif Galal, Alex Jianzhong Chen, Khaled Abdelfattah, Todd L. Brooks
  • Patent number: 8193863
    Abstract: According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Tsurumi
  • Patent number: 8159304
    Abstract: A current-feedback amplifier with at least one feed-forward capacitor at the input stage of the current-feedback amplifier is provided. In one embodiment, the current-feedback amplifier and feed-forward capacitor(s) are arranged as follows. The input stage includes two translinear loops, where each translinear loop includes a translinear element that is connected to the non-inverting input of the current-feedback amplifier. One feed-forward capacitor is in parallel with each translinear element that is connected to the non-inverting input of the current-feedback amplifier. In other embodiments, the feed forward capacitor(s) are arranged in a different manner.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: April 17, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Kwok Kit Lau
  • Patent number: 8130038
    Abstract: A class AB operational amplifier includes: a first transistor, for generating a first current; a second transistor, where a second source voltage of the second transistor is equal to a first source voltage of the first transistor, for generating an output stage quiescent current; and an output stage quiescent current controller, coupled to a gate and a source of the first transistor, for controlling a first drain-to-source voltage of the first transistor to be equal to a second drain-to-source voltage of the second transistor. A ratio of the output stage quiescent current to the first current is equal to a ratio of a second W/L ratio of the second transistor to a first W/L ratio of the first transistor.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: March 6, 2012
    Assignee: Anpec Electronics Corporation
    Inventors: Ming-Hung Chang, Che-Hung Lin
  • Patent number: 8031002
    Abstract: A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: October 4, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Yoo Sam Na, Yoo Hwan Kim
  • Patent number: 7999618
    Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: August 16, 2011
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Farhood Moraveji
  • Publication number: 20110133839
    Abstract: A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, ?). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
    Type: Application
    Filed: August 10, 2009
    Publication date: June 9, 2011
    Applicant: NXP B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans
  • Patent number: 7948316
    Abstract: An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is biased by a relatively small bias current with respect to an output current of the amplifier. The amplification portion provides an amplified output signal to the output portion. The amplifier further comprises at least one impedance component coupled between the output portion and the amplification portion to alter at least one pole associated with the amplifier to mitigate instability of the amplifier related to the relatively small bias current.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: May 24, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Wei-Chung Wu, Lin Chen, Yuan Gu, Kae Ann Wong
  • Patent number: 7944302
    Abstract: An apparatus and method for biasing each amplifier of an amplification stage provides that the voltage across each current sensing element of each amplifier of the amplification stage is measured. For each pair of voltage measurements taken, a sum and difference is calculated, where the sum is processed to determine minima peaks and the difference is averaged. A portion of the sum term and the average of the difference term are summed to yield the individual bias current conducted by a first amplifier of the amplification stage. The difference between a portion of the sum term and the average of the difference term is calculated to yield the individual bias current conducted by the second amplifier of the amplification stage. The bias current conducted by the first and second amplifiers may then be individually modified manually, or conversely, may be modified automatically based upon the bias current measurements taken.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: May 17, 2011
    Assignee: Fender Musical Instruments Corporation
    Inventor: Charles C. Adams
  • Patent number: 7936217
    Abstract: A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: May 3, 2011
    Assignee: QUALCOMM, Incorporated
    Inventors: Junxiong Deng, Gurkanwal Singh Sahota, Solti Peng
  • Patent number: 7920025
    Abstract: It was difficult to design an operational amplifier which can cancel an offset to drive a liquid crystal display. An operational amplifier includes: a first differential pair having a first transistor and a second transistor of a first conduction type; a second differential pair having a third transistor and a fourth transistor of a second conduction type; a first floating current source; a second floating current source; and an output stage having a fifth transistor and a sixth transistor, in which, when an input signal is applied to the first and third transistor, an electric current which flows into the fifth transistor and the sixth transistor is set by the first floating current source, and when the input signal is applied to the second and fourth transistor, an electric current which flows into the fifth transistor and the sixth transistor is set by the second floating current source.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: April 5, 2011
    Assignee: RENESAS Electronics Corporation
    Inventors: Kouichi Nishimura, Kazuo Suzuki
  • Patent number: 7907013
    Abstract: A class AB output stage includes a driver to generate a first drive signal and a second drive signal, and two bias voltage sources to provide two bias voltages to level shift the first and second drive signals, in order to drive a pair of high side and low side transistors, respectively. A control circuit provides a control signal to adjust the first and second bias voltages, so as to shift the bias point of the class AB output stage. The control signal is determined according to the currents in the high side and low side transistors and a programmable parameter. By adjusting the parameter, the bias point deviation can be removed to obtain both low quiescent current and best THD performance.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: March 15, 2011
    Assignee: Richtek Technology Corp.
    Inventor: Chao-Hsuan Chuang
  • Patent number: 7872531
    Abstract: Techniques for generating a bias voltage for a class AB amplifier having first and second active transistors. In an exemplary embodiment, a diode-coupled first transistor supports a first current, and the gate voltage of the first transistor is coupled to the gate voltage of the first active transistor. The first current is split into a second current and a first auxiliary current supported by a second transistor, which is biased at a desired common-mode output voltage of the class AB amplifier. The first auxiliary current is further combined with a third current to be supported by a third transistor, with the third transistor configured to replicate the characteristic of the second active transistor. Further techniques are provided for setting the drain voltage of the third transistor to be close to the common-mode output voltage. The techniques described herein may be used to provide a bias voltage for the NMOS and/or PMOS active transistors in a class AB amplifier.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: January 18, 2011
    Assignee: QUALCOMM, Incorporated
    Inventor: Vijayakumar Dhanasekaran
  • Patent number: 7834699
    Abstract: An audio apparatus is provided, receiving a reference voltage and an input signal to generate an output signal. In the audio apparatus, a compensation circuit, generates a compensated reference voltage based on the input signal, the reference voltage and the output signal. A class AB power amplifier receives the compensated reference voltage to amplify the input signal into the output signal.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: November 16, 2010
    Assignee: Fortemedia, Inc.
    Inventors: Li-Te Wu, Min-Yung Shih
  • Patent number: 7825732
    Abstract: This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Patent number: 7800447
    Abstract: A low-power, low-voltage feedback class AB operational amplifier is disclosed. The minimum supply voltage is one gate-source voltage and two saturation voltages. Currents on the output p-type and n-type transistors are monitored as part of the feedback loop control. Accurate monitoring is achieved by connecting current monitors directly to the corresponding voltage rail. Additional output stages may be selectively connected to the primary output stage to dynamically adjust to changes source conditions. Thus by connecting the appropriate number and type of additional output stages, continuous time adaptive power supply compensation is achieved. Both single ended and differential topologies are described.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: September 21, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Khiem Nguyen
  • Patent number: 7786804
    Abstract: A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: August 31, 2010
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Uday Dasgupta
  • Patent number: 7772926
    Abstract: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: August 10, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Eric Modica, Derek Bowers
  • Patent number: 7764123
    Abstract: A buffer amplifier having a wide output voltage range includes a first source follower circuit having a first current source and a first transistor, and a second source follower circuit having a second current source and a second transistor. The first source follower circuit has an output terminal connected to a gate of a third transistor and a source of a fourth transistor. The second source follower circuit has an output terminal connected to a gate of a fifth transistor and a source of a sixth transistor. First and second voltages are respectively supplied to the gates of the fourth and sixth transistors. The sixth transistor is operated in place of the fifth transistor in a low voltage range, and the fourth transistor is operated in place of the third transistor in a high voltage range.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: July 27, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Hiroyuki Kimura
  • Patent number: 7733182
    Abstract: Various embodiments of a hybrid class AB super follower circuit are provided.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: June 8, 2010
    Assignee: Agere Systems Inc.
    Inventors: Hiep The Pham, Nader Sharifi