Abstract: An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for providing a high output voltage and current reference signal suitably includes an output buffer configured with a compensation circuit for reducing disturbances introduced into the output stage amplifier circuit by voltage supply rails, such as parasitic ringing and other disturbances. The compensation circuit can suitably comprise a first compensation device, such as at least one capacitor, and a second compensation device, such as at least one capacitor. The compensation devices are suitably coupled between an input terminal of the output stage amplifier circuit and a pair of transistors proximate a pair of output transistors of the output stage amplifier circuit, and are configured to provide “pole-zero” compensation to the output stage amplifier circuit.

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract: An improved class-G amplifier (FIG. 2) is provided by adding a first capacitor (82) between the input of current mirror (18) and node p, and by adding a second capacitor (84) between the input of current mirror (20) and node m. The added capacitors (82) and (84) can be sized to stabilize frequency responses when high power supplies are enabled. The added capacitors (82) and (84) further function to reduce transient currents during switching through the crossover points between first upper and lower power supplies (Vsp1, Vsph) and between second upper and lower power supplies (Vsm1, Vsmh).

Abstract: The present invention provides technical advantages as a class AB output driver (400) with minimal cross-over distortion. If the differential input to the driver is I+&dgr;I/2 and I−&dgr;I/2, then the current gain is the average of &bgr;n and &bgr;p, more specifically, (&bgr;n−&bgr;p)*I+((&bgr;n+&bgr;p)/2)* &dgr;I. The offset current (&bgr;n−&bgr;p)*I is taken out with a feedback loop.

Abstract: An operational amplifier that decreases idling current, widens a voltage output range, and increases load driving capacity. The operational amplifier includes a first output transistor connected to a high potential power supply. A second output transistor is connected between the first output transistor and a low potential power supply. The first and second output transistors generate an output signal at a node between the first output transistor and the second output transistor. An idling current control circuit controls the collector current of the first output transistor in accordance with the base voltage of the second output transistor to control the idling current of the first and second output transistors.

Abstract: An operational amplifier input stage includes a first differential input transistor and a second differential input transistor receiving a differential input voltage. A first translinear loop is coupled to the first differential input transistor and a second translinear loop is coupled to the second differential input transistor. The first and second translinear loops are operable to supply an instantaneous current to the respective first and second differential input transistors to sufficiently charge capacitances therein during slewing conditions.

Abstract: An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.

Abstract: A class ‘AB’ amplifier output stage has an active current bias source that provides base drive current to the output transistors that is proportional to the signal input voltage level. The output transistor currents are modulated with the input signal such that the quiescent supply current is reduced to a very small level.

Abstract: An amplifier circuit that includes an amplifier stage and an output stage, and local feedback between these stages to drive a biasing string associated with the amplifier stage using the potential at the output stage. In one embodiment, the local feedback line is coupled between the output stage and the biasing string to remove the loading effect of the biasing string on the amplifier stage. In another embodiment, the local feedback line is coupled between the switches of the amplifier stage and the switches of the output stage to bias the amplifier stage using the output stage.

Abstract: The improved Class AB input stage monitors the needs of base current in the slewing transistors 22-25 and supplies that base current with extremely fast and precise feedback loops 90-93. This allows the input stage quiescent current to be very small and gets rid of the non-linearities associated with the lack of base current available to drive the slewing transistors 22-25 in a conventional prior art Class AB input stage. The input stage is a very efficient, low distortion, high small signals and full power bandwidth Class AB input stage.

Abstract: A method for adjusting the output response of a complementary bipolar operational amplifier includes: providing a first bipolar transistor 14; providing a second bipolar transistor 16 coupled to the first bipolar transistor 14; providing a first current source 26 coupled to a base of the first bipolar transistor 14; providing a second current source 28 coupled to a base of the second bipolar transistor 16; providing a third bipolar transistor 10 coupled to the base of the first bipolar transistor 14; providing a fourth bipolar transistor 12 coupled to the base of the second bipolar transistor 16; providing a first resistor 20 coupled between a base of the third transistor 10 and a common node; providing a second resistor 18 coupled between a base of the fourth transistor 12 and the common node; providing a capacitor 30 coupled to the common node; providing a first input stage current source 24 coupled to the first resistor 20; providing a second input stage current source 22 coupled to the fourth resistor 18;

Abstract: The present invention provides for an output stage which couples with an input stage and is configured to limit a reflection current which is reflected back into the input stage to enhanced an output voltage to drive a variety of loads. The present output stage limits the reflection current by compensating for at least one bias current at the input stage output. The output stage further reduced a quiescent current needed to maintain the output stage in an active state without adversely affecting the output voltage supplied to the load. The output stage includes a first and second current driving stage, a first and second current compensation circuit and an output circuit. The first and second current driving stages couple with both the input stage and the output circuit.

Abstract: An operational amplifier is provided which includes a first and a second output transistor which are selectively activated as a function of a potential difference between input signals to an inverting input and a non-inverting input of the operational amplifier to establish a connection between an output terminal of the operational amplifier and a positive voltage side of a dc power supply or a connection between the output terminal and a negative voltage side of the dc power supply, thereby outputting a signal from the output terminal as a function of the potential difference between the input signals in a wider voltage range.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A first amplifying transistor is connected between a first supply terminal and an output terminal, the latter being grounded via a loudspeaker system, and another such transistor between a second supply terminal and the output terminal. A first and a second drive transistor are Darlington connected respectively to the first and the second amplifying transistor. A first biasing circuit is connected between the first supply terminal and the base of the first drive transistor, and a second biasing transistor between the second supply terminal and the base of the second drive transistor. In order for an idling current of stable magnitude to flow immediately when the amplifier circuit is powered on, without need for preadjustment of circuit elements, an improved third biasing circuit is connected between the bases of the two drive transistors. The third biasing circuit comprises two biasing transistors and a serial circuit of two resistors.

Abstract: A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/&bgr; portion. Since the error current has no first order in 1/&bgr; portion, the current-to-current ronverter exhbits very low distortion.

Abstract: A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially from the second voltage supply. Collector voltage at the output stage is dynamically controlled to be greater than the emitter voltage by a difference voltage that increases proportionally as output voltage increases above the switch-over threshold. This difference voltage is commonly referred to as “headroom.

Abstract: An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.

Abstract: A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.

Abstract: A dual-drive coupling for an output stage of class AB amplifier is disclosed. A class AB amplifier comprises a PMOS output device and an NMOS output device coupled together. Two signal sources are used; one to drive the PMOS output device and one to drive the NMOS output device. The signal source driving the PMOS output device has a transconductance that is three times greater than the signal source driving the NMOS output device because the PMOS device is about three times bigger than the NMOS output device. A floating resistor network, comprised of an NMOS transistor and a PMOS transistor is coupled between the coupling of the signal sources with the output devices. A replica device can be added between the PMOS output device and its corresponding signal source to replicate the drain voltage of the signal source for the NMOS output device.

Abstract: A class AB amplifier having an output stage comprising complementary common source transistors (T1, T2) has means for setting the quiescent current. These comprise a bias resistor (R1) through which a bias current is passed and which is connected between the gates of transistors (T1 and T2) to set their voltages. The current through the bias resistor (R1) is derived from two reference transistors (T3 and T4) which each have the desired quiescent current passed through them by current sources (3, 5). The gate voltages of the reference transistors (T3, T4) are applied across a reference resistor (R2) and the current through the reference resistor (R2) is mirrored (T5 to T9) to the bias resistor (R1).

Abstract: A transistor saturation control circuit for controlling saturation of a PNP transistor. The control circuit includes current sense circuitry which produces a control output in response to a change in current of an N well associated with the PNP transistor. Base drive control circuitry operates to limit base drive to the PNP transistor in response to the control output.

Abstract: A push-pull amplifier circuit includes a push-pull output circuit having a P-channel FET 11 and an N-channel FET 10 connected in series between supply potentials VDD and VSS, a gate potential difference circuit 16A having ends OP and ON connected to the gates of the FET 11 and FET 10, respectively, wherein the voltage VPN between OP and ON is adjusted depending on a control signal VG3, an input circuit 17 for changing potentials of OP and ON in response to an input voltage VI while keeping the voltage VPN between OP and ON substantially constant, a constant current source 40 for outputting a reference current IS, and an idle current detecting and comparing circuit 30 for detecting a current proportional to an idle current flowing through the FET 11 and FET 10 and generating a control signal VG3 for the circuit 16A so that the detected current approaches a reference current IS.

Abstract: A class AB amplifier biasing circuit is provided for controlling the quiescent state of a pull-up output device and a complimentary pull-down output device. The biasing circuit includes first and second current sources, each having a floating resistor configured to supply current to the pull-up and pull-down devices, respectively. The biasing circuit also includes gate control circuits for controlling the gate voltages of the first and second floating resistors. A device replica transistor is connected to a voltage node associated with the gate of the either the pull-up device or the pull-down device.

Abstract: An amplifier output stage including a PNP transistor having an emitter coupled to a power rail and a collector coupled to an amplifier output. The PNP transistor is driven by an NPN transistor having a collector coupled to the base of the PNP transistor. A bias circuit produces a base-emitter voltage across the PNP transistor so that the PNP transistor will conduct a desired quiescent current. The bias circuit has an effective output impedance which is sufficiently large to form a pole in combination with a frequency compensation capacitor coupled to the collector of the PNP transistor, with the pole being located at a frequency beyond the unity-gain frequency of the amplifier.

Abstract: An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32).

Abstract: An output stage of a complementary bipolar operational amplifier includes: a first bipolar transistor 14; a second bipolar transistor 16 coupled to the first bipolar transistor 14; a third bipolar transistor 10; a fourth bipolar transistor 12; a first resistor 42 coupled between a base of the first bipolar transistor 14 and the third bipolar transistor 10; a second resistor 43 coupled between a base of the second bipolar transistor 16 and the fourth bipolar transistor 12; a first current source 26; a second current source 28; a third resistor 40 coupled between the first current source 26 and the third transistor 10; a fourth resistor 41 coupled between the second current source 28 and the fourth transistor 12; a fifth resistor 19 coupled between a base of the third transistor 10 and a common node; a sixth resistor 18 coupled between a base of the fourth transistor 12 and the common node; a first input stage current source 24 coupled to the base of the third transistor 10; and a second input stage current sou

Abstract: The invention relates to a Class AB operational amplifier providing both output gain enhancement and adaptative output bias. The operational amplifier includes first and second output terminals; a main differential stage having first and second differential inputs and a first differential output stage; a first adaptatively biased, boosted output stage coupling the first differential output stage to the output terminal. Each output stage includes a first NMOS output transistor having a control terminal, a first terminal coupled to the respective output terminal, and a second terminal, and includes a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to provide adaptative bias for the first boosted output stage, and an output coupled to the control terminal of the first output transistor.

Abstract: The Ultra Complementary Output Stage utilises both direct and bootstrapped drive for the output power devices in audio frequency power amplifiers operating in Class A, Class AB or Class B, in emitter follower, Sziklai pair/hybrid, or compound (eg. triple) configurations.

Abstract: A first amplifying transistor is connected between a first supply terminal and an output terminal, the latter being grounded via a loudspeaker system, and another such transistor between a second supply terminal and the output terminal. A first and a second drive transistor are Darlington connected respectively to the first and the second amplifying transistor. A first biasing circuit is connected between the first supply terminal and the base of the first drive transistor, and a second biasing transistor between the second supply terminal and the base of the second drive transistor. In order for an idling current of stable magnitude to flow immediately when the amplifier circuit is powered on, without need for preadjustment of circuit elements, an improved third biasing circuit is connected between the bases of the two drive transistors. The third biasing circuit comprises two biasing transistors and a serial circuit of two resistors.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (VDD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (VSS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180°. The dc bias circuit includes a dynamic bias boosting circuit for increasing the dc bias current provided to the amplifying transistor by the dc bias circuit in direct proportion to an increase in the input signal provided to the power amplifier. The bias boosting circuit permits the power amplifier circuits to operate in Class B or Class AB with improved power output characteristics and reduced power dissipation at low power levels.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: An electronic circuit for a Class AB output stage that has a differential input and a single ended output. A pair of clamp transistors are coupled between the bases of a pair of output transistors so that cross-over distortion is reduced and the output transistors do not completely turn off. A floating current source is employed to provide a stable quiescent current over a range of supply voltages. Also, the types and sizes of the transistors in the floating current source and the clamp transistors are matched so that any non-linear change in the operation of the clamp transistors caused by the Early effect over a range of supply voltages is automatically compensated for.

Abstract: A rail-to-rail op amp output stage is configured to provide one or more additional base drive paths for each of its output transistors, reducing the stage's distortion and increasing its maximum output current without substantially increasing quiescent current. The additional base drive paths reduce the demand on the transistors driving the output transistors, lowering the distortion they might otherwise contribute to the output current. In a preferred embodiment, the collectors of the stage's clamp transistors are connected to the bases of their opposing output transistors, so that each clamp transistor provides an additional base drive path to a respective output transistor, thereby increasing maximum output current without substantially increasing quiescent current, and substantially reducing crossover distortion.

Abstract: A monolithic power amplifier system is described which comprises a biasing system 50, transconductance amplifier circuit 42 and a transimpedance amplifier circuit 44 biasing network 50 is operable to generate a bias voltage which is used by the transimpedance amplifier 44. The transimpedance amplifier 44 receives an input current signal from the transconductance amplifier 42. The changes in the input current are communicated to a pull-up transistor 184 and a pull-down transistor 190 which drive an output voltage VOUT at sufficient levels to power the cathode of an electron gun of a video system.

Abstract: A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply. Collector voltage at the output stage can be maintained greater than the emitter voltage by a predetermined, substantially constant amount.

Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

Abstract: An operational amplifier circuit including a differential amplifier circuit and a current mirror circuit. The differential amplifier circuit amplifies a signal which enters a non-inverted input terminal and an inverted input terminal. The differential amplifier circuit receives resulting differential currents from an inverted current inflow terminal and a non-inverted current inflow terminal, and outputs corresponding differential currents from an inverted current outflow terminal and an non-inverted current outflow terminal to the current mirror circuit. The differential current flowing in the terminal is converted into a voltage by a load transistor so that the voltage drives a p-channel transistor, whereas the corresponding differential current flowing out from the terminal is converted into a voltage by a load transistor so that the voltage drives an n-channel transistor.

Abstract: A method and circuits are disclosed for an operational amplifier operating from a single cell 1.5 Volt supply which consumes very little power, and which can handle rail-to-rail input common mode and output signal swings. Low voltage and low power operation are made possible by biasing the CMOS transistors of the entire operational amplifier in the so called “sub-threshold” or “weak inversion” region of operation. This lowers VGSN and VGSP below VTN and VTP, and also lowers VDsat so that the operational amplifier can operate down to 0.9 Volt. The Class AB control circuit part of the operational amplifier can be applied to any conventional (normal biasing—other than weak inversion) low voltage Class AB output stage. The output stage of the operational amplifier is designed to source and sink more than 60 microAmperes of current into a 10 Kohm load while consuming only 4 micoramperes of current in the quiescent state.

Abstract: The present invention teaches a variety of output stages for amplifying high speed signals while keeping distortion low and using a low supply voltage. The invention includes the use of dual complementary signal paths that include a complementary push-pull output stage. Bias circuits are used to keep the paths symmetrical and positive feedback is used to oppose output loading effects.

Abstract: The present invention teaches output stages having distortion performance improved relative to prior art class-AB output stage distortion performance. The general concept is to constantly bias the feed-forward circuitry of the output stage into a low-distortion operating state. This can be done through several different methods, each of which has its own particular circuit requirements. For example, in one embodiment the bias circuitry generates a near constant bias current suitable for forcing the feed-forward circuitry into a low-distortion operating state regardless of the output stage output value.

Abstract: The present invention is directed to a buffer stage for buffering and isolating a signal source from an external load. The stage has a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal, corresponding to said input signal, to the external load. The stage comprises an input section including at least two driver transistors each arranged so as to operate with a predetermined bias current. The stage further comprises an output section including at least two output transistors each arranged so as to operate with a predetermined quiescent current, and a voltage source, coupled to the input and output sections and constructed and arranged so as to set the quiescent currents flowing through the output transistors substantially independent of the size of the bias current flowing through the driver transistors.

Abstract: The present invention reduces certain unwanted transients in an output stage by sensing the power supply and disabling the output stage output devices in correlation with the sensing of an invalid bias. In preferred embodiments, the bias is measured at a node that is the last bias node to reach a steady state during power up or power glitches. This ensures that all portions of the output stage are being provided a valid bias prior to enabling the output devices of the output stage. By enabling the output devices only after a valid bias is present, signals generated by the output devices are based upon valid operation of the output stage.

Abstract: A class AB CMOS output stage for an operational amplifier with a rail-to-rail output swing includes a pair of complementary control transistors connected in opposing phase to each other. Connection of the complementary control transistors is made between driving nodes of a pair of complementary output transistors driven by a differential signal. The differential signal is provided by a pair of differential signal input lines connected to an input stage of the operational amplifier. Biasing of the pair of complementary control transistors is by the differential signal.

Abstract: An LDMOS RF amplifier having a bias voltage generated through feedback around an LDMOS sense transistor has a sense transistor, a current sensing circuit that monitors current in the sense transistor, and a bias voltage generation circuit controlled by an output of the current sensing circuit. The bias voltage from the bias voltage generation circuit is applied to the gates of both the sense transistor and an LDMOS RF power amplifier transistor. An AC-coupled RF input signal is applied through typical impedance-matching circuitry to the gate of the RF power amplifier transistor, and an AC-coupled output signal is tapped from, and power applied to, the drain of the RF power amplifier transistor through impedance matching circuitry of the type known in the art.

Abstract: A rail-to-rail output circuit synthesizes a constant product output characteristic by replicating the current through a pull-up transistor and utilizing a translinear loop to drive a complementary pull-down transistor responsive to the replicated current. A smaller replication transistor shares a common V.sub.BE with the pull-up transistor so as to generate a scaled replication current that is proportional to the current through the pull-up transistor. The replication transistor is coupled to the base of the pull-down transistor through a bias circuit that forms a fast translinear loop with the pull-down transistor. An emitter follower transistor sevoes the loop so that the product of the currents through the pull-up and pull-down transistors is proportional to the square of a bias current. To reduce the turn-off time of the pull-down transistor, a second replication transistor is be connected with its base-emitter junction sharing the V.sub.