Abstract: A class AB output stage includes a driver to generate a first drive signal and a second drive signal, and two bias voltage sources to provide two bias voltages to level shift the first and second drive signals, in order to drive a pair of high side and low side transistors, respectively. A control circuit provides a control signal to adjust the first and second bias voltages, so as to shift the bias point of the class AB output stage. The control signal is determined according to the currents in the high side and low side transistors and a programmable parameter. By adjusting the parameter, the bias point deviation can be removed to obtain both low quiescent current and best THD performance.

Abstract: Techniques for generating a bias voltage for a class AB amplifier having first and second active transistors. In an exemplary embodiment, a diode-coupled first transistor supports a first current, and the gate voltage of the first transistor is coupled to the gate voltage of the first active transistor. The first current is split into a second current and a first auxiliary current supported by a second transistor, which is biased at a desired common-mode output voltage of the class AB amplifier. The first auxiliary current is further combined with a third current to be supported by a third transistor, with the third transistor configured to replicate the characteristic of the second active transistor. Further techniques are provided for setting the drain voltage of the third transistor to be close to the common-mode output voltage. The techniques described herein may be used to provide a bias voltage for the NMOS and/or PMOS active transistors in a class AB amplifier.

Abstract: An audio apparatus is provided, receiving a reference voltage and an input signal to generate an output signal. In the audio apparatus, a compensation circuit, generates a compensated reference voltage based on the input signal, the reference voltage and the output signal. A class AB power amplifier receives the compensated reference voltage to amplify the input signal into the output signal.

Abstract: This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.

Abstract: A low-power, low-voltage feedback class AB operational amplifier is disclosed. The minimum supply voltage is one gate-source voltage and two saturation voltages. Currents on the output p-type and n-type transistors are monitored as part of the feedback loop control. Accurate monitoring is achieved by connecting current monitors directly to the corresponding voltage rail. Additional output stages may be selectively connected to the primary output stage to dynamically adjust to changes source conditions. Thus by connecting the appropriate number and type of additional output stages, continuous time adaptive power supply compensation is achieved. Both single ended and differential topologies are described.

Abstract: A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.

Abstract: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor.

Abstract: A buffer amplifier having a wide output voltage range includes a first source follower circuit having a first current source and a first transistor, and a second source follower circuit having a second current source and a second transistor. The first source follower circuit has an output terminal connected to a gate of a third transistor and a source of a fourth transistor. The second source follower circuit has an output terminal connected to a gate of a fifth transistor and a source of a sixth transistor. First and second voltages are respectively supplied to the gates of the fourth and sixth transistors. The sixth transistor is operated in place of the fifth transistor in a low voltage range, and the fourth transistor is operated in place of the third transistor in a high voltage range.

Abstract: Various embodiments of a hybrid class AB super follower circuit are provided.

Abstract: An amplifier including complementary push and pull components, a bias component and a quiescent current balancer. The complementary push and pull components are serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal responsive to the input signal source. The bias component is coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal. The quiescent current balancer is coupled to the output terminal to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

Abstract: The present invention relates an output buffer and a power amplifier having the same. The output buffer includes a push-pull circuit unit, an output unit, and a driver. The push-pull circuit unit includes transistors connected to each others in a push-pull formation between a high level power voltage and a low level power voltage. The output unit is connected to the high level power voltage and the low level power voltage, and the driver drives the output unit according to a signal from the push-pull circuit unit.

Abstract: A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear loop, an input stage, a current biasing and enabling circuit. Further, the trans-linear loop is coupled to a signal input terminal ABIN via node A, and the push-pull output stage is coupled to the trans-linear loop via node B and node C. Further, the trans-linear loop includes a speed balancing resistor RB in a faster signal traveling path (i.e., ABIN to ABOUT via node A and B) to match up the speed with a slower signal traveling path (i.e., ABIN to ABOUT via node A and C). In another embodiment, the MOS transistors are also used instead of the speed balancing resistor RB to balance the signal traveling time of the two signal traveling paths.

Abstract: A unity gain buffer is provided. The unity gain buffer includes two complementary pairs of emitter followers and two bias current sources. The top bias current source is arranged to provide a bias current so that, if the input voltage is greater than zero, the bias current provided by the top current source increases at the input voltage increases. The bottom current source is arranged to provide a bias current so that, if the input voltage is less than zero, the bias current provided by the bottom current source decreases as the input voltage decreases.

Abstract: An output stage includes two transistors (switching transistor and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit adjusts the gate voltage on a biasing transistor based on the output node voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

Abstract: A driving amplifier circuit includes: a first driver for souring a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) coupled to a differential input signal for driving the first driver; a second operational amplifier coupled to the differential input signal for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit, coupled to the first bias circuit and the second bias circuit, for enabling either the first bias circuit or the second bias circuit according to a control signal; and a digital control circuit, coupled to the enabling circuit, for monitoring currents of the first driver and the second driver to generate the control signal.

Abstract: An amplifier driver circuit (10) includes first (11-1) and second (11-2) feedback amplifiers including first (14-1) and second (14-2) upper current mirrors, respectively, and first (16-1) and second (16-2) lower current mirrors, respectively, first (12-1) and second (12-2) amplifier input stages receiving a common mode input signal, and first (18-1) and second (18-2) amplifier output stages coupled to outputs of the first and second amplifier input stages, respectively. Each current mirror has an input (IN) and first (OUT1) and second (OUT2) outputs. Upper bias terminals of the first (12-1) and second (12-2) amplifier input stages are coupled to the inputs (IN) of the first (14-1) and second (14-2) upper current mirrors, respectively, and are cross-coupled to the second outputs (OUT2) of the second (16-2) and first (16-1) lower current mirrors, respectively.

Abstract: An amplifier biasing stage includes a transistor that provides a biasing signal for a complementary pair of field-effect transistors included in an output stage of an amplifier. The amplifier biasing stage also includes one resistive element connected to an emitter of the transistor, another resistive element connected to a base of the transistor, and still another resistive element connected to a collector of the transistor. The respective resistances of the resistive elements are selected to substantially match a voltage provided by the amplifier biasing stage to a gate-to-source voltage of the complementary pair of field-effect transistors. The resistances of the resistive elements are also selected to substantially match a temperature coefficient of the amplifier biasing stage to a temperature coefficient of the complimentary pair of field-effect transistors.

Abstract: A current mirror includes at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. The current mirror further includes a base current compensation block inserted between the input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference. The base current compensation block at least includes a bias current generator of a bias current and a first compensation transistor inserted, in series to each other, between the voltage reference and the input terminal, and a second compensation transistor inserted between the voltage reference and the common control terminals of the mirror transistors and having a control terminal connected to a control terminal of the first compensation transistor.

Abstract: A voltage-clamping device used in an operational amplifier is provided. The operational amplifier comprises a first transistor. The cross-voltage between the gate and the source of the first transistor is near to a specific voltage and the cross-voltage between the drain and the source of the first transistor is not equal to zero, so as to generate a big substrate current. The voltage-clamping device comprises a second transistor whose source and gate are respectively coupled to the drain of the first transistor and used for receiving a bias signal, so that the second transistor is biased in saturation region, and the voltage at the source of the second transistor is made equal to the difference between the bias signal and the threshold voltage of the second transistor. Thus, the cross-voltage between the drain and the source of the first transistor is reduced and the substrate current is reduced accordingly.

Abstract: A transconductance control circuit, comprising: a test transconductance circuit for providing an output current from a reference voltage; apparatus for deriving a bias current for the test transconductance circuit from the output current, the bias current including a component that varies with temperature and a component that varies with process; and apparatus for providing the bias current to other transconductance circuits.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A low voltage amplifier having a class-AB control circuit which generates minimal or no surge current when the output of the amplifier clips to ground or the negative rail. The amplifier includes an input stage, a summing circuit, a class-AB control circuit and an output stage. The input stage connects to a first current source and couples to receive a pair of differential input signals to generate intermediate signals that are summed together using the summing circuit. A second current source supplies the summing circuit with current. The class-AB control circuit receives the summed signals from the summing circuit to provide control for the output stage which generates the amplifier result at the output of the amplifier which delivers current to drive an external load.

Abstract: The present invention discloses an apparatus for slew rate enhancement of an operational amplifier, wherein an auxiliary control device and an auxiliary output device are added to the output stage of an operational amplifier. The auxiliary control device mirrors the current of the output stage and then compares the mirrored current with a reference current to generate an auxiliary push/pull control signal, which is used to control the auxiliary output device. When the output signal is different from the input signal, the auxiliary control device turns on the auxiliary output device to provide an auxiliary output current for the output terminal. When the output signal is equal to the input signal, the auxiliary output device is turned off.

Abstract: An amplifier includes a differential amplifier stage, a voltage amplification stage and a power output stage. The bias level of the output stage is proportional to current through the voltage amplification stage. The voltage amplification stage includes a current mirror whereby controlled current through a first leg of the current mirror controls current through the remaining, second leg, which, in turn, determines the bias level of the power output stage. Control circuitry senses a parameter of the amplifier, such as DC bias or input signal level to generate a control signal which is applied to the first leg of the current mirror to thereby control bias level of the power output stage.

Abstract: A radio frequency amplifier module (500) has a voltage monitor (546) that monitors an input supply voltage of an input power supply (534) and an adjustable power supply (512) that accepts power from the input power supply (534) and produces an adjustable power supply output that has a controllable voltage. The radio frequency amplifier module (500) further has an amplifier (402) that is supplied by the adjustable power supply output and that amplifies a radio frequency signal. The radio frequency amplifier module (500) also has an output controller (546) that is communicatively coupled to the voltage monitor and the adjustable power supply (512). The output controller (546) controls, in response to the input source voltage, the controllable voltage of the adjustable power supply output.

Abstract: It is an object of the present invention to provide an amplifier circuit that supplies a differential output signal (Voutp?Voutn) with a stable common mode potential (½×(Voutp+Voutn)) and a stable amplification characteristic. An essential feature of the invention is a control path (24, 26, 30, 28, 36, 38, 34, 32) feeding back into a control stage of the amplifier circuit for the combined control of the quiescent currents that flow through the output transistors (T1-T4), and of the common mode potential of the differential output signal. By means of this combination of two control functions in one and the same control path (24, 26, 30, 28, 36, 38, 34, 32) any coupling between separate control loops is avoided.

Abstract: An operational transconductance amplifier is configured with an asymmetric output current capability. When current sunk from the output exceeds a rated load, the normally equal input voltages diverge. A comparator coupled to the OTA inputs senses when the output current drain exceeds the rated load and changes state when the OTA input voltages diverge. When used in conjunction with a current mirror transistor of known proportion, current through an output transistor, such as quiescent current through the output stage of a class A/B amplifier, can be accurately detected. A current source in parallel with the OTA output can be used to offset the current sensing trigger point.

Abstract: Circuitry for increasing the maximum output current magnitude of a diamond buffer (Q57,58,74,75) having increased maximum output current provides a bias current of a first magnitude (I) into an emitter of a PNP first input transistor (Q57) and sinks a bias current of the first magnitude out of an emitter of an NPN second input transistor (Q55). The decrease is sensed in a collector current of the first input transistor caused by a demand for increased base current by a NPN first output transistor (Q74) of the diamond buffer. A collector current (Ic(65)) in an NPN another transistor (Q65) is increased in response to the decrease in the collector current of the first input transistor. The increased collector current in the first transistor is mirrored into a base of the first output transistor to boost its base current and maintain operation of the first input transistor when the amount of base current demanded by the first output transistor exceeds the first magnitude.

Abstract: There is provided a power amplifier circuit that applies an output voltage according to a given input voltage to a load, the power amplifier circuit includes an amplifying section of which an output port is connected to the load and that outputs the output voltage according to the input voltage, a source-side power source path that supplies an electric current output from the amplifying section via the output port to the amplifying section, a sink-side power source path that supplies an electric current drawn from the amplifying section via the output port to the amplifying section, a source-side capacitor that is connected between the output port of the amplifying section and the source-side power source path, and a sink-side capacitor that is connected between the output port of the amplifying section and the sink-side power source path.

Abstract: An integrated circuit radio transceiver and method therefor comprises circuitry that is operable to up-convert an outgoing continuous waveform signal to RF and that is further operable to down-convert and ingoing RF signal to one of a baseband or intermediate frequency in a manner that provides a linearized output current having an amplified current magnitude for mixing with a local oscillation in a mixer block. Specifically, a circuit portion is operable to produce a linearized current based upon an input signal. The linearized current is then produced to a current mirror block that produces a scaled and amplified output current. The scaled and amplified output current is then produced to a mixer block for mixing with a local oscillation to create the outgoing RF signal or the ingoing baseband or intermediate frequency signal.

Abstract: An output stage includes two transistors (switching transistor and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit adjusts the gate voltage on a biasing transistor based on the output node voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

Abstract: The present invention relates an output buffer and a power amplifier having the same. The output buffer includes a push-pull circuit unit, an output unit, and a driver. The push-pull circuit unit includes transistors connected to each others in a push-pull formation between a high level power voltage and a low level power voltage. The output unit is connected to the high level power voltage and the low level power voltage, and the driver drives the output unit according to a signal from the push-pull circuit unit.

Abstract: An integrated circuit radio transceiver and method therefor includes a linear regulator an output transistor for producing a current into an output node of the regulator wherein an amplification block is operable to produce a bias signal to a gate terminal of the output transistor to operably bias the output transistor to produce the current into the output node of the regulator. A current steering amplification block is operably disposed to steer current in/out of the gate of the output transistor (depending on device type) based upon the current being conducted through the output node of the regulator exceeding a specified threshold. The current steering amplification block further includes a current sinking element operably disposed to sink a specified amount of current to define the specified threshold.

Abstract: In one example, an amplifier for providing stable output quiescent current comprising includes a number of supply rails, an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails, and an output quiescent current controller coupled to the plurality of supply rails and the output device, the output quiescent current controller to regulate the voltage in the output device to provide a consistent quiescent current in the output device.

Abstract: A circuit capable of quiescent current control, the circuit comprising a first operational transconductance amplifier (OTA) including a first output terminal, a first transistor including a first gate coupled to the first output terminal of the first OTA, a second OTA including a second output terminal, a second transistor including a second gate coupled to the second output terminal of the second OTA, a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate, a first current source capable of providing a first current flowing toward the first terminal of the resistive load, and a second current source capable of providing a second current flowing away from the second terminal of the resistive load.

Abstract: A bipolar high output current buffer is disclosed using a negative feedback current mirror to supply the base drive to an output transistor. Small quiescent currents are used wherein the buffer demonstrates low quiescent power dissipation. The current mirror supplies the incremental base drive to the output transistor to support high output currents. When the output drive may source or sink the high output currents, two current mirrors may be used, one for each of the source and the sinking circuitry. This invention provides for minimal loss of dynamic range.

Abstract: Various source follower circuits and methods for implementing such are disclosed. As one example, a class AB source follower circuit is disclosed that includes a source follower circuit that is actively biased. The dynamic biasing allows the source follower circuit to sustainably sink a DC current. In some instances of the embodiments, the class AB source follower circuits are operable to source and sink both AC and DC currents.

Abstract: A differential amplifier includes an input stage circuit including a first differential pair and a second differential pair which are complementary to each other; a first current mirror circuit connected with the first differential pair and configured to function as an active load; a second current mirror circuit connected with the second differential pair and configured to function as an active load; an output stage circuit having a pair of output transistors connected in series between a higher power supply and a lower power supply; an operation point setting circuit configured to set an operation point of the output transistors; and a floating constant current source connected between an input terminal of the first current mirror circuit and an input terminal of the second current mirror circuit, and configured to supply a constant current.

Abstract: An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.

Abstract: An integrated circuit device includes an amplifier circuit that generates an output voltage. A bias control circuit is configured to generate a bias control voltage or the output voltage at an output thereof based on a state of a control signal. An output stage driver circuit that is responsive to the voltage generated at the output of the bias control circuit.

Abstract: An amplifying circuit which may be useful in a diamond buffer amplifier or operational amplifier includes an input transistor including an emitter, a collector, and a base coupled to receive an input voltage. An adjustable current source circuit is coupled between a first reference voltage and the emitter of the input transistor. A current source is coupled between a second reference voltage and the collector of the input transistor. An isolation resistor has a first terminal coupled to an output terminal of the adjustable current source circuit and a second terminal coupled to the emitter of the input transistor. A current follower circuit is coupled between the collector of the input transistor and an input terminal of the adjustable current source circuit. A feed-forward capacitor is coupled between the collector of the input transistor and the first terminal of the isolation resistor.

Abstract: Embodiments of RF power amplifiers are disclosed that include switched-mode power amplifiers supplied by synchronous buck DC-DC converters. The switched-mode power amplifiers can be used to amplify a limited form of an RF input signal and the supply to the switched-mode power amplifier is varied in response to the envelope of the RF input signal. One embodiment includes a switched-mode power amplifier connected to a synchronous buck DC-DC converter.

Abstract: A linear amplifier is configured with a current-feedback amplifier followed by a voltage-feedback amplifier to drive a totem-pole output stage. The output stage includes a series arrangement of an npn transistor and a pnp transistor with their emitters coupled in series and to an output node. The voltage amplifier driving the output stage is also configured with totem-pole elements, wherein a conductive path between the voltage-feedback amplifier and an output transistor is included to reduce conduction of the output transistor when the opposing output transistor is driven to increase conduction as a result of a high-frequency input signal. A capacitor may be included between the collector and base of a transistor in the circuit path that drives an output transistor in the output stage to briefly reduce its conduction when the opposing output transistor is driven to increase conduction.

Abstract: A compact semiconductor device for controlling impedance is provided. The semiconductor device has: a replica transistor of a transistor included in a control target circuit; and a substrate bias control circuit for controlling the impedance of the control target circuit by applying a substrate bias potential to the transistor in the control target circuit. The substrate bias potential is fed back to the substrate bias control circuit via the replica transistor.

Abstract: Provided is an amplifier including a system for controlling output stage quiescent current. The amplifier includes a driving stage including first pmos and nmos transistors coupled together, and an output stage connected to the driving stage. The output stage includes second pmos and nmos transistors coupled together. The amplifier also includes a quiescent control stage connected to the driving stage and including third pmos and nmos transistors coupled together, fourth pmos coupled to third pmos and 4th nmos coupled to 3rd nmos. A topology of the coupled third pmos and nmos transistors substantially matches a topology of the coupled first pmos and nmos transistors, and 4th pmos and nmos match to 2nd pmos and nmos.

Abstract: A push-pull amplifier includes a pair of transistors, wherein each of the transistors has a control terminal, a first terminal, and a second terminal. A current that flows between the first terminal and the second terminal is controlled in accordance with signals applied to the control terminal, such that when an amount of current flowing between the first terminal and the second terminal of one of the transistors is within a predetermined range, a high-frequency component of the signals input to the control terminal of one of the transistors is amplified, and when this current is outside the predetermined range, the high frequency component is not amplified.

Abstract: An amplifier capable of controlling the magnitudes of quiescent and output current, using externally supplied voltages. The amplifier includes: an input circuit converting a voltage difference between input signals into a current; an output circuit outputting an output current to the outside of the (class AB) amplifier (in response to a change in voltages at the first and second output nodes of the input circuit); a first control circuit generating a first bias current (when a first control voltage is applied), and a first control current; and a second control circuit generating a second bias current (whose magnitude is less than that of the first bias current) when a second control voltage is applied, and a second control current. In a first operating mode the first bias current controls the magnitude of quiescent flowing through the output circuit. The first control circuit and the output circuit form a current mirror.

Abstract: A class AB amplifier capable of easily controlling the amount of quiescent current and the amount of amplifier output current. The amplifier includes an input circuit that transform a voltage difference between input signals into a current; a current mirror including the (the Pull Up and Pull Down transistors of the) output circuit of the amplifier controls the quiescent current through the Pull Up and Pull Down transistors output circuit; and a control circuit in the current mirror (to which a first control voltage and a second control voltage are applied), adjusts the amount of quiescent current flowing through the output circuit in a first operating mode (by controlling a first bias current that is proportionate to the quiescent current in the current mirror), and controls the amount of the output current sourced or sinked (in response to the change in the voltages at the first and second output nodes of the input circuit) in a second operating mode.

Abstract: A buffer circuit is arranged for offset cancellation between an input voltage and a buffered voltage. The buffer circuit includes two bias current sources, two p-type transistors, and two n-type transistors. Further, the base-emitter voltages of the two p-type transistors and the two n-type transistors are arranged to form a translinear loop. The translinear loop is arranged to provide the buffered voltage from the input voltage. One of the bias sources is arranged to provide a bias current to one of the p-type transistors, and the other bias circuit is arranged to provide a bias current to one of the n-type transistors. One of the bias current circuits is arranged to actively sense the reverse saturation currents of the p-type transistors and the n-type transistors, and to provide its bias current so that the offset voltage between the input voltage and the buffered voltage is substantially cancelled.

Abstract: An amplification apparatus is provided that includes a plurality of gain stages including a first gain stage having first and second transistors and a second gain stage having third and fourth transistors. A plurality of replica stages may also be provided that includes a first replica stage and a second replica stage. Each replica stage may correspond/match one of the plurality of gain stages. An amplifying device may be provided to adjust a body potential of at least the first transistor of the first gain based on an output of the first replica stage and an output of the second replica stage.