Abstract: In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Abstract: A method and apparatus for frequency modulating a PWM involves 1) generating a high frequency carrier signal much greater in frequency than the PWM signal; 2) modulating the high frequency signal to generate a spread spectrum carrier signal; and, 3) retiming a PWM signal with this high frequency SS carrier signal so that the binary transitions of the PWM signal are aligned with the frequency varying carrier signal. In another embodiment, a PWM oscillator is driven by a second, FM oscillator having spread spectrum characteristics. In another embodiment a PWM oscillator is driven and modulated by a counter/frequency divider comprised of modules.

Abstract: A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage. The switching circuit has an inherent temperature profile associated therewith. A voltage divider circuit outputs a defined trip voltage that is compensated over the temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for the free running clock circuit. The voltage divider circuit has a top programmable resistor array connected in series with at least two programmable resistor arrays between two supply terminals of differing voltages.

Abstract: An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.

Abstract: In one embodiment, an oscillator circuit is configured to oscillate at a base frequency. The oscillator is configured to receive a synchronization signal and restart a period of the oscillator signal responsively to the synchronization signal.

Abstract: A micropower RC oscillator comprises a current generating section including a current source that generates a current; and a variable resistor of which the magnitude is variably set and which is configured by combining resistor elements at a predetermined ratio, the resistor elements having opposite characteristics to each other with respect to a temperature change, the variable resistor adjusting the magnitude of the generated current; a start-up circuit section connected to the current generating section and fixing a bias operating point to a constant value such that the current generating section stably generates a current; a charge and discharge circuit section including a variable capacitor, of which the magnitude is variably set, and a plurality of transistors, the charge and discharge circuit section charging and discharging the variable capacitor by using the current generated from the current generating section and the plurality of transistors; an oscillation signal output section connected to the ch

Abstract: An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

Abstract: Circuits, systems, and methods for generating a variable oscillator output. The circuits generally comprise a capacitor configured to receive first and second currents of a first polarity (e.g., charging currents) and a third current of a second polarity opposite to the first polarity (e.g., a discharge current). The circuit further comprises a first circuit configured to receive a bias input, a second circuit configured to receive a coarse control input, and a third circuit configured to receive a fine control input. The first circuit is further configured to provide the first current in response to the bias input. The second circuit is further configured to provide the second current in response to the coarse control input, such that the second current generally has a magnitude of from zero to a multiple of the magnitude of the first current.

Abstract: Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

Abstract: A comparator with a fixed reference voltage (self bias) for an oscillator is disclosed. The comparator includes: a depletion MOS network to form a source current, wherein the gate and the source has a connection; and an enhanced MOS transistor, wherein the drain or the source connects with the depletion MOS transistor in series. The gate of the enhanced MOS transistor receives an input voltage when the input voltage is lower than the reference voltage, and the comparator outputs a high level voltage, or the enhanced MOS transistor outputs a low level voltage if the input voltage is higher then the reference voltage. Moreover, the oscillator's comparator has a reference voltage that is independent from temperature and supply voltage source.

Abstract: A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and the current mirror for charging a capacitor when a voltage thereof is lower than a predetermined threshold voltage and for discharging the capacitor when the voltage thereof is higher than the predetermined threshold voltage, thereby generating a clock signal at a predetermined frequency, wherein the charge control module adjusts the predetermined frequency by changing the predetermined threshold voltage.

Abstract: A temperature-dependent oscillator includes a first current source, wherein a first current provided by the first current source has a positive temperature coefficient, a second current source serially connected to the first current source, wherein a second current provided by the second current source has a negative temperature coefficient, and a capacitor serially connected to the first current source and parallel connected to the second current source.

Abstract: A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a temperature detection unit for detecting temperature at a proximity of the CR circuit, a storage unit for storing data that enables the multiplied frequency of the clock signal in an output from the multiplier to have a constant value based on a temperature-dependent oscillation characteristic of the oscillator, and a control unit for setting a multiplication value for generating the multiplied frequency of the clock signal to the multiplier based on the data in the storage unit that is correlated to the temperature detected by the temperature detection unit.

Abstract: An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.

Abstract: An integrated tuner includes circuitry to receive a television signal, a quadrature mixer coupled to the output of the circuitry, a polyphase filter coupled to the output of the quadrature mixer, a relaxation oscillator, and a digital calibration module. The relaxation oscillator generates a clock having a period that is directly proportional to the on-chip RC time constant. The clock is fed into a counter of the digital calibration module. The counter is started and stopped at predefined time intervals by a finite state machine. The finite state machine updates the calibration code based on a successive approximation algorithm according to the end count results received from the counter. The digital calibration module outputs the updated calibration code to the polyphase filter and to the relaxation oscillator.

Abstract: The invention provides an oscillator circuit that reduces the dependence of an oscillation frequency on a power supply voltage. A charging and discharging circuit is a circuit switchable between an initializing operation setting an initial voltage for discharge and a discharging operation, and outputs a clock when the discharge is completed. The clock is inputted to a set terminal of a RS flip-flop. A signal formed by delaying an output signal of the RS flip-flop by a delay circuit is inputted to a reset terminal of the RS flip-flop. The output signal of the RS flip-flop is inverted to a discharge enable signal by an inverter, and the discharge enable signal is inputted to a switching circuit of the charging and discharging circuit. With this structure, the charging and discharging circuit alternately repeats the initializing operation and the discharging operation, and by the initialization the discharging operation is always started from the power supply voltage.

Abstract: An oscillator circuit having a closed loop connection, including: an oscillator for generating an output signal oscillating at a frequency corresponding to a control signal; a frequency/voltage converter for generating a detection signal having a voltage corresponding to a frequency of the output signal; a difference detector for generating a difference signal indicating a difference between the detection signal and a reference signal; and an integrator for generating the control signal by integrating the difference signal.

Abstract: A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

Abstract: An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.

Abstract: A variable frequency multi-phase oscillator for providing multi-phase signals is disclosed. The variable frequency multi-phase oscillator includes a correlator, a plurality of delay cells, and a NOR circuit. Each delay cell includes a current supply, a capacitor, a comparator, a switch, and a logic unit. The plurality of delay cells generate the multi-phase signals that are phase correlated within a large frequency range. The frequency and duty cycles of the multi-phase signals are adjustable.

Abstract: An oscillator circuit includes a capacitor, a first constant current source electrically couplable to an end of the capacitor, a second constant current source electrically couplable to the end of the capacitor, a control circuit coupled to the end of the capacitor, a first reference potential, and a second reference potential to switch, in response to a comparison of a potential at the end of the capacitor with the first and second reference potentials, between a first operation to charge the capacitor by electrically coupling the first constant current source to the end of the capacitor and a second operation to discharge the capacitor by electrically coupling the second constant current source to the end of the capacitor, and a circuit configured to have an output signal thereof exhibiting a signal transition in response to timing at which the switching occurs between the first operation and the second operation.

Abstract: The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.

Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Abstract: In a timer circuit of a semiconductor circuit including a current source driven by a power supply voltage, the current source outputs a current dependent on the power supply voltage, and outputs a reference voltage obtained when the power supply voltage is dropped by a predetermined drop voltage. A capacitor is charged with electric charges by the current outputted from the current source. The comparator compares a voltage across the capacitor with the reference voltage from the current source, and outputs an output signal when a voltage across the capacitor is equal to or higher than the reference voltage. The timer circuit outputs an output signal after a delay time, from a timing when supply of the power supply voltage is started, to a timing when the voltage across the capacitor rises substantially in proportion to an elapsed time by charging the capacitor and reaches the reference voltage.

Abstract: An electric circuit includes a circuit path from a first reference voltage to a second reference voltage lower than the first reference voltage. The path includes a current generator, a capacitor, a first switching element suitable for connecting or disconnecting the capacitor with respect to the current generator. The first switching element has a triggering value and the electric circuit includes a second switching element placed in parallel to the capacitor and control elements suitable for acting on the first and second switching elements for controlling the charging and discharging of the capacitor. The control elements comprise a comparator operable during the charging of the capacitor and suitable for acting on the first switching element for blocking the charging of the capacitor when the voltage value at its terminals reaches a threshold voltage value. The threshold voltage value is lower than the triggering voltage of the first switching element and higher than the second reference voltage.

Abstract: An RC oscillator circuit is disclosed. The RC oscillator circuit includes a current generator configured to generate a charge current. The RC oscillator circuit also includes an integrator having an input and an output, the input being connected to the current generator. The RC oscillator circuit also includes a comparator having a first input, a second input, and an output, the first input being connected to the output of the integrator and the second input being configured to supply a reference threshold. The RC oscillator circuit also includes a clock pulse generator connected to the output of the comparator and a reference generator configured to generate the reference threshold based on a supply voltage of the RC oscillator circuit.

Abstract: The invention relates to an electronic circuit comprising a first comparator having a first input offset voltage, wherein the first comparator is operatively coupled to a first sampling capacitor, a second comparator having a second input offset voltage, wherein the second comparator is operatively coupled to a second sampling capacitor, and a control circuit operatively coupled to the first comparator and the second comparator for generating alternate cycles having a first phase and a second phase, wherein a first sampled offset voltage is stored in the first sampling capacitor during the first phase of the alternate cycles, wherein the first sampled offset voltage is subtracted from the first input offset voltage during the second phase of the alternate cycles, wherein a second sampled offset voltage is stored in the second sampling capacitor during the second phase of the alternate cycles, and wherein the second sampled offset voltage is subtracted from the second input offset voltage during the first phas

Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

Abstract: A tunable oscillator comprises a control supply configured to output a control output operable to tune the tunable oscillator. The tunable oscillator further comprises an oscillator circuit configured to output a signal such that a frequency of the signal increases with increasing control output. A control circuit is configured to control the frequency of the oscillator circuit signal in response to a comparison of the oscillator circuit signal with a reference signal. A propagation delay compensation circuit is configured to vary an amplitude of the reference signal at substantially the same frequency as the oscillator circuit signal to compensate for propagation delay of signals from the control circuit to the oscillator circuit.

Abstract: An oscillator comprises a data storage unit, an oscillation unit, and a control unit. The data storage unit is adapted to store a plurality of reference condition codes and a plurality of reference control codes. The oscillation unit is adapted to output an oscillation signal having an oscillation frequency that varies according to a control code. The control unit is adapted to generate the control code with a target value based on the reference condition codes and the reference control codes and a current condition code input to the control unit. Where control code has the target value, the oscillation unit outputs the oscillation signal with the oscillation frequency substantially equal to a target oscillation frequency.

Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

Abstract: An oscillator circuit includes a capacitance element; an inverter outputting an inverted voltage at a first terminal of the capacitance element; a voltage source including a resistor and an NMOS transistor connected in series between a first high-potential power supply and a ground power supply and outputting a voltage from a node to which the resistor and the NMOS transistor are connected; a switch circuit connecting a second terminal of the capacitance element to the voltage source or the ground power supply in accordance with the voltage output from the inverter; and a constant-current source connected to a second high-potential power supply and allowing, regardless of changes in the voltage and temperature of the second high-potential power supply within certain ranges, flow of a constant current into or out of the first terminal of the capacitance element in accordance with the voltage output from the inverter.

Abstract: A triangular wave generating circuit capable of reducing a time lag between the time of input of a discharging start signal and the time of start of actual discharging is provided.

Abstract: An RC oscillator integrated circuit includes: an active current mirror connected to an external resistor, for receiving a current signal corresponding to a voltage signal applied to the external resistor, performing 1/N-times division of the received current signal according to an input clock signal, and generating a 1/N-times current signal; an oscillation circuit for generating an output voltage corresponding to a charging- or discharging-operation of a capacitor via a current path formed by the active current mirror; a feedback switching circuit for controlling a charging- or discharging-path of the capacitor by a feedback of an output signal Vo of the oscillation circuit; and a divider for generating not only a first clock signal capable of driving the active current mirror according to the output signal of the oscillation circuit, but also a second output clock signal having a compensated mismatch of the active current mirror.

Abstract: An RC oscillator is provided. The oscillator includes an RC selecting switch disposed in an input port of the oscillator, a resistor output port, a capacitor output port, at least a resistor switch with a first end connected to the RC selecting switch and a second end floatingly connected to the resistor output port, and at least a capacitor switch with a first end connected to the RC selecting switch and a second end floatingly connected to the capacitor output port. The second ends of the resistor switch and the capacitor switch are selectively connected to the resistor output port and the capacitor output port respectively for providing different combinations of a resistor output value and a capacitor output value.

Abstract: A clock oscillator system for use in providing the switching regulator duty cycle control in a fixed frequency (no cycle skipping) operation is provided. In one embodiment, the circuit according to the invention uses an analog feedback loop to extend the switch ON time of the clock cycle by controlling the oscillator charging current and, thereby, increase the duty cycle. Preferably, this circuit can achieve very high switching duty cycle and/or very low switching duty cycle in a PWM switching regulator operated in very low drop-out operation when very high duty cycle is required or in other conditions when very low duty cycle is required.

Abstract: A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators.

Abstract: A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the relaxation oscillator and a second ramp signal that is periodic at the frequency of the relaxation oscillator and is out of phase with respect to the first ramp signal The first ramp signal is compared to a first reference voltage and the state of a first flip-flop is changed if the first ramp signal exceeds the first reference voltage. The second ramp signal is compared to the first reference voltage and the state of a second flip-flop is changed if the second ramp signal exceeds the first reference voltage. The first flip-flop is reset in response to a first level of the first ramp signal and the second flip-flop is reset in response to a second level of the second ramp signal.

Abstract: There is provided an RC oscillation circuit capable of adjusting an oscillation frequency, and an oscillation method thereof. The RC oscillation circuit including: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

Abstract: There are provided relaxation oscillators and methods for controlling the same. A relaxation oscillator includes a load device, a switching device, a fine-tuning varactor, and a current source. The load device is configured to provide a variable oscillator output based on a variable input reference voltage. The switching device is connected in signal communication with the load device and is configured to become active and inactive based on the variable oscillator output. The fine-tuning varactor is connected in signal communication with the switching device and is configured to provide fine-tuning of the variable oscillator output when the switching device is active. The current source is connected in signal communication with the switching device and is configured to provide coarse-tuning of the variable oscillator output when the switching device is active.

Abstract: A timing circuit operates by applying an arbitrary voltage across a resistance, and using the resulting current to generate a charging current which charges and/or discharges a capacitance to an endpoint voltage. Additional circuitry is arranged such that the capacitance is charged and/or discharged until its voltage crosses a threshold which is proportional to one of the resistance's endpoint voltages, such that the capacitance's endpoint voltage tracks the resistance's endpoint voltage. Thus, the resistor voltage can vary with supply voltage or temperature, or the resistance value itself can vary, without materially affecting the timing relationships. The arbitrary voltage is preferably provided with a pair of diode-connected transistors connected in series with the resistance, so that a single transistor operated at the same current density as one of the diode-connected transistors establishes the threshold voltage and detects when the capacitor voltage reaches the threshold.

Abstract: An oscillator circuit is disclosed that includes a first oscillation part configured to output a first oscillation output by charging and discharging a first capacitor, and a second oscillation part configured to output a second oscillation output by charging and discharging a second capacitor. The second oscillation part includes a phase difference detection part configured to detect the phase difference between the first oscillation output and the second oscillation output, and a charging current and discharge current control part configured to control the charging current and the discharge current of the second capacitor in accordance with the phase difference detected by the phase difference detection part so that the second oscillation output synchronizes with the first oscillation output.

Abstract: An oscillator according to the present invention reduces power consumption by enlarging the pulsewidth of an oscillator output pulse. Since this pulse disables an oscillator current source, the enlarged pulsewidth reduces the time the current source is enabled. When a first capacitor charges to at least a reference voltage, a differential amplifier produces a low level signal that is provided to a latch generating the output pulse. The low level signal controls the latch to produce and maintain a high level signal until the latch is triggered. The latch signal disables the current source, while enabling a transistor to transfer charge from the first capacitor to a second capacitor. When the second capacitor attains a sufficient voltage, the latch is triggered to produce a low level signal, thereby enlarging the pulsewidth of the output pulse. The low level signal enables the current source and facilitates discharge of the second capacitor.

Abstract: A CR oscillation circuit comprises first and second logic elements, a capacitive element, and a resistive element. The first logic element is connected between a first node and a second node. The second logic element is connected between the second node and a third node. The capacitive element is connected between the first node and the second node. The resistive element is connected between the first node and the third node. The capacitive element includes a well, a diffusion layer, a gate electrode and a gate oxide film. The capacitive element has a voltage-dependence characteristic such that its capacitance value varies according to the variation in a supply voltage. The capacitance value of the capacitive element decreases when the on-resistance of the first and second logic elements increases according to the variation in the supply voltage.

Abstract: The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node1) when the output stays in low, for discharging the stored charge of node1 when the output stays in high, a comparator (C1) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref0), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuit 2 for controlling the discharge current based on constant current.

Abstract: A memory circuit that generates a positive temperature correlated clock frequency is described. One embodiment includes a voltage reference having a voltage determined at least in part by a diode or transistor having a negative temperature coefficient. A clock generator generates a clock having a frequency that is based at least in part on the voltage reference voltage so that the clock frequency has a positive temperature correlation. A memory charge pump is enabled at least in part by the clock.

Abstract: An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a constant cycle regardless of the shift in the power supply voltage which can keep constant the duration period of internal control signals of devices, such as a timer and a pump circuit, which are synchronized to the reference clock.

Abstract: An R-C oscillator (200) is configured to vary the two voltage levels that are used to control the oscillation, such that the variation in oscillation frequency with temperature is minimized. A first resistor (R1) is used to control one of the voltage levels, and a second resistor (R2) having a temperature coefficient that differs from the temperature coefficient of the first transistor is used to control the other voltage level. The first resistor (R1) also controls the current used to charge and discharge the capacitor (C) used to effect the oscillation. By the appropriate choice of resistance values, the variations of the control voltages and current are such that the time to charge and discharge the capacitor (C) between the control voltages remains substantially constant with temperature. Preferably the resistance values are selected to also compensate for temperature variations in the delay of the feedback loop.

Abstract: A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.

Abstract: An integrated circuit includes an oscillator circuit, where a frequency of an oscillator output signal provided by the oscillator circuit is adjustable by either coupling a resistor to an input pin, or by applying an external clock signal to the input pin. The oscillator circuit includes a comparator, a follower, a current-controlled oscillator, and a switch circuit. The switch circuit is coupled between the input pin and a node that is coupled to the current-controlled oscillator. Also, the follower is arranged to cause the voltage at the node to be at a pre-defined voltage unless the voltage at the node is overdriven by an external clock signal. The comparator circuit is arranged to determine whether the signal at the input pin is a clock signal. If it is determined that the signal at the input pin is a clock signal, the switch circuit is opened.