Abstract: An oscillation circuit includes: a first oscillation circuit and a second oscillation circuit, wherein the first oscillation circuit includes a first input side electrode electrically connected to a first oscillator and a first output side electrode electrically connected to the first oscillator, and the second oscillation circuit includes a second input side electrode electrically connected to a second oscillator and a second output side electrode electrically connected to the second oscillator, wherein the distance between the first output side electrode and the second input side electrode is greater than the distance between the first input side electrode and the first output side electrode.

Abstract: The present invention is an oscillator which implements matched resonators which are driven at a same frequency, one hundred-eighty degrees out-of-phase. The resonators may be implemented in a same plane of a printed circuit board and located adjacent to each other, thus the resonators are affected by a same (ex.—same magnitude of) vibration interference. However, in the oscillator embodiments described herein, the vibration interference component cancels out of (ex.—is eliminated from) the oscillator output signal, leaving only the desired component.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a digital audio circuit which converts an input digital signal into an analog audio signal, a DC-DC converter having a switching power source circuit, and an audible frequency determining circuit. In order that a difference between a frequency of a first clock signal for digital to analog conversion which is used in the digital audio circuit and a frequency of a second clock signal for switching control which is used in a DC-DC converter exceeds a maximum audible frequency, a frequency comparing circuit in the audible frequency determining circuit outputs a signal to a frequency changing circuit in the DC-DC converter. The frequency changing circuit causes a second oscillating circuit to change the second frequency.

Abstract: An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Abstract: A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency.

Abstract: An oscillation device for reducing memory capacity includes a frequency difference detecting unit and a compensation value obtaining unit. When oscillation frequencies of the first and second oscillation circuits are respectively f1 and f2, and oscillation frequencies of the first and second oscillation circuits at a reference temperature are respectively f1r and f2r, the frequency difference detecting unit determines a difference corresponding value x corresponding to a difference value between a value corresponding to a difference between f1 and f1r, and a value corresponding to a difference between f2 and f2r. The compensation value obtaining unit obtains a frequency compensation value of f1 resulting from ambient temperature different from reference temperature based on the difference corresponding value x, and calculates the frequency compensation value of f1 by calculating nth-order polynomial for X being a value corresponding to x/k, where k is a divide coefficient specific to a device.

Abstract: A signal generator provides a plurality of oscillating signals, whereby each oscillating signal has a different peak voltage and has a predictable and consistent phase relationship with the other oscillating signals. The signal generator includes a plurality of stacked oscillators arranged between two reference voltages, such that each oscillator in the stack generates an oscillating signal having a different peak voltage. Each oscillator stage in a designated oscillator includes a transistor that is connected to a transistor of a corresponding stage in another oscillator. This arrangement of the oscillators provides for charge transfer between the corresponding stages to provide for similar voltage swings in each oscillating signal, as well as to provide for predictable phase relationship between the oscillating signals.

Abstract: In a dual-hand capable voltage-controlled oscillator (VCO) device at least two voltage-controlled oscillator units (VCO1, VCO2) are coupled via a reactive component (A) and each said at least one voltage-controlled oscillator unit (VCO1, VCO2) further being connected to at least a respective external switching device (B1, B2) adapted to control an operating frequency of the (VCO) device.

Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.

Abstract: A tunable multiphase ring oscillator includes a plurality of stages connected in series in a ring structure, where each stage generating a stage output from a stage input. Each stage of the tunable multiphase ring oscillator includes a plurality of trans-conductance cells, each generating an output from at least one portion of the stage input. Each stage further includes at least one phase shifting module for imparting at least one phase shift to the at least one portion of the stage input, an oscillator unit for generating the stage output from a combination of the plurality of outputs, and means for varying at least one of the plurality outputs so as to adjust a phase of the stage output.

Abstract: A plurality of inductance enhanced interweaved rotary traveling wave oscillators (RTWO) is disclosed. Portions of the transmission line conductors are increased in length and run in parallel. Because the currents in these portions travel in the same direction, the inductance of these inductors is increased. By controlling the length of the transmission line conductors in these areas compared to the lengths where the currents in the oscillators travel in opposite directions, the overall impedance of the oscillators can be increased. Increased impedance leads to lower power and lower phase noise for the oscillators. Additionally, the interweaved oscillators are phase-locked to each other.

Abstract: An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC unit provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.

Abstract: An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.

Abstract: A circuit includes an oscillator circuit including a first oscillator and a second oscillator. The first and the second oscillators are configured to generate signal having a same frequency and different phases. A transmission line is coupled between the first and the second oscillators.

Abstract: A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

Abstract: A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal.

Abstract: In one embodiment, a method includes generating, by a LCVCO, a first signal having a first phase based on a resonant frequency of a first LC tank; generating, by a second LCVCO, a second periodic signal having a second phase based on a resonant frequency of a second LC tank; determining a phase offset between the first LC tank and the second LC tank based on the first and second signals; generating a first output signal and a second output signal based on the determined phase offset; and adjusting the phase offset such that the phase offset is substantially equal to a predetermined phase offset. In one embodiment, the adjusting comprises modulating a first impedance of the first LC tank based on the first output signal, and/or modulating a second impedance of the second LC tank based on the second output signal.

Abstract: A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.

Abstract: In one embodiment, a circuit comprises a first inductor-capacitor based voltage-controlled oscillator (LCVCO) generating a first periodic signal with a first frequency and a first phase and a second LCVCO generating a second periodic signal with a second frequency and a second phase, and the second phase is offset relative to the first phase by a 90 degrees offset.

Abstract: A system for random number generation includes a digital oscillator circuit, which has a set of available configurations and is operative to generate a random number sequence in accordance with a current configuration selected from the set. The system further includes a randomization circuit, which is operative to produce a pseudo-random stream of values corresponding to the available configurations of the digital oscillator circuit, and to control the digital oscillator circuit to alternate among the available configurations in accordance with the pseudo-random stream of values.

Abstract: A wideband oscillation circuit outputting oscillation signals (divided signals) of continuous frequencies is disclosed and the wideband oscillation circuit includes an oscillator that outputs an oscillation signal, a filter that filters the oscillation signal output from the oscillator and outputs an injection locked signal, and an injection locked frequency divider that performs a free-run operation and outputs a divided signal of the oscillation signal while its oscillating operation is regulated by the injection locked signal, the division ratio of which varies in accordance with a control signal, wherein the filter generates the injection locked signal by controlling the passing characteristic that caused the oscillation signal to pass with respect to time in accordance with a filter control signal locked with the divided signal.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: An oscillating device is provided that has several oscillators. Each oscillator has a capacitive inductive resonant circuit and a flow-through conduction circuit having a negative flow-through conduction. The inductive elements of the oscillators are mutually coupled. Each oscillator also has short-circuit or not short-circuit the capacitive element of the oscillator. The oscillating device also has a controllable commutating means arranged to activate one oscillator at a time.

Abstract: Provided are a differential voltage-controlled oscillator (VCO) and a quadrature VCO using center-tapped cross-coupling of a transformer. The differential VCO and the quadrature VCO can be driven by low power through a current reuse structure and have an excellent phase noise characteristic by center-tapped cross-coupling through a transformer. Further, variable capacitance units for frequency variation are divided into variable capacitance units for coarse tuning and variable capacitance units for fine tuning. Therefore, it is possible to obtain a wide tuning range while voltage oscillation gain is reduced. Further, the differential VCO and the quadrature VCO are configured in such a manner that the respective variable capacitance units operate linearly throughout the entire capacitance region due to control voltage distribution by resistors. Accordingly, it is possible to obtain a linear control voltage-oscillation frequency characteristic.

Abstract: An oscillation circuit includes: n ring oscillators each formed from m delay elements connected annularly, m being an integer equal to or greater than 2, n being an integer equal to or greater than 2; and a phase coupled ring.

Abstract: Provided is a surface mount crystal oscillator and a substrate sheet to prevent a decrease in a frequency variable amount by reducing electrostatic capacitance of the crystal oscillator. The surface mount crystal oscillator and the substrate sheet are each configured such that one end of a crystal holding terminal is connected to a corner terminal, and another end of the crystal holding terminal is formed from a center of a short side to be shorter than the one end so as to form an area in which no pattern is formed, and a pattern of a GND terminal is formed on that portion of a rear surface of a substrate which is opposed to the area in which no pattern is formed, so that the pattern (a crystal-mounted pattern) of the crystal holding terminal and the pattern of the GND terminal are not opposed to each other across the substrate.

Abstract: A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.

Abstract: The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.

Abstract: Oscillators and methods of manufacturing and operating an oscillator are provided, the oscillators include a base free layer having a variable magnetization direction, and at least one oscillation unit on the base free layer. The oscillation unit may include a free layer element contacting the base free layer and having a width less than a width of the base free layer, a pinned layer element separated from the free layer element, and a separation layer element between the free layer element and the pinned layer element. A plurality of oscillation units may be arranged on the base free layer.

Abstract: A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.

Abstract: The present invention provides an array of tunable, injection-locking oscillators which are scalable to higher frequencies and measure the entire relevant frequency space simultaneously. The scalable, highly-parallelized, adaptive receiver architecture uses arrays of tunable, injection-locking nonlinear oscillator rings for broad spectrum RF analysis. Three separate and different microelectronic circuit configurations, each having a different type of readout, are described. The embodiments are designed to be incorporated as a subsystem in any type of powered system in which a fast image of the broader spectrum is valuable, when no information about the location of signals in the frequency space is predictable or forthcoming.

Abstract: A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal.

Abstract: A first oscillating signal may be generated via a first direct digital frequency synthesizer of a communication device. One or more second oscillating signals may be generated via one or more second direct digital frequency synthesizers of the communication device. Signals received via a plurality of antennas may be processed utilizing the first oscillating signal. Signals to be transmitted via the plurality of antennas may be processed utilizing the first oscillating signal and the one or more second oscillating signals. The communication device may comprise a plurality of receive channels, a plurality of transmit channels, and a multiplexer. The first oscillating signal may be coupled, via the multiplexer, to the plurality of receive paths and one of the transmit paths. During time intervals in which the communication device is configured to receive signals via the plurality of antennas, the multiplexer may route the first oscillating signal to the first one or more direct digital frequency synthesizers.

Abstract: An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: A device can be coupled to an electrical load for supplying electrical power to the electrical load. The device contains an oscillator unit and an auxiliary oscillator unit. The oscillator unit is configured to generate an output signal of the device which can be supplied to the electrical load and which has a first frequency. The auxiliary oscillator unit is electrically coupled to the oscillator unit. The auxiliary oscillator unit is configured to excite the oscillator unit to oscillate at a second frequency greater than the first frequency. The auxiliary oscillator unit contains a timing element which is configured and arranged to terminate the excitation of the oscillator unit after the expiration of a pre-specified period of time after the start of the oscillator unit and the auxiliary oscillator unit.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements.

Abstract: In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Abstract: Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of: timing information; frequency information; phase information; and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of: timing information; frequency information; phase information and combinations thereof, wherein the second signal is used for disciplining the LO. The LO error corrector is configured to: if the second signal is unavailable to discipline the LO, discipline the LO using a source that is less accurate than the second signal. Upon the second signal becoming at least temporarily available, the LO corrector determines an offset error of the LO relative to the second signal.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.

Abstract: The device resonant comprises a plurality of synchronized oscillators. Each oscillator comprises a resonator which comprises detection means providing detection signals representative of oscillation of the resonator to a feedback loop connected to an excitation input of the resonator. The detection signals control the conductivity of the feedback loop of the oscillator. The excitation inputs of all the resonators are connected to a common point which constitutes the output of the resonant device. A capacitive load is connected between said common point and a reference voltage.

Abstract: In order to decrease the temperature sensitivity of an oscillator output, and obtain a frequency of oscillation that remains stable over variations in temperature, two oscillators may be configured with identical comparators and logic circuitry, but having different oscillation frequencies. The different oscillation frequencies may be achieved by configuring each oscillator with a respective resistor divider circuit configured to adjust the reference voltage at the reference input of the respective comparator. The difference between the respective periods of oscillation of the two oscillators may therefore become independent of the comparator delay, and may only depend on temperature sensitivity of the resistor.

Abstract: In the field of direct mind-machine interactions, prior art devices and methods do not provide sufficiently fast and reliable results. Mental influence detectors (100, 140, 400, 430) and corresponding methods provide fast and reliable results useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector (100) includes a source (104) of non-deterministic random numbers (110), a converter (114) to convert a property of numbers, a processor to accept converter output (118) and to produce an output signal (124) representative of an influence of mind. The processor output signal (124) contains fewer numbers than the input (110).