Abstract: One embodiment in accordance with the invention is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Abstract: An ILO circuit has a plurality of oscillator stages which are coupled to one another by means of a “tank lock” coupling. The coupling leads to an improved synchronization of the individual oscillator stages and thus to a reduced phase noise. Any desired LC oscillator topology can be used, not just the topology with PMOS and NMOS transistors. It is also possible to use SOI transistors, that is to say transistors formed on an SOI substrate. The bulk terminals of the transistors may be coupled not only to a supply voltage but, for example, also to a center potential, a reference voltage source, to ground, in floating fashion and/or to the source terminal.

Abstract: A local oscillator without a frequency divider is provided. The local oscillator includes a quadrature voltage controlled oscillator generating I and Q signals having a frequency which is one-third of a local oscillation frequency, and a differential second-harmonic signal having a frequency which is two-thirds of the local oscillation frequency, a poly-phase filter converting the differential second-harmonic signal input from the quadrature voltage controlled oscillator into I and Q signals, and a single side band (SSB) mixer receiving the I and Q signals having the frequency which is one-third of the local oscillation frequency from the quadrature voltage controlled oscillator as an input and receiving the I and Q signals having the frequency which is two-thirds of the local oscillation frequency from the poly-phase filter as an input, and outputting the I and Q signals having the local oscillation frequency.

Abstract: An ensemble clock comprises: an input for receiving a reference signal; multiple free-running oscillators each configured to generate a corresponding free-running frequency; an output oscillator configured to generate a controlled frequency having a frequency responsive to a control signal; a differencer unit configured to derive difference measurements indicative of time and frequency-based errors associated with each of (i) the controlled frequency, and (ii) the free-running frequency, relative to the reference signal; and a controller configured to generate the control signal responsive to the difference measurements.

Abstract: An oscillator circuit is disclosed that includes a first oscillation part configured to output a first oscillation output by charging and discharging a first capacitor, and a second oscillation part configured to output a second oscillation output by charging and discharging a second capacitor. The second oscillation part includes a phase difference detection part configured to detect the phase difference between the first oscillation output and the second oscillation output, and a charging current and discharge current control part configured to control the charging current and the discharge current of the second capacitor in accordance with the phase difference detected by the phase difference detection part so that the second oscillation output synchronizes with the first oscillation output.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.

Abstract: A ring oscillator setting apparatus and method depending on an environmental change of an image formation apparatus is provided. The apparatus includes a plurality of ring oscillators for generating different oscillation frequencies. The apparatus further includes a loopspeed detection unit to detect a loopspeed representing the number of pulses generated at the oscillation frequency by one of the ring oscillators selected from the plurality of ring oscillators for a predetermined unit time. Moreover, a state sensing unit is provided to detect a state of system environment of the image formation apparatus. A setting control unit is also provided to select and set one of the ring oscillators selected corresponding to change of the loopspeed detected from the loopspeed detection unit among the plurality of ring oscillators in response to the detected state of the state sensing unit.

Abstract: A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.

Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Abstract: A frequency generator is provided. The generator comprises two voltage controlled oscillators generating a first signal of a given multiple of a predetermined raster frequency, and a second signal of another given multiple of a predetermined raster frequency, dividers dividing the output signal of the oscillator until the frequency of both divided output signals is equal to the raster frequency, a filter arrangement connected to the output of the dividers, and a single sideband mixer. The mixer produces as output a signal having a frequency which is equal to the frequency of the output signal of either one of the oscillators or to the frequency of the output signal of either one of the oscillators from which the output signal of the filter arrangement has been subtracted or to which the output signal of the filter arrangement has been added.

Abstract: An arrangement (100) and method for a high precision and low distortion digital delay line with infinite delay. The digital delay line has an oscillating ring (110) with an odd number of inverting elements that triggers a counter (120). A comparator (130) compares the counter and the MSB of a given delay word. A line of inverters (150–159), double the odd number in the ring oscillator, is connected to a MUX (160) controlled by the LSB of the delay word. This provides the advantages of: high resolution due to use of a small, basic component, self-delay ring oscillator; small silicon area due to use of a special decoding scheme use the rings number to produce large delays; and easy implementation as a digital block in an integrated circuit using a standard cells library to build the ring and the decoder.

Abstract: A system, apparatus, and method to connect an oscillator network to multiple parallel oscillator circuits. The apparatus may include multiple modules located within a platform, where each of the multiple modules includes an internal oscillator circuit and the platform includes an input port; and an oscillator network located external to the platform. The oscillator network is coupled to each of said internal oscillator circuits through the input port. Other embodiments are described and claimed.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: A voltage controlled oscillator apparatus includes at least two voltage controlled oscillators, each of the voltage controlled oscillators being formed on a semiconductor substrate and having an LC-resonant circuit including a three-terminal inductor or a two-terminal inductor, and a continuously variable capacitor, and an amplifier including n-channel transistors or n-channel transistors and p-channel transistors. Two of the three-terminal or two-terminal inductors constructing the first and second voltage controlled oscillators have a coil shape formed with a wiring layer of an integrated circuit formed on the semiconductor substrate, and one of the three-terminal or two-terminal inductors has such a shape that its inductance value differs from that of the other of the three-terminal or two-terminal inductors, and is disposed in a region inside of the other of the three-terminal or two-terminal inductors with respect to its planar shape.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.

Abstract: A communication semiconductor integrated circuit device includes an RFVCO and a TXVCO and is formed over one semiconductor substrate, and has a first operation mode (idle mode) which does not perform transmission and reception, a second operation mode (warmup mode) which performs a preparation prior to the start of transmission or reception, and a third operation mode (transmission or reception mode) which performs transmission or reception. In the first operation mode, two oscillators are deactivated, and the operation of selecting a frequency band to be used in at least the TXVCO which generates a transmit signal, is performed in the second operation mode.

Abstract: The frequency of a first voltage controlled oscillator is stabilized in a first PLL circuit part into which a reference frequency signal is inputted. In addition, a second PLL circuit part is formed by inputting a control voltage which is the same as the frequency control voltage of the first voltage controlled oscillator into a second voltage controlled oscillator having the same configuration as the first voltage controlled oscillator. The first PLL circuit part is provided with first and second variable frequency dividers which respectively divide the reference frequency signal and the output of the first voltage controlled oscillator. In response to an input signal into the second PLL circuit part, the free-running frequencies of the second and first voltage controlled oscillators are switched, and at the same time, the division ratio of first and second variable frequency dividers are switched.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: A voltage-controlled oscillator has a voltage-controlled oscillation circuit that oscillates at a frequency according to a control voltage and a limiter circuit that limits the output of the voltage-controlled oscillator to a predetermined level. This configuration makes it possible to maintain a constant output level irrespective of the oscillation frequency.

Abstract: A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: The invention relates to a new family of differential oscillators based on oscillator amplifiers with local feedback forming respective local feedback systems, and at least one common link interconnecting the local feedback systems. Each branch of the differential oscillator includes an oscillator amplifier with a phase shifting and impedance transforming local feedback path from the output to the input of the amplifier to form a local feedback system. The differential oscillator also includes one or more common phase shifting links for interconnecting and cooperating with the local feedback systems to enable self-sustained differential oscillation. In differential mode operation, the electrical midpoint of the common phase shifting link(s) is virtually grounded and the local feedback systems of the two branches operate, together with the common phase shifting link(s), effectively in anti-phase with respect to each other as two separate oscillators.

Abstract: A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.

Abstract: In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Abstract: An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Abstract: A low power balanced Colpitts oscillator circuit with improved negative resistance. The oscillator circuit comprises two cross-coupled Colpitts oscillators with a crystal oscillator connected between the two oscillators. A single current source can be used for both Colpitts oscillators since only one Colpitts needs a current source at a time. Using a single current source cuts the power consumption in half. Alternatively, a transistor in each Colpitts oscillator can act as a current source, which is turned on or off depending on the state of the Colpitts transistor. The two current sources are biased at a common level and matched to ensure the circuit remains symmetrical. An additional benefit of the present invention is that the negative resistance is directly improved.

Abstract: By using a CR oscillating circuit and a PLL oscillating circuit selectively, these two oscillating circuits are used as a high frequency, low power consumption, short waiting time for stable oscillation, and low operating voltage oscillating circuit.

Abstract: An oscillator having a desired output frequency, comprising a cavity resonator 102 loaded with an anisotropic dielectric material and an oscillator circuit 100 including the cavity resonator 102 as a frequency determining element, the oscillator circuit 100 arranged to operate the cavity resonator 102 at a first frequency in a first mode and at a second frequency in a second mode, the first mode and the second mode each being influenced to a different extent by the thermal coefficient of permittivity of at least one crystal axis of the dielectric material, the oscillator circuit arranged to produce the desired operating frequency from the first frequency and the second frequency. The first frequency and the second frequency differ by an amount corresponding to the desired output frequency.

Abstract: A frequency-selective high-frequency oscillator includes a first switching circuit that controls the operation of a first amplifying circuit, and a second switching circuit that controls the operation of the first switching circuit and a second amplifying circuit. Switching control signals are input to the second switching circuit. When the switching control signal is “Low”, the second switching circuit turns ON and the second amplifying circuit only operates, thereby outputting a high frequency signal with a resonant frequency according to a second resonant circuit. On the other hand, when the switching control signal is “High”, the second switching circuit turns OFF and the first switching circuit turns ON, which causes the first amplifying circuit only to operate. Thus, a high frequency signal with a resonant frequency acceding to a first resonant circuit is output.

Abstract: A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

Abstract: A voltage-controlled oscillator has a voltage-controlled oscillation circuit that oscillates at a frequency according to a control voltage and a limiter circuit that limits the output of the voltage-controlled oscillator to a predetermined level. This configuration makes it possible to maintain a constant output level irrespective of the oscillation frequency.

Abstract: In a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the control voltage, and a frequency divider formed by a fixed frequency divider and a programmable frequency divider, a selecting circuit selects and activates only one of the voltage controlled oscillators, and counts a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, the one of the voltage controlled oscillators being selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value.

Abstract: A method and system for fast wakeup of a high-Q oscillator (300) that includes a resonating element (304), preferably a crystal resonator (304), and an amplifier (310). The method comprises connecting the resonating element (304) to a fast wakeup, low-Q oscillator (302), inputting a plurality of pulses generated by the low-Q oscillator (302) into the resonating element (304), and simultaneously disconnecting the resonating element (304) from the low-Q oscillator (302) while connecting the resonating element (304) to the amplifier (310), thereby obtaining substantially uniform steady state oscillations in the high-Q oscillator. The system (300) includes in addition to high-Q and low-Q oscillator elements a mechanism for counting the pulses (312) and for performing the simultaneous disconnection and connection mentioned above.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages that are configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same and the plurality of oscillators are inductively coupled. The synchronous oscillation is substantially caused by magnetic coupling. The oscillator stages may be electrically coupled during a first time period and the electrical coupling and disconnected or reduced during a second time period.

Abstract: A cluster of processing systems is provided wherein each processing system is set to operate at a unique operating frequency. Each unique frequency is set to differ from each other by at least a predetermined frequency differential or bandwidth. When clustered, the radiated emissions will not add. Rather, the RF energy is distributed over the predetermined frequency bandwidth and in so doing achieve a reduction of measured RF energy at any singular frequency. By using RF energy dispersal in systems consisting of aggregated processing elements as subsystems, the need for special or additional RF shielding is precluded. Current design and manufacturing techniques can continue to be used. Thus, reducing the overall cost of implementing aggregated systems.

Abstract: Provided is a quadrature voltage controlled oscillator capable of varying a phase difference between an in-phase output signal and a quadrature output signal. The quadrature voltage controlled oscillator comprises a first voltage controlled oscillator, a second voltage controlled oscillator, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The first voltage controlled oscillator generates a first output and a second output. The second voltage controlled oscillator generates a third output and a fourth output. The first output is a positive in-phase signal, and the second output is a negative in-phase signal. The third output is a positive quadrature signal, and the fourth output is a negative quadrature signal. The first amplifier is controlled by a first current and drives the first output and the second output in response to the third output and the fourth output.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

Abstract: A circuit and method for generating quadrature signals with a deterministic phase relationship. Between two inductive-capacitive (LC) based quadrature voltage controlled oscillators (VCO), phase shift circuitry is interposed such that the individual LC VCO circuits produce signals with corresponding phase delays which ensure that the desired lead or lag phase relationship between the quadrature signals is achieved.

Abstract: A redundant clock module provides a highly reliable fixed clock reference output. This clock reference output is based on at least two internal reference oscillators that are monitored and eliminated from use if they are not operating or within tolerance requirements. The redundant clock module comprises at least two oscillators, detection circuitry, switching circuitry and control circuitry. If a primary oscillator fails or is out of tolerance, the redundant clock module will detect the failure or out of tolerance condition and switch to a secondary working and in tolerance oscillator to take over primary timing functions of an end user application. The redundant clock module provides a slow and seamless transition between oscillator switching to assure no significant phase shift or runt pulses will affect the end user application.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: In an ensemble oscillator system including multiple free-running oscillators, a voltage controlled oscillator having a frequency responsive to a control signal, and a differencer unit that measures time differences between the oscillators, an adaptive Kalman Filter Processor (AKFP) generates the control signal responsive to the time differences. The AKFP uses oscillator noise models to model noise/errors of the ensemble system oscillators, including random noise parameters, and adaptively estimates the errors and the random noise parameters to derive the control signal.

Abstract: A method and apparatus for producing high-frequency oscillations is disclosed. A new resonator architecture minimizes via losses and supports a compact layout of active circuitry. The resonator architecture incorporates dual resonant transmission lines to reduce resonator loss and facilitate compact layout. The oscillations of two oscillators are cross-coupled in a way that compensates for the delay in the active devices of the oscillator, thus permitting accurate alignment of the active circuitry response with the oscillation waveform. The cross-coupling of the two oscillators improves phase noise performance and eliminates spurious oscillations. An active circuit architecture provides very narrow pulses for the operation of the oscillator. This architecture provides for accurate cross-coupling and pulsed-mode operation to improve manufacturing stability and phase noise performance.

Abstract: Embodiments of the invention provide techniques for calibrating voltage-controlled oscillators (VCOs). Multiple VCOs may be disposed on a chip with the VCOs having different frequency ranges. The VCOs may be selected and tested to determine a desired VCO to use to tune to a selected channel frequency. Each of the VCOs has multiple possible varactor configurations. The varactor configurations of the desired VCO determined to be used to tune to the selected channel frequency can be selected and tested to determine a desired varactor configuration for the desired VCO. The desired VCO with the desired varactor configuration will preferably be able to produce a full range of desired frequencies corresponding to all channel frequencies desired.

Abstract: A single integrated chip has first and second voltage controlled oscillators and first and second buffers. The first voltage controlled oscillator has a first output defined by a first frequency band, and the second voltage controlled oscillator has a second output defined by a second frequency band. The first and second buffers selectively couple the first and second outputs to a common output. The first buffer is coupled between the first frequency controlled oscillator and the common output, and the second buffer is coupled between the second frequency controlled oscillator and the common output. The first buffer has a high output impedance when the second buffer couples the second output to the common output, and the second buffer has a high output impedance when the first buffer couples the first output to the common output.

Abstract: Transmitter frequency locking across a full duplex communications link. An offset in one transmitter results in an offset at the corresponding receiver. That receiver offset shifts its transmitter in a corresponding manner, causing a correcting offset in the first receiver, which is used to correct the first transmitter. A first embodiment uses filtered received frequency information derived from a baseband demodulator to correct transmitter frequency. A second embodiment uses filtered frequency information from a frequency detector to correct transmitter frequency.

Abstract: The oscillation circuit includes at least two ring oscillation circuits in each of which a plurality of inverters are connected in a ring shape in a multi-stage fashion, and a conductive wiring line. The output of at least one inverter of each of the ring oscillation circuits is connected to the conductive wiring line, whereby the plurality of ring oscillators are caused to oscillate at an identical frequency. A PLL is constructed in such a way that the oscillation circuit obtained by the above means is formed into a voltage-controlled oscillation circuit, and that a phase-frequency comparator, a charge pump circuit and a low-pass filter are employed.

Abstract: A voltage controlled oscillator including a first oscillator circuit portion with at least one first inductor, and a second oscillator circuit portion with at least one second inductor, wherein the at least one first inductor and the at least one second inductor are electromagnetically coupled to each other.

Abstract: A method of locking a first differential oscillator with a second differential oscillator and a circuit and an arrangement therefor. The method comprises AC coupling a fundamental frequency AC-ground of the first differential oscillator with a fundamental frequency AC-ground of the second differential oscillator.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.