Current And/or Voltage (e.g., Ballast Resistor) Patents (Class 338/20)
  • Patent number: 11160988
    Abstract: Discrete cofired feedthrough filters are provided for medical implanted device applications. A plurality of discrete vertical feedthrough filter elements are respectively associated with a plurality of signal wires or pins otherwise supported by an insulating feedthrough and a ferrule. The resulting discrete device comprises a single-element device which is cheaper to make, and which reduces cross-talk between adjacent signal wires/pins while otherwise accommodating changes in feedthrough pitch without having to redesign the filter.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 2, 2021
    Assignee: AVX Corporation
    Inventor: Andrew P. Ritter
  • Patent number: 11145442
    Abstract: An externally-controllable thermal tripping device comprising a voltage dependent resistor including a voltage dependent resistor chip; a thermal tripper including a tripping electrode; and a controllable heating element. The tripping electrode is connected to an electrode of the voltage dependent resistor chip through a meltable welding material, and the controllable heating element is controlled by an external control device to generate heat and transmit generated heat to a commissure of said welding material to melt said welding material and electrically disconnect the tripping electrode from the voltage dependent resistor chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: October 12, 2021
    Assignees: Shanghai ASP Lighting Protective Technology Co., Ltd., MERSEN USA EP Corp.
    Inventor: Ting Pan
  • Patent number: 11112092
    Abstract: A streetlight device includes a power source portion and a lighting portion. The power source portion includes a driving power source, a power source base provided with a receiving space for receiving the driving power source, and a power source upper cover for closing the power source base. The lighting portion is connected at one end of the power source upper cover. The power source upper cover and the power source base are connected with each other through a hinge assembly. The power source upper cover is provided with a power source mounting assembly, and the driving power source is mounted onto the power source upper cover through the power source mounting assembly.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 7, 2021
    Assignees: Opple Lighting Co., Ltd., Suzhou Opple Lighting Co., Ltd.
    Inventors: Zenglong Zhu, Hongbo Wang, Qingjun Wei, Guoping Wang
  • Patent number: 11094461
    Abstract: A composite electronic component includes a composite body that includes a multilayer ceramic capacitor and a ceramic chip coupled to each other. The multilayer ceramic capacitor includes a first ceramic body in which a plurality of dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween are stacked, and first and second external electrodes are disposed on both end portions of the first ceramic body. The ceramic chip is disposed on a lower portion of the multilayer ceramic capacitor and includes a second ceramic body and first and second terminal electrodes disposed on both end portions of the second ceramic body and connected to the first and second external electrodes, respectively. A plurality of electrodes are disposed in the second ceramic body.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soo Hwan Son, Jong Duck Kim, Dae Heon Jeong, Ho Yoon Kim
  • Patent number: 11063209
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, an oxide layer and at least one oxygen blocking layer. The free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. The nonmagnetic spacer layer is between the pinned layer and the free layer. The oxide layer is adjacent to the free layer. The free layer is between the nonmagnetic spacer layer and the oxide layer. The oxygen blocking layer(s) has a position selected from adjacent to the oxide layer and adjacent to the pinned layer. In some aspects, the magnetic junction may also include an oxygen adsorber layer and/or a tuning layer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xueti Tang, Gen Feng, Mohamad Towfik Krounbi
  • Patent number: 11037708
    Abstract: A PPTC assembly may include a PPTC component, having a trip temperature, and further comprising a first temperature coefficient of resistance, in a low temperature range below the trip temperature. The PPTC assembly may include a resistive component, disposed in electrical contact with the PPTC component on a first side of the PPTC component, the resistive component comprising an electrical conductor, and having a second temperature coefficient of resistance in the low temperature range, less than the first temperature coefficient of resistance. The PPTC component may include a first electrode, electrically coupled to the first side of the PPTC component, and a second electrode, electrically coupled to the second side of the PPTC component, where the PPTC component and the resistive component are arranged in electrical series between the first electrode and the second electrode.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Littelfuse, Inc.
    Inventors: Jianhua Chen, Chun Kwan Tsang
  • Patent number: 11009545
    Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, David M. Audette, Dennis R. Conti, Brian M. Erwin, Grant Wagner
  • Patent number: 10979083
    Abstract: Example embodiments herein relate to methods of transmitting and receiving audio signals. A method of transmitting an audio signal includes: receiving the audio signal including frames having left and right subframes containing audio data of a first number of bits; encoding the left and right subframes into a parity code of a second number of bits; generating serial data by combining the parity code and audio data; and transmitting the serial data over an audio transmission media having a bandwidth of a third number of bits, a sum of the first and second number being below the third number. A method of receiving an audio signal includes: receiving a serial signal combining a parity code; decoding the serial signal by calculating a syndrome based on the parity code; detecting an error by comparing the syndrome with the audio data; and generating a corrected audio signal by correcting the detected error.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 13, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Jiong Huang, Alexander Peysakhovich, Lei Ming
  • Patent number: 10971916
    Abstract: The invention disclosure relates to a space-limited protection module with at least two overvoltage protection elements in parallel current branches, where the protection module includes a local multistage indicator for indicating at least one operating state, a warning state and a defect state, and where the parallel switched overvoltage protection elements are arranged on a circuit board in electrical connection to conductor tracks of the circuit board and attached in a thermally softenable manner.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 6, 2021
    Assignee: PHOENIX CONTACT GMBH & CO KG
    Inventors: Gernot Finis, Christian Birkholz, Steffen Pfoertner
  • Patent number: 10923885
    Abstract: A surge protection component with a main body which has at least one inner electrode arranged between two ceramic layers, wherein the at least one inner electrode is set back from at least one lateral face of the main body, wherein a gas-filled cavity is provided between the at least one inner electrode and the at least one lateral face, and wherein an outer electrode is respectively arranged on two mutually opposite lateral faces of the main body. According to a further aspect, the present invention relates to a method for producing a surge protection component.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 16, 2021
    Assignee: EPCOS AG
    Inventor: Franz Rinner
  • Patent number: 10839994
    Abstract: A varistor includes a substrate; first and second electrodes disposed on an upper side and a lower side of the substrate, respectively; a core varistor body surrounded by the substrate and disposed between the first and second electrodes; first and second terminals having at least portions disposed on one side and the other side of the substrate, respectively, and electrically connected to the first and second electrodes, respectively; and a cover varistor body covering the core varistor body and disposed in a level higher than an upper surface of the substrate or disposed in a level lower than a lower surface of the substrate.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ic Seob Kim, Jung Il Kim, Yong Sung Kim, Hae In Kim
  • Patent number: 10777366
    Abstract: Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Zhaohui Chen, Wei C. Jin, Scott B. Clendenning, Eric C. Hannah, Tomm V. Aldridge, John L. Gustafson
  • Patent number: 10734805
    Abstract: A circuit is provided for limiting an applied voltage applied between a power line and an electrical ground. The circuit includes a transistive element connected between the power line and the electrical ground to provide a channel, where current flow through the channel is controlled by a control voltage provided to a control terminal of the transistive element. A first Correlated Electron Material (CEM) device having an impedance state is coupled between the power line and a first node, and a sensing circuit coupled between the first node and the control terminal of the transistive element. The sensing circuit is configured to detect a voltage drop across the CEM device and to provide the control voltage. The channel of the transistive element is opened when the detected voltage drop across the CEM device exceeds a threshold. The CEM device may contain a transition metal oxide (TMO), for example.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: August 4, 2020
    Assignee: ARM Limited
    Inventors: Bal S. Sandhu, Lucian Shifren, Glen Arnold Rosendale
  • Patent number: 10700167
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type and connected to the first semiconductor region, a first electrode forming a Schottky-contact with the first semiconductor layer and the first semiconductor region, and a second electrode forming an ohmic contact with the second semiconductor region. The second electrode has a Ti—Al alloy layer on a surface in contact with the first electrode. The second electrode further has therein a nickel silicide layer containing titanium.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 30, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shoji Kitamura, Tsukasa Tashima, Kazuhiro Kitahara
  • Patent number: 10679279
    Abstract: An Indoor location mapping and wayfinding system for mapping waypoints on an interactive mapping system that can function both indoors and outdoors based on user selections and location. It can include a shopping system that allows users to pre-select items for purchase, maps the items on an indoor map of the store, and provides a route to the user for the collection of the selected items.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: June 9, 2020
    Inventors: Frank Daly Ward, Steven James Faletto
  • Patent number: 10622147
    Abstract: A composite electronic component includes a composite body that includes a multilayer ceramic capacitor and a ceramic chip coupled to each other. The multilayer ceramic capacitor includes a first ceramic body in which a plurality of dielectric layers and internal electrodes disposed to face each other with respective dielectric layers interposed therebetween are stacked, and first and second external electrodes are disposed on both end portions of the first ceramic body. The ceramic chip is disposed on a lower portion of the multilayer ceramic capacitor and includes a second ceramic body and first and second terminal electrodes disposed on both end portions of the second ceramic body and connected to the first and second external electrodes, respectively. A plurality of electrodes are disposed in the second ceramic body.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soo Hwan Son, Jong Duck Kim, Dae Heon Jeong, Ho Yoon Kim
  • Patent number: 10593877
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
  • Patent number: 10559444
    Abstract: A fuse device including a fuse component, a first electrode, disposed on a first side of the fuse component, a second electrode, disposed on a second side of the fuse component, and a phase change component, disposed in thermal contact with the fuse component. The fuse component may comprise a fuse temperature, wherein the phase change component exhibits a phase change temperature, the phase change temperature marking a phase transition of the phase change component, and wherein the phase change temperature is less than the fuse temperature.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 11, 2020
    Assignee: LITTELFUSE, INC.
    Inventors: Chun-Kwan Tsang, Jianhua Chen
  • Patent number: 10490322
    Abstract: A green film composed of varistor material laminated on a ceramic main body, which is provided with metallizations on both sides, and is sintered to form a varistor layer. A terminating electrode pair completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair can serve directly as a terminal contact for mounting an electrical component.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 26, 2019
  • Patent number: 10446300
    Abstract: An anti-surge structure built in switches includes three metal-oxide varistors disposed in an insulating body in stair-like arrangement. The metal-oxide varistors further has an insulating band surrounding a middle metal-oxide varistor and defining four isolated insulating areas within the insulating body, so as to avoid high voltage flashover and to protect the structure from external impacts. With the stair-like arrangement, each metal-oxide varistor has a connecting area for both ends of a metal strap to be welded thereon by low-temperature solder paste. When the low-temperature solder paste are melted by heat, a compressed spring element thereof is ejected to displace a pushing element thereof and to further detach two connecting points of the structure, so as to break a circuit connected by the structure.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 15, 2019
    Inventors: Yi-Hsiang Wang, I-Ying Wang
  • Patent number: 10320154
    Abstract: An ESD protection device includes a multilayer substrate, first and second discharge electrodes, and a discharge auxiliary electrode. Discharge portions of the first and second discharge electrodes are opposed to each other in a lamination direction of insulating layers with the discharge auxiliary electrode interposed between both the discharge portions. A cavity is provided within the multilayer substrate in at least one of a region positioned adjacent to or in a vicinity of the discharge portion of the first discharge electrode on an opposite side to the discharge auxiliary electrode and a region positioned adjacent to or in a vicinity of the discharge portion of the second discharge electrode on an opposite side to the discharge auxiliary electrode.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 11, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takeshi Miki
  • Patent number: 10262803
    Abstract: A multilayer chip capacitor includes electrodes comprised of numerous, closely spaced conductive layers interposed within a dielectric laminate. Adjacent conductive layers are essentially non-overlapping, so that fringe capacitance between opposing electrodes provides substantially all of the capacitance. The conductive layers may be shaped to form a non-planer boundary between electrodes. An additional high frequency integrated capacitor is formed from external electrode plates. The non-planar electrode boundary principle is also applied to discoidal capacitors in the form of a non-concentric electrode boundary.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: April 16, 2019
    Assignee: Presidio Components, Inc.
    Inventors: Hung Van Trinh, Alan Devoe
  • Patent number: 10211853
    Abstract: Example embodiments disclosed herein relate to a method of transmitting an audio signal and also a method of receiving an audio signal. The method of transmitting the audio signal includes: receiving the audio signal including a plurality of frames having a left and right subframes containing audio data of a first number of bits; encoding the left and right subframes into a parity code of a second number of bits; generating serial data by combining the parity code and the audio data; and transmitting the serial data over an audio transmission media having a bandwidth of a third number of bits, a sum of the first number of bits and the second number of bits being below the third number of bits. The method of receiving the audio signal includes: receiving a serial signal combining a parity code; decoding the serial signal by calculating a syndrome based on the parity code; detecting an error by comparing the syndrome with the audio data; and generating a corrected audio signal by correcting the detected error.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: February 19, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jiong Huang, Alexander Peysakhovich, Lei Ming
  • Patent number: 10043602
    Abstract: To provide a chip resistor in which a resistive element can be surely protected from an external environment and which is also excellent in corrosion resistance, a chip resistor 1 is configured to include an insulating substrate 2, a pair of front electrode 3 provided on opposite end portions of a front surface of the insulating substrate 2, a pair of back electrodes 7 provided on opposite end portions of a back surface of the insulating substrate 2, a resistive element 4 provided to extend onto the two front electrodes 3, a first insulating layer 5 covering the resistive element 4, a second insulating layer 6 made of a resin material to cover the first insulating layer 5, end surface electrodes 8 establishing electrical continuity between the front electrodes 3 and the back electrodes 7, plating layers 9 covering the end surface electrodes 8, etc.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: August 7, 2018
    Assignee: KOA Corporation
    Inventor: Kentaro Matsumoto
  • Patent number: 10037838
    Abstract: A thermistor element satisfies 4?(d/ed) when a first distance is d, which is a shortest distance between a first internal electrode and a second external electrode, whereas a second distance is referred to as ed, which is a shortest distance between the first internal electrode and a fifth internal electrode, in a cross section of a body including an L direction and a T direction thereof.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 31, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinichiro Nawai, Yuichi Hirata
  • Patent number: 9865399
    Abstract: An electronic component of a multi-layered structure includes a laminate formed by stacking a plurality of ceramic bodies and an external electrode made of a conductive resin for connecting each ceramic body.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: January 9, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Hun Cho, Chang Ho Lee, Won Sik Chong
  • Patent number: 9780146
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a line-type first electrode layer having at least one protrusion and extending in a first direction, and a plurality of memory elements, each memory element including a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 3, 2017
    Assignee: SK HYNIX INC.
    Inventor: Kyung-Wan Kim
  • Patent number: 9761356
    Abstract: A varistor device includes a main body, a conductive area, a specific-melting-point metallic pin, and an elastic unit. The main body has a first surface, and the conductive area is located at the first surface. The specific-melting-point metallic pin has a first section and a second section. The first section and the second section are one-piece formed. The first section is fixedly disposed on the conductive area. The second section has a specific melting point such that the second section melts when a current flows between the first surface and the second section so as to expose the second section to a temperature greater than the specific melting point. The elastic unit has an end connected to the second section, and the elastic unit provides an elastic force to the second section to break the second section so as to cut off the current when the second section melts.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: September 12, 2017
    Assignee: POWERTECH INDUSTRIAL CO., LTD.
    Inventor: Jung-Hui Hsu
  • Patent number: 9672964
    Abstract: The present invention relates to a varistor material for a surge arrester with target switching field strength ranging from 250 to 400 V/mm comprising ZnO forming a ZnO phase and Bi expressed as Bi2O3 forming an intergranular bismuth oxide phase, said varistor material further comprising a spinel phase, characterized in that the amount of a pyrochlore phase comprised in the varistor material is such, that the ratio of the pyrochlore phase to the spinel phase is less than 0.15:1.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: June 6, 2017
    Assignee: ABB SCHWEIZ AG
    Inventors: Felix Greuter, Michael Hagemeister, Oliver Beck, Ragnar Osterlund, Reto Kessler
  • Patent number: 9601234
    Abstract: A method of making a three-dimensional porous device entails providing a substrate having a conductive pattern on a surface thereof, and depositing a colloidal solution comprising a plurality of microparticles onto the surface, where the microparticles assemble into a lattice structure. Interstices of the lattice structure are infiltrated with a conductive material, which propagates through the interstices in a direction away from the substrate to reach a predetermined thickness. The conductive material spans an area of the surface overlaid by the conductive pattern. The microparticles are removed to form voids in the conductive material, thereby forming a conductive porous structure having the predetermined thickness and a lateral size and shape defined by the conductive pattern.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: March 21, 2017
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: William P. King, Paul V. Braun, Zhenting Dai, Xindi Yu, Hui Gang Zhang
  • Patent number: 9420705
    Abstract: A current conducting element including a substrate, a through hole, an electrode layer and a conductor structure is provided. The through hole is disposed through the substrate and has a first opening. The electrode layer is disposed on the substrate. A portion of the first opening is exposed from the electrode layer. The conductor structure is disposed in the through hole and contacted with the electrode layer. The electrode layer and the conductor structure form a current conducting path.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 16, 2016
    Assignee: CYNTEC CO., LTD.
    Inventors: Yi-Geng Li, Chung-Hsiung Wang, Hung-Ming Lin
  • Patent number: 9391274
    Abstract: The present invention provides a nonvolatile memory element, in a nonvolatile memory element having a variable resistance layer possessing a stacked structure, in which the variable resistance layer has a high resistance change ratio, and a method of manufacturing the same. The nonvolatile memory element according to one embodiment of the present invention includes a first electrode, a second electrode, and a variable resistance layer which is interposed between the first electrode and second electrode and in which the resistance value changes into at least two different resistance states. The variable resistance layer possesses a stacked structure having a first metal oxide layer containing Hf and O, and a second metal oxide layer that is provided between the first metal oxide layer and at least one of the first electrode and the second electrode and contains Al and O.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 12, 2016
    Assignee: CANON ANELVA CORPORATION
    Inventors: Eun-mi Kim, Yuichi Otani, Takashi Nakagawa
  • Patent number: 9320135
    Abstract: Printed circuit boards including voltage switchable dielectric materials (VSDM) are disclosed. The VSDMs are used to protect electronic components, arranged on or embedded in printed circuit boards, against electric discharges, such as electrostatic discharges or electric overstresses. During an overvoltage event, a VSDM layer shunts excess currents to ground, thereby preventing electronic components from destruction or damage.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 19, 2016
    Assignee: LITTELFUSE, INC.
    Inventors: Lex Kosowsky, Robert Fleming, Bhret Graydon, Daniel Vasquez
  • Patent number: 9299474
    Abstract: There is provided an oxide for semiconductor layers of thin-film transistors, which oxide can provide thin-film transistors with excellent switching characteristics and by which oxide favorable characteristics can stably be obtained even after the formation of passivation layers. The oxide to be used for semiconductor layers of thin-film transistors according to the present invention includes Zn, Sn, and Si.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 29, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Shinya Morita, Aya Miki, Yumi Iwanari, Toshihiro Kugimiya, Satoshi Yasuno, Jae Woo Park, Je Hun Lee, Byung Du Ahn
  • Patent number: 9293242
    Abstract: Provided is a voltage detection circuit, which can remove influence of error voltage caused by tiny amount of self-inductance existing in a shunt resistor, though in the resistor for large current usage, which is impossible to surface-mount on a voltage detection circuit board. The shunt resistor device comprises: a resistance body (11); a pair of main electrode (12) for flowing current to be monitored through the resistance body; a pair of detection terminal (13a) for detecting voltage caused in the resistance body; and a pair of wiring (23) each electrically connected to the detection terminal. And, a pair of voltage detection wiring consisting of the detection terminal (13a) and the wiring (23) is brought closer, at prescribed location, than distance between each of connection position of the pair of the detection terminal (13a) on the main electrode (12).
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 22, 2016
    Assignee: KOA CORPORATION
    Inventors: Tadahiko Yoshioka, Koichi Hirasawa, Yoshinori Aruga
  • Patent number: 9269896
    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: February 23, 2016
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Vidyut Gopal, Chien-Lan Hsueh
  • Patent number: 9246322
    Abstract: Aspects of the innovations herein relate to surge protection devices. Such surge protection devices may have an arrester. The arrester may produce an equalization between different potentials and arrest a surge current during use. A sensor may be provided on the arrester, said sensor generating an electric switch-off signal. A switching device may receive the switch-off signal and separate the arrester from an electric circuit, the switching device and arrester being arranged in a physically separate manner from each other.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: January 26, 2016
    Assignee: PHOENIX CONTACT GMBH & CO. KG
    Inventors: Joachim Schimanski, Martin Wetter, Gerhard Wolff
  • Patent number: 9147510
    Abstract: An overvoltage protection element is disclosed that includes a housing, connections for electrically connecting the overvoltage protection element to a current path or a signal path to be protected The overvoltage protection element further includes two varistors arranged inside the housing and electrically connected in parallel, and a center electrode arranged at least partially between the varistors. The housing has two housing halves made of metal and electrically connected to each other, wherein the center electrode is isolated from the housing halves and is electrically connected at the opposite sides of the electrode to a first connection area of a varistor and wherein the two varistors and the center electrode are sandwiched between the two housing halves. The overvoltage protection element includes an arrester between one terminal of the overvoltage protection element and the parallel connection of the two varistors.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: September 29, 2015
    Assignee: Phoenix Contact GmbH & Co. KG
    Inventors: Christian Depping, Christina Stohlmeyer, Joachim Wosgien, Philip Jungermann
  • Patent number: 9138381
    Abstract: Process for producing composite materials by reactive spray-drying, where a liquid phase A, which comprises inorganic cations, and a liquid phase B, which comprises anions which, with the inorganic cations, form a salt that is insoluble in the mixture of the liquid phases are sprayed together using at least one multi-substance nozzle, and where at least one hydrophobic active ingredient is present in dissolved form in at least one liquid spraying phase, and where the salt formed from the cations of phase A and the anions of phase B has a solubility of less than 0.02 mol/l in the neutral aqueous medium.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: September 22, 2015
    Assignee: BASF SE
    Inventors: Andreas Kempter, Max Siebert, Heidrun Debus
  • Patent number: 9099230
    Abstract: An amorphous metal thin-film non-linear resistor (AMNR) is provided. The AMNR is an electronic device possessing symmetric non-linear current-voltage (I-V) characteristics, an exemplary configuration of which may comprise three sequentially deposited layers which include a lower amorphous metal thin-film (AMTF) interconnect, a thin-film insulator located on top of the AMTF interconnect, and two upper conductive contacts located on top of the insulator and disposed in the same physical plane.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: August 4, 2015
    Assignee: STATE OF OREGON ACTING BY AND THROUGH THE STATE BOARD OF HIGHER EDUCATION ON BEHALF OF OREGON STATE UNIVESITY
    Inventor: E. William Cowell, III
  • Patent number: 9087623
    Abstract: A voltage nonlinear resistor ceramic composition comprises zinc oxide, with respect to 100 mol of said zinc oxide, 0.30 to 10 mol of Co oxide in terms of Co, 0.10 to 10 mol of R oxide (note that R is at least one selected from a group consisting of Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu) in terms of R, 0.10 to 5 mol of Cr oxide in terms of Cr, 0.10 to 5 mol of oxide of at least one selected from Ca and Sr respectively in terms of Ca or Sr, 0.0005 to 5 mol of oxide of at least one selected from Al, Ga and In respectively in terms of Al, Ga or In, and 0.10 to 5 mol of barium titanate in terms of BaTiO3.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: July 21, 2015
    Assignee: TDK CORPORATION
    Inventors: Takahiro Itami, Naoyoshi Yoshida, Kaname Ueda
  • Patent number: 9077174
    Abstract: The ESD protection device includes: opposed electrodes 2 including an opposed electrode 2a on one side and an opposed electrode 2b on the other side, and a discharge auxiliary electrode 3, the discharge auxiliary electrode being placed so as to extend from the opposed electrode on one side to the opposed electrode on the other side, wherein the discharge auxiliary electrode contains metal grains, semiconductor grains and a glass material, the metal grains, the semiconductor grains, and the metal grain and the semiconductor grain are bound together, respectively, via the glass material, the average grain size X of the metal grains is 1.0 ?m or more, and the relationship between the thickness Y of the discharge auxiliary electrode and the average grain size X of the metal grains satisfies the requirement of 0.5?Y/X?3.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 7, 2015
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kumiko Hiehata, Takahiro Sumi, Jun Adachi, Jun Urakawa, Takayuki Tsukizawa
  • Publication number: 20150145638
    Abstract: Provided are a multilayer chip ZnO varistor with base metal inner electrodes and a preparation method thereof. The varistor is formed by ceramic sheets and inner electrodes which were alternately laminated. Wherein the main material of inner electrodes is the base metal nickel(Ni), both ends of the varistor are coated with silver electrodes.
    Type: Application
    Filed: June 30, 2014
    Publication date: May 28, 2015
    Inventors: Qiuyun Fu, Dongxiang Zhou, Yunxiang Hu, Zhiping Zheng, Wei Luo, Tao Chen
  • Publication number: 20150145538
    Abstract: A circuit is provided, including a first resistor, a second resistor and a control unit. The second resistor may have an adjustable resistance. The control unit may be configured to adjust the second resistor to have a first resistance at which a voltage due to a first current flowing through the first resistor is equal to a voltage due to a second current flowing through the second resistor. The control unit may be further configured to adjust the second resistor to have a second resistance at which a voltage due to another first current different from the first current and flowing through the first resistor is equal to the voltage due to the second current flowing through the second resistor. The control unit may be still further configured to adjust the second resistor to have a third resistance based on at least a difference of the first resistance and the second resistance.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Infineon Technologies AG
    Inventor: Steffen Thiele
  • Publication number: 20150123516
    Abstract: A method for producing a multilayer component (21) is specified, which involves providing a body having dielectric layers (3) arranged one above another and first and second electrically conductive layers (4, 84, 5, 85) arranged therebetween. The first conductive layers (4, 84) are connected to a first auxiliary electrode (6) and the second conductive layers (5, 85) are connected to a second auxiliary electrode (7). The body (1, 81) is introduced into a medium and a voltage is applied between the first and second auxiliary electrodes (6, 7) for producing a material removal. Furthermore, a multilayer component is specified, which has depressions (20) formed by an electrochemically controlled material removal.
    Type: Application
    Filed: June 6, 2013
    Publication date: May 7, 2015
    Inventors: Franz Rinner, Dieter Somitsch, Christoph Auer, Gerhard Fuchs
  • Publication number: 20150109093
    Abstract: With miniaturization of a variable resistance element, it is becoming difficult to suppress the adverse effect CMP or etching might have on the resistance variable element. There is proposed a variable resistance element comprising an insulation film and a lower electrode equipped with a first portion surrounded by the insulation film and a columnar-shaped second portion protruded upwards from the first portion beyond an upper surface of the insulation film. The variable resistance element also comprises a variable resistance film that covers a preset region of the insulation film, the present region including the lower electrode, and that is electrically connected to at least an upper surface of the second portion of the lower electrode. The variable resistance element further comprises an upper electrode that covers the variable resistance film and that is electrically connected to the variable resistance film.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 23, 2015
    Inventors: Naoya HIGANO, Yukio TAMAI, Suguru KAWABATA
  • Patent number: 8940193
    Abstract: One or more embodiments provide for a device that utilizes voltage switchable dielectric material having semi-conductive or conductive materials that have a relatively high aspect ratio for purpose of enhancing mechanical and electrical characteristics of the VSD material on the device.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: January 27, 2015
    Assignee: Littelfuse, Inc.
    Inventors: Lex Kosowsky, Robert Fleming
  • Publication number: 20140375417
    Abstract: A tunable resistance system includes a layer of a first functional material deposited on a component of the system. The first functional material undergoes a phase transition at a first critical voltage. An insulating layer is deposited upon the layer of first functional material. A layer of a second functional material deposited on the insulating layer. The second functional material undergoes a phase transition at a second critical voltage. The insulating layer is configured to induce a stress on the layer so as to change the first critical voltage. In this way, the resistance of the system is tunable, allowing the system to undergo multi-stage electrical switching of resistive states.
    Type: Application
    Filed: February 6, 2013
    Publication date: December 25, 2014
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: You Zhou, Zheng Yang, Shriram Ramanathan
  • Publication number: 20140375416
    Abstract: A detection signal receiving unit receives, via signal lines, a detection signal output from a position detector which is used in a motor control device. The resistance value of a termination resistor unit is changed to a resistance value determined depending on the type of the position detector in accordance with the received detection signal and the reference value determined depending on the type of the position detector.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 25, 2014
    Inventor: Kunio TSUCHIDA
  • Publication number: 20140361864
    Abstract: To provide a resistance change device that can be protected from an excess current without enlarging a device size. A resistance change device 1 according to the present embodiment includes a lower electrode layer 3, an upper electrode layer 6, a first metal oxide layer 51, a second metal oxide layer 52, and a current limiting layer 4. The first metal oxide layer 51 is disposed between the lower electrode layer 3 and the upper electrode layer 6, and has a first resistivity. The second metal oxide layer 52 is disposed between the first metal oxide layer 51 and the upper electrode layer 6, and has a second resistivity higher than the first resistivity. The current limiting layer 4 is disposed between the lower electrode layer 3 and the first metal oxide layer 51, and has a third resistivity higher than the first resistivity and lower than the second resistivity.
    Type: Application
    Filed: August 27, 2013
    Publication date: December 11, 2014
    Inventors: Natsuki Fukuda, Kazunori Fukuju, Yutaka Nishioka, Koukou Suu