Abstract: A light emission driver for a display device is disclosed. In one aspect, the driver includes a first node to which first and second light emitting power source voltages are applied according to respective clock signals. The driver also includes a second node to which the first and third light emitting power source voltages are applied according to the respective clock signals. The driver further includes first and second transistors respectively turned on by the first and second nodes and respectively transmitting the second and first light emitting power source voltages to a light emitting signal output terminal, respectively.

Abstract: There is provided a display device capable of displaying an image that barely changes with low power consumption on the basis of video data included in a transmitted command, and there is also provided a method for driving the same. A display timing controller (31) determines every frame period whether or not an externally transmitted command includes updated video data. As a result, when it is determined that no updated video data is included, screen refreshing is paused by not reading video data stored in frame memory (36). Moreover, when it is determined that updated video data is included, the screen refreshing is performed by reading video data stored in the frame memory (36).

Abstract: The present invention provides an active matrix image display apparatus including an organic EL element capable of efficiently arranging a wiring pattern on an insulating substrate compared to the related art. The present invention provides a dummy region arranged at the outermost periphery of a display unit as a scanning line coupling region or a pitch conversion region. A power supply scanning line is commonly used by a pixel circuit of an odd-numbered line and a pixel circuit of a following even-numbered line.

Abstract: There is provided an SSD display device with reduced power consumption. A selection circuit (400) consists of k selection blocks (410(1) to 410(k)). Each selection block consists of three thin-film transistors. The three thin-film transistors respectively have three phases of selection control signal (CT) provided to their gate terminals. A scanning period (T1) is provided and followed by an idle period (T2). In the idle period (T2), the three thin-film transistors in each selection block are brought into ON state in accordance with selection control signals (CT) at an idle period frequency (fck2). The idle period frequency (fck2) is lower than a scanning period frequency (fck1).

Abstract: An organic light emitting display device includes a scan driving unit supplying a first scan signal and a second scan signal to each of a plurality of scan lines; a data driving unit supplying data signals to each of a plurality of data lines to be synchronized with the second scan signal; pixels positioned at intersections of the scan lines with the data lines, receiving bias power when the first scan signal is supplied, and receiving the data signals when the second scan signal is supplied.

Abstract: A display controller is capable of changing a refresh rate, indicative of how often a screen displayed on a display device having a plurality of pixels is switched, between a low refresh rate of 40 Hz and a normal refresh rate of 60 Hz and generates (i) a dot clock (reference clock) serving as a timing signal indicative of a timing of operation in the display device, (ii) video data indicative of an image to be displayed on the screen, (iii) Hsync for defining a horizontal period of a display on the screen, and (vi) Vsync for defining a vertical period of the display on the screen, so as to supply the dot clock, the video data, Hsync, and Vsync to the display device, wherein the display controller includes a dot clock generation circuit for generating the reference clock whose frequency is constant without depending on a change of the refresh rate.

Abstract: The invention discloses a driving apparatus for driving an LCD. The driving apparatus comprises a voltage control unit, an operating unit, a resistance unit, and a voltage selection unit. The operating unit comprises two sets of buffers formed by a plurality of operational amplifiers in negative feedback circuit. The two sets of buffers selectively receive positive polarity voltages and negative polarity voltages respectively. The voltage selection unit is provided with the positive polarity voltages and negative polarity voltages through the operating unit and the resistance unit. The voltage selection unit selectively provides the pixels of the LCD with the positive polarity voltage and the negative polarity voltage. Accordingly, each of the pixels is provided either with the positive polarity voltages or the negative polarity voltages by one of the two sets of buffers.

Abstract: A display device of an embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data has a first flag for specifying a polarity of voltage of a common electrode added thereto. The display driver generates, in accordance with a timing of a serial clock, a timing signal for a horizontal period for a data signal line driver, and a timing signal for a gate signal line driver. This realizes a display device capable of easily generating, within a driver IC, a timing signal for writing the image data in pixels.

Abstract: A pixel of a display apparatus includes at least a first transistor and at least a second transistor. A cell of transparent fluid including particles charged to have different polarities from each other is arranged between a pixel electrode and a common electrode. The first and second transistors are connected to the pixel electrode. The pixel is drivable according to pulse amplitude modulation (PAM) and pulse width modulation (PWM) such that a frame of an image is displayable using a single field.

Abstract: An LCD device according to an embodiment includes a liquid crystal display panel in which n gate lines are formed; a timing controller to generate first to sixth clock signals; a first gate driver to apply a high gate voltage to one ends of the (2k?1)th gate lines in response to the first, third and fifth clock signals; a second gate driver to apply the high gate voltage to one ends of the (2k)th gate lines in response to the second, fourth and sixth clock signals; left discharge circuits each to apply a low gate voltage to the other end of the (2k?1)th gate line according to a voltage level on (2k+1)th gate line; and right discharge circuits each to apply the low gate voltage to the other end of the (2k)th gate line according to the voltage level on (2k+2)th gate line.

Abstract: A driving method of a liquid crystal display (LCD) device includes a step A and a step B. In the step A, using frequency conversion on a received source image signal when a type of the received source image signal is different from a preset target frequency, and converting a display frequency of the received source image signal into a target frequency, generating a target image signal based on the target frequency. In the step B, performing an overvoltage drive output using an overvoltage driving table matching with the target frequency of the target image signal.

Abstract: A display apparatus and a method for controlling the display apparatus are provided. If a display apparatus is in a power off state and an interface is connected to a cable, an output of a cable connection sensing signal is blocked. Accordingly, the display apparatus may be able to report its power off state to an external device.

Abstract: A panel display apparatus is provided which includes a timing controller, a plurality of source drivers, a first data path, and a second data path. The first data path and the second data path are both coupled between the timing controller and the source drivers. The timing controller transmits multiple display data to the source drivers via the first data path. When the source drivers detect an event (e.g. error event), the source drivers transmit at least one event data (e.g. notification data) to the timing controller via the second data path to notify the timing controller that event correction (e.g. error correction) is needed.

Abstract: A driving method of a display device having a driving transistor and a display element, one source/drain region of the driving transistor connected to a power supply part, the other source/drain region connected to an anode electrode provided in the display element, the method includes the steps of: setting a potential of the anode electrode by applying a predetermined intermediate voltage to the anode electrode so that a potential difference between the anode electrode of the display element and a cathode electrode at the other end of the display element does not exceed a threshold voltage of the display element; and then holding the driving transistor in OFF-state while a drive voltage is applied from the power supply part to one source/drain region of the driving transistor.

Abstract: An organic light emitting display device operates for an initializing period, a scan period and an emission period divided from one frame period. The organic light emitting display device includes: a data driver for supplying data signals to output lines; a connecting unit for selectively coupling a data line of data lines to a corresponding one of the output lines or an initial power supply, and being positioned between the output lines and the data lines; a second power driver for applying second power having a low level and a high level to pixels positioned at crossing regions of scan lines and the data lines; and a first control line commonly coupled to the pixels, in which each of the pixels includes an organic light emitting diode, and an anode electrode of the organic light emitting diode is supplied with a voltage of the initial power supply for the initializing period.

Abstract: An organic light emitting display device capable of improving image quality. A driving method of an organic light emitting display device in which a plurality of sub-fields may be included in one frame, wherein a first sub-field includes an initialization period in which voltage of an initialization power supply is supplied to a gate electrode of a driving transistor included in each of the pixels, a scan period that voltage corresponding to a data signal is stored in the pixels, and a light emitting period that the pixels emit light, and wherein the remaining sub-fields with the exception of the first sub-field include only a scan period and a light emitting period.

Abstract: A scroll display control device is provided, which is capable of scroll-displaying a text corresponding to a picture in such manner that the text can be easily understood. The scroll display control device scroll-displays, in synchronism with reproduction of the picture correlated to text information (TI), the corresponding text information (TI) on a text display screen (TW). A scroll speed calculation unit (102) dynamically calculates a text scroll speed (v) on the basis of a time length of a picture section presently under reproduction, a text quantity of the corresponding text section and text display setting information. A picture text control unit (104) scroll-displays text of the text section at a predetermined reference position of the text display screen (TW) according to the scroll speed (v). By displaying preceding and succeeding texts with respect to the text corresponding to the picture section presently under reproduction, it is possible to read back and pre-read.

Abstract: A driving circuit of an electro-optical device, a capacitance-line-driving circuit shifting voltage of a capacitance line to one voltage of two-value voltage, and the capacitance-line-driving circuit includes a unit control circuit provided correspondingly to the capacitance line at both end portions of the capacitance line, and the unit control circuit corresponding to one capacitance line includes, a latch circuit maintaining a logic level at one level for at least a period of the scanning line corresponding to the one capacitance line being selected, a switch provided between the capacitance line and a signal line supplying a capacitance signal in which the two-value voltage is switched over at a predetermined cycle, the switch being electrically connected when the logic level is one level and electrically disconnected when the logic level is the other level.

Abstract: A timing controller adapted to a flat display includes a voltage detecting circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detecting circuit detects a variation of an operating voltage and thus outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a constant voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and a second clock signal. A frequency of the second clock signal is obviously higher than a frequency of the first clock signal.

Abstract: An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between ?VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively.

Abstract: An emission control driver includes stages sequentially outputting emission control signals through emission control lines. Each stage includes a first signal processor receiving a first voltage and generating first and second signals in response to first and second sub-control signals, a second signal processor receiving a second voltage having a level higher than a level of the first voltage and generating third and fourth signals in response to the third sub-control signal, the first signal, and the second signal, and a third signal processor receiving the first and second voltages and generating the emission control signal in response to the third and fourth signals. The first signal processor of each stage receives the emission control signal output from a previous stage as the first sub-control signal, and the first signal processor of a first stage among the stages receives a start signal as the first sub-control signal.

Abstract: A display substrate includes a base substrate including a display area and a peripheral area, a pixel disposed on the display area, wherein the pixel includes; a pixel transistor connected to a gate line and a data line which cross each other, and a pixel electrode connected to the pixel transistor and the pixel electrode, and a gate driving circuit disposed on the peripheral area, wherein the gate driving circuit outputs a gate signal to the gate line and comprises a plurality of stages, an n-th stage of the gate driving circuit including a plurality of circuit transistors and a boosting capacitor including a first capacitor and a second capacitor, the plurality of circuit transistors and the first capacitor being disposed on a first area and the second capacitor being disposed on a second area of the peripheral area positioned between the first area and the display area.

Abstract: Disclosed are a backlight unit and a display device. The backlight unit includes alight emitting module including a plurality of light emitting devices; a controller for controlling an operation of the light emitting module; a light guide plate disposed at one side of the light emitting module; and an optical member disposed on or under the light guide plate. The light emitting module includes a first light emitting device and a second light emitting device. Light linearity of the first light emitting device is superior to light linearity of the second light emitting device, and a light orientation angle of the first light emitting device is smaller than a light orientation angle of the second light emitting device. The controller selectively drives the first and second light emitting devices.

Abstract: A display device including a voltage generator is disclosed. The voltage generator includes an analog driving voltage generator to convert a source voltage from an external source to an analog driving voltage and to output the analog driving voltage through an output terminal, a capacitor connected between the output terminal and a ground voltage node, and a discharge circuit connected between the output terminal and the ground voltage node to discharge a current at the output terminal in response to a blank synchronization signal.

Abstract: A display device includes a data driver for applying a data signal to a data line; a gate driver for applying a gate signal to a gate line; a level shifter for shifting a voltage level of a signal applied to the gate driver; and a signal controller for controlling the data driver, the level shifter, and the gate driver, wherein when a signal exchange between the data driver and the signal controller has an abnormality, the signal controller maintains a control signal applied to the level shifter in an off level.

Abstract: A display module of the present invention includes: a plurality of source drivers (SDa); a plurality of memory sections (30a, 30b) respectively provided for the plurality of source drivers (SDa), each of the plurality of memory sections (30a, 30b) being for storage of at least data of a video signal to be displayed on that one of a plurality of divided regions for which that one of the plurality of source drivers is provided, for which the memory section (30a, 30b) is provided; and timing control means (33a) serving as sync control means for synchronizing the plurality of source drivers (SDa) to synchronously output video signals that the plurality of source drivers (SDa) output based on data respectively supplied from the plurality of memory sections (30a, 30b), so that the synchronized video signals are supplied to corresponding ones of the plurality of divided regions.

Abstract: A gate driver includes: a scan signal output circuit for performing alternately scanning whereby either odd-numbered scan signal lines or even-numbered scan signal lines are sequentially driven and scanning whereby the remaining scan signal lines are sequentially driven; a rise counter circuit for sensing the rise count for a clock signal in a HIGH level period of an externally supplied start signal; a scan sequence setup circuit for setting up a scan sequence to be followed by the scan signal output circuit according to the rise count; and a start signal generating circuit for generating a start signal to be supplied to a next scan signal line driver circuit. Hence, the resultant scan signal line driver circuit and method thereof is capable of producing high quality images at low cost while restricting power consumption and heat generation by a data signal line driver circuit.

Abstract: Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

Abstract: In order to suppress an influence of an electrical stress on a TFT characteristic in use of a TFT, a light emitting display apparatus according to the present invention comprises organic EL devices and driving circuits for driving the organic EL devices. The driving circuit includes plural pixels each having a thin film transistor of which a threshold voltage reversibly changes due to the electrical stress applied between a gate terminal and a source terminal, and a voltage applying unit which sets gate potential of the thin film transistor higher than source potential. The voltage applying unit applies the electrical stress between the gate terminal and the source terminal at a time when the thin film transistor is not driven, so as to drive the thin film transistor in a region that the threshold voltage is saturated to the electrical stress.

Abstract: A display device including a display panel including gate and data line that cross each other; a first control signal generation unit generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit starting to count a number of clocks of a fixed-frequency clock signal based on a point of time at which a first state of the source output enable signal ends, and outputting a second gate output enable signal when the counted number of the clocks becomes equal to a reference value; and a gate driving unit controlling an outputting of a gate signal to the gate lines using the second gate output enable signal.

Abstract: A scan-line driving device for a LCD apparatus is provided. The scan-line driving device comprises a PWM signal generating circuit, two impedances with different resistance values, a capacitor and two scan drivers. The PWM signal generating circuit outputs a PWM signal with two potentials and a predetermined duty cycle. A terminal of the capacitor is electrically coupled to a ground potential, and the other terminal of the capacitor receives the PWM signal. Each of the scan drivers comprises a core circuit and a transistor. A source/drain terminal of each transistor is electrically coupled to a PWM signal input terminal of a corresponding core circuit and the other terminal of the capacitor, the other source/drain terminal of each transistor is electrically coupled to the ground potential through a corresponding one of the impedances, and the gate terminal of each transistor receives a turn-on control signal.

Abstract: The display device includes a driving circuit and a panel. The driving circuit is configured to generate a source output enable signal having at least one pulse during one horizontal scanning period in response to a mode signal and configured to generate a source driving signal by latching an image data in response to the source output enable signal. The driving circuit is further configured to generate an internal horizontal synchronization signal in response to the source output enable signal and configured to generate a gate driving signal in response to the internal horizontal synchronization signal. The panel is configured to display the image data in response to the gate driving signal and the source driving signal.

Abstract: Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

Abstract: One frame period of image data is divided into a plurality of subframes and driven. A first subframe included in one frame and a second subframe following the first subframe are output at opposite polarities. The image data is output while switching a phase mode between a first mode of driving the first subframe at positive polarity and the second subframe at negative polarity and a second mode of driving the first subframe at negative polarity and the second subframe at positive polarity.

Abstract: A liquid crystal material is prevented from being degraded by a voltage to control the shift of the threshold voltage which is applied to a back gate on the same conductive film as a pixel electrode. A liquid crystal display device includes a pixel circuit including a pixel electrode which applies an electric field to a liquid crystal layer; and a driver circuit including a transistor including a first gate and a second gate with a semiconductor film interposed therebetween. The transistor overlaps with the liquid crystal layer. A signal for controlling on/off of the transistor is input to the first gate. A signal for applying a first voltage is input to the second gate in a gate line selection period. A signal for alternately applying the first voltage and a second voltage is input to the second gate in a vertical retrace period.

Abstract: There is provided a display device capable of displaying an image that barely changes with low power consumption on the basis of video data included in a transmitted command, and there is also provided a method for driving the same. A display timing controller (31) determines every frame period whether or not an externally transmitted command includes updated video data. As a result, when it is determined that no updated video data is included, screen refreshing is paused by not reading video data stored in frame memory (36). Moreover, when it is determined that updated video data is included, screen refreshing is performed by reading video data stored in the frame memory (36).

Abstract: An apparatus for displaying a three-dimensional (3D) image may include a plurality of display panels and a controller configured to apply image signals to each of the plurality of display panels. At least one of the display panels may include a transparent display panel. The plurality of display panels may be spaced apart from each other in a depth direction. A method of displaying a three-dimensional (3D) image may include displaying plane images on each of a plurality of display panels. At least one of the plurality of display panels may include a transparent display panel. The plurality of display panels may be spaced apart from each other in a depth direction.

Abstract: In order that a boost converter of an LDI can reduce electromagnetic interference by generating a panel driving voltage through the use of a variable frequency, while achieving a stable boosting operation using the same frequency whenever each frame begins, an oscillator generates an oscillation signal having a frequency, which varies in a predetermined pattern or hops in a random pattern around a center frequency, and generates an oscillation signal having a preset fixed frequency whenever each frame begins.

Abstract: A mobile terminal having a dual display unit and a method of changing a display screen using the same are disclosed. The mobile terminal includes a main body, a front display unit for providing a multimedia mode, a rear display unit for providing a normal mode, and a screen control module for controlling to turn off the rear display unit and turn on the front display unit, and to display a multimedia execution screen in the front display unit. The method of changing a display screen of the mobile terminal having additional multimedia functions provides an optimum multimedia environment and improves user convenience and effectiveness of the mobile terminal by flexibly supporting a multimedia function to be executed according to a screen state of the rear display unit.

Abstract: A pixel circuit and an organic light-emitting diode (OLED) display using the pixel circuit is provided. The pixel circuit includes: an OLED; a third N-channel metal-oxide semiconductor (NMOS) transistor coupled to a data line and a first scan line and configured to apply a data signal to a first node; a storage capacitor having one terminal coupled to the first node and the other terminal coupled to a second node; a fourth NMOS transistor coupled between a first power and the second node and configured to apply a voltage of the first power to the second node; a first NMOS transistor having a first electrode, a second electrode, and a gate electrode coupled to the second node; and a second NMOS transistor coupled between the second node and the first electrode of the first NMOS transistor and configured to diode-connect the first NMOS transistor.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A power-off discharge circuit comprises a power voltage detection unit that detects whether a first power voltage for driving a source driver circuit is blocked and generates a discharge control signal, and a discharge unit that discharges a load circuit in a display panel based on the discharge control signal.

Abstract: A gate driver of on embodiment of the present invention includes: a scan signal output circuit for performing alternately scanning whereby either odd-numbered scan signal lines or even-numbered scan signal lines are sequentially driven and scanning whereby the remaining scan signal lines are sequentially driven; a rise counter circuit for sensing the rise count for a clock signal in a HIGH level period of an externally supplied start signal; a scan sequence setup circuit for setting up a scan sequence to be followed by the scan signal output circuit according to the rise count; and a start signal generating circuit for generating a start signal to be supplied to a next scan signal line driver circuit. Hence, the resultant scan signal line driver circuit and method of driving a display device is capable of producing high quality images at low cost while restricting power consumption and heat generation by a data signal line driver circuit.

Abstract: A display control/drive device (a liquid crystal controller driver and a semiconductor integrated circuit for driving liquid crystals) which can serve to reduce peak currents and thereby restrain the occurrence of EMI is to be provided. In a liquid crystal display control/drive device in which image signals to be applied to signal lines of a color liquid crystal panel are generated in response to display image data that are received, image signals for pixels of the same color are divided into a plurality of groups. And during a period in which the substantial frame frequency can be reduced, the period of a line clock matching one horizontal period is extended to slightly stagger the output timing of image signals from one to another of the groups and the sequence of outputs from the different groups is periodically varied.

Abstract: The present invention retains a scanning line for power supply in a floating state in a pause provided halfway through a period of emission.

Abstract: The present invention provides an active matrix image display apparatus including an organic EL element capable of efficiently arranging a wiring pattern on an insulating substrate compared to the related art. The present invention provides a dummy region arranged at the outermost periphery of a display unit as a scanning line coupling region or a pitch conversion region. A power supply scanning line is commonly used by a pixel circuit of an odd-numbered line and a pixel circuit of a following even-numbered line.

Abstract: A method of transmitting three dimensional video information over an interface from a playback device to a displaying device, the displaying device and the interface such that the properties of the displaying device can be queried over the interface, the method comprising determining one or more video format in which a compressed three dimensional video information is available to an input of the playback device, the three dimensional video information available either as stored on a record medium or received via a data transmission system; querying the displaying device over the interface with respect to one or more three dimensional video formats which the displaying device is able to process; selecting a best matching video format, wherein the best matching video format different from at least one available video format, the selection of the best matching video format based on the available video format and the video formats which the displaying device is able to process; processing the compressed three di

Abstract: Power consumption required for charging and discharging a source signal line is reduced in an active matrix EL display device. A bipolar transistor (Bi1) has a base terminal B connected to an output terminal c1 of an operational amplifier (OP1), a collector terminal C connected to a low power potential (GND), and an emitter terminal E connected to a resistor R2. A high power potential (VBH) is a potential in synchronization with a high power potential of a light emitting element. A potential of the output terminal c1 of the operational amplifier (OP1) is outputted as a buffer low power potential (VBL). The low power potential (VBL) corresponds to a potential difference between the high power potential (VBH) and a high power potential (V1). Accordingly, the low power potential (VBL) can follow the high power potential (VBH), that is a high power potential of the light emitting element.

Abstract: An integrated circuit device having a data line driving circuit and a position offset addition circuit that connects position offsets based on position offset setting values, wherein, among first pixel to p-th pixel of a plurality of pixels, a position offset register stores a first position offset setting value corresponding to the first pixel and a p-th position offset setting value corresponding to the p-th pixel among the first pixel to the p-th pixel; among first image data to p-th image data respectively corresponding to the first pixel to the p-th pixel, the position offset addition circuit processes a position offset correction value based on the first position offset setting value to the first image data, and processes a position offset correction value based on the p-th position offset setting value to the p-th image data among the first image data to p-th image data, to correct the position offsets.

Abstract: A source driver and a display device having the same are provided. The source driver shares several outputs by using a time division method and has an analog voltage stored in a buffer supplied to each data line multiple times during a horizontal scanning interval. Accordingly, by supplying an analog voltage to a data line a first time in a first activation interval and supplying an analog voltage to a data line a second time in a second activation interval, a target voltage of each pixel may be achieved quickly and accurately.