Abstract: A display device includes display panel includes a first source driver including a first input terminal and a first output terminal connected to the display panel; a first gate driver including a first input-output terminal, a second input-output terminal connected to the first input-output terminal, and a second output terminal connected to the display panel; a timing controller including a first terminal for outputting or inputting a first signal to or from the first input-output terminal and a second terminal; a first signal line connected to the first terminal; a second signal line connected to the second terminal; and a third signal line connected to the first source driver and the timing controller for transmitting a second signal indicating a display direction of the image data. The first source driver operates according to the first signal from the first terminal or the second terminal selected.

Abstract: According to an embodiment, an image processing device is operable by switching an operation mode among a first mode and a second mode. In the first mode, a first synchronization signal and a first image signal are inputted. The first synchronization signal comprising pulses having a first cycle, and the first image signal is composed of a plurality of frames switching in synchronization with the pulses of the first synchronization signal. In the second mode, an input of the first synchronization signal and the first image signal is stopped and a second image signal written to a frame memory is read.

Abstract: A display panel driving apparatus includes an image pattern analyzing part, a clock signal generating part and a data driving part. The image pattern analyzing part is configured to analyze an image pattern of an image data. The clock signal generating part is configured to generating a clock signal having a different pulse width according to the image pattern of an image data. The data driving part is configured to drive a data line of a display panel in response to the clock signal. Thus, power consumption and heating of the data driving part may be decreased.

Abstract: A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

Abstract: A liquid crystal display device includes: a first image signal generating unit for acquiring an image signal and for generating a first image signal in which at least a part of the pixel drive values are reduced; a second image signal generating unit for acquiring the image signal and for generating a second image signal in which at least a part of the pixel drive values are increased; a display signal selection unit for selecting one of the first image signal and the second image signal as a display signal; and a polarity control unit for controlling a polarity of the display signal. The polarity control unit inverts the polarity of the display signal. The display signal selection unit selects the first image signal in a frame immediately before the inversion and selects the second image signal in a frame immediately after the inversion.

Abstract: A gate drive circuit for a display device is disclosed, by which output states of scan pulses are identically maintained in a manner of minimizing load deviation between connecting units. The present disclosure includes at least two clock transmission lines transmitting at least two clock pulses having a phase difference in-between, a shift register outputting scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines, and a plurality of connecting units connecting the clock transmission lines to the shift register, respectively, wherein at least one of the connecting units is zigzagged in part, the at least one connecting unit comprising: a pad connected to the corresponding clock transmission line via a pad connecting unit; a zigzagged line connected to one side of the pad; and a connecting line that has one side connected to the zigzagged line and the other side connected to the shift register.

Abstract: Aspects of the present invention relate to a display device, a timing controller, and an image display method. When a frame of an input image signal including an odd-field signal and an even-field signal is received, a timing controller outputs a gate scanning clock (GCK) signal and an output enable (OE) signal in an interlaced scanning manner, to separately scan the odd-field image and the even-field image in the interlaced scanning manner in real time. The interlaced scanning manner is used for the interlaced signal, thereby saving a storage equipped in a converter.

Abstract: A display apparatus for displaying the state of an external device and a method thereof are provided. According to the present invention, messages indicating the connection state, the power state and the sleep mode of the external device are displayed on a screen of the display apparatus to which a USB is applied. Therefore, the state of an external device which inputs a video signal to the display apparatus, may be shown on the screen, and thus a user can easily know the state of the external device.

Abstract: A PWM circuit that can have two refresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two refresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal.

Abstract: A display system includes: an image output apparatus and an image display apparatus, wherein the image output apparatus has: a display image generating unit which generates a display image which is an image which the image display apparatus is caused to display; a control image generating unit which generates a control image which is an image including control information for controlling the image display apparatus; and an image output unit which outputs the display image and control image to the image display apparatus, and the image display apparatus has: a display unit which displays the input display image; a control information acquisition unit which acquires the control information included in the input control image; and a drive control unit which, based on the acquired control information, controls a drive of the image display apparatus.

Abstract: A voltage generator includes a boosting circuit boosting a power voltage to generate first through fourth voltages, and a boosting controller controlling the boosting circuit. The boosting controller sets the third and fourth voltages to a voltage level lower than that of a ground voltage while the first and second voltages are generated, so that a plurality of voltages may be stably generated, i.e., without latch-up.

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Abstract: Each of image-signal-line drive circuits includes a timing controller that generates a control signal controlling itself and other image-signal-line drive circuit, and a master/slave selection circuit that sets itself as a master mode image-signal-line drive circuit or a slave mode image-signal-line drive circuit based on a selection signal to be given from outside. From among the plurality of image-signal-line drive circuits, the master mode image-signal-line drive circuit gives the control signal to the slave mode image-signal-line drive circuit.

Abstract: A display driver integrated circuit includes a gate driving unit configured to control voltages of a plurality of gate lines connected to a display panel, a voltage boosting unit configured to supply a gate voltage to the gate driving unit, and a control logic, unit configured to receive data, a horizontal synchronization signal, and a vertical synchronization signal, generate a gate control signal based on the data, the horizontal synchronization signal, and the vertical synchronization signal, and transfer the gate control signal to the gate driving unit and the voltage boosting unit. The voltage boosting unit adjusts a level of the gate voltage based on the gate control signal.

Abstract: According to one embodiment, a circuit includes: a synchronous driver configured to generate a control signal in synchronization with an output pulse of an AC/DC converter; and an LED current controller configured to start to control a current of an LED in response to the control signal, and configured to output a stop signal for stopping the control signal when a predetermined LED current is detected; wherein the synchronous driver is caused to stop the control signal by the stop signal.

Abstract: A system performs a method for detecting display driver error. The method includes sending a first command signal to a display driver to operate according to a first operating state that includes the display driver sending a synchronization signal, and monitoring for the synchronization signal during a first time period after sending the first command signal. The method further includes sending a second command signal to the display driver to operate according to a second operating state that includes the display driver withholding sending the synchronization signal, and monitoring for the synchronization signal during a second time period after sending the second command signal. In addition, the method includes detecting a display driver error based on results of the monitoring during at least one of the first or the second time periods.

Abstract: A display device includes gate lines which transmits a plurality of gate signals, data lines which transmits a plurality of data signals, and pixels connected to the gate lines and the data lines; a signal controller which generates image data, a data control signal and a gate control signal based on an input video signal and an input control signal; a timing setter including connection pads connected to a voltage of a first level or a voltage of a second level; and a gate driver which generates timing information based on tuning signals transmitted from the timing setter through the connection pads and generates gate signals using the gate control signal and the timing information, where the gate control signal includes a scan start reference signal, which instructs a scan start, and a clock control reference signal, which controls each pulse width of the gate signal.

Abstract: In one embodiment, a display panel includes a substrate and a gate driver disposed on the substrate. The gate driver comprises a wiring unit which receives signals and a circuit unit which outputs driving signals in response to the signals received from the wiring unit. The circuit unit comprises a shift register and a shift register wiring connected to the shift register. The wiring unit comprises first through n-th signal lines (n is a natural number greater than two) arranged sequentially adjacent to the shift register. The first line is located farthest from the shift register and the n-th signal line is closest from the shift register. Further, the first signal line is electrically connected to the shift register by a first connection line that comprises a first contact portion connected to the first signal line and a second contact portion connected to the shift resistor wiring.

Abstract: A pixel includes an organic light emitting diode and a pixel control circuit. The pixel control circuit includes a first transistor, a second transistor, and a third transistor. The first transistor controls an amount of current to the organic light emitting diode from a first power source based on a voltage applied to a first node. The second transistor is coupled between the first node and a data line and turns on when a scan signal is supplied to a scan line. The third transistor is coupled between the first power source and a second node that is a common terminal of first and second capacitors, which are coupled in series between the first node and the first power source. In operation, the third transistor turns on when a first control signal is supplied to a first control line.

Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.

Abstract: In one embodiment of the present invention, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.

Abstract: A pixel circuit includes a first sub-pixel and a second sub-pixel. The first sub-pixel is coupled to a scan line and a data line, so as to determine whether to be enabled according to a first scan signal transmitted on the scan line, and whether to be driven according to a data signal transmitted on the data line. The second sub-pixel is coupled to the scan line, so as to determine whether to be enabled according to the first scan signal. The data signal is in a first state when the first scan signal is in a pre-charged period. The data signal is in a second state during a time interval after the pre-charged period is over and before the first scan signal enters a turn-on period. Voltage polarities of the first state and the second state are opposite. The pixel design can improve color shift and frame flicker.

Abstract: A display device includes a display unit including a plurality of scan lines, a plurality of data lines to which a plurality of compensation data signals are transmitted, a plurality of light emitting signal lines, and a plurality of pixels respectively connected to the plurality of scan lines, the plurality of data lines, and the plurality of light emitting signal lines, and a data driver generating a data voltage corresponding to a image data signal, and converting the data voltage to the compensation data signal. The data driver includes a compensator generating the compensation data signal in accordance with a feedback voltage. The feedback voltage is determined by a degree of deterioration associated with each pixel, and increases with an increasing deterioration degree of the pixel.

Abstract: Provided are a display device and a method for driving the same. The display device includes: a plurality of display modules; a plurality of display module drivers for respectively driving the display modules; a data divider receiving data signals for displaying an image on the display device and separating the received data signals into output data signals corresponding to each respective display module driver; and a timing control signal generator for generating a timing control signal to be supplied commonly to the display module drivers.

Abstract: A scan driver includes stages dependently connected to each other, where each of the stages outputs a gate signal, where a first scanning start signal is input to a first stage of the stages, where a second scanning start signal is input to a last stage of the stages, where each of the first scanning start signal and the second scanning start signal has one pulse per frame, where the stages sequentially output a gate-on voltage between a time when a pulse of the first scanning start signal for a frame is input to the first stage and a time when a pulse of the second scanning start signal for the frame is input to the last stage, and where the stages output a first low voltage lower than the gate-on voltage after the pulse of the second scanning start signal for the frame is input to the last stage.

Abstract: A monochrome light emitting display device and a method for fabricating the same are disclosed, in which a pixel structure of a monochrome light emitting display device is changed to improve a contrast ratio and resolution and at the same time color shift is prevented from occurring, so as to display clearer image. The monochrome light emitting display device comprises a display panel having unit pixels of first and second sub-pixels arranged in a matrix arrangement to display a monochrome image; gate and data drivers respectively driving gate lines and data lines of the display panel; and a timing controller aligning externally input RGB data to be suitable for driving of the display panel to supply the RGB data to the data driver and generating data and gate control signals to control the data and gate drivers.

Abstract: The present invention relates to an EL display device in which a stereoscopic image is perceived and eyeglasses having a switching means with which an image for a left eye or an image for a right eye is selectively perceived. The image for the left eye and the image for the right eye are displayed in a display portion of the EL display device by holding an image signal from a signal line in a first capacitor in a first period, holding the image signal held in the first capacitor in a second capacitor to control current that flows through an emission-control transistor in a second period, and turning on a driving transistor to control light emission of a light-emitting element and holding an image signal from a signal line in the first capacitor in a third period.

Abstract: To control multiple electronic circuits organized in a series configuration, this document introduces a single-wire power, control, and feedback system. Specifically, individually controlled electronic circuits are arranged in a series configuration that is driven by a control unit located at the head of the series. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the electronic circuits in the series in a manner that allows each electronic circuit to periodically draw power from the single wire and receive control information. Each electronic circuit in the series may communicate back to the head-end control unit by drawing power or not during a specified time slot.

Abstract: A driver for use in a liquid crystal display (LCD) includes a signal generator for supplying direct current (DC) voltage and control signal, the control signal comprising 3D enabling signal, a timing controlling module coupled to the signal generator, for receiving the 3D enabling signal, and a DC/DC converter coupled to the signal generator, for outputting vertical synchronous signal to a gate driver to drive a pixel array of the LCD upon receiving 3D enabling signal. The present invention also proposes a driving method for driving an LCD and related LCD. The present invention proposes a simplified circuit design and reduce cost.

Abstract: An electro-optic device includes an electro-optical panel and a polarization axis conversion unit that emits transmission lights corresponding to a first image or a second image with the polarization axis of the first image intersecting the polarization axis of the second image, by converting the polarization axis of the lights emitted from the electro-optical panel. The electro-optic device further includes a scanning signal supply unit supplying scanning signals through the plurality of scanning lines and an image signal supply unit supplying a first image signal corresponding to a first image to the plurality of pixel sections during a first field period and supplying a second image signal corresponding to a second image to the plurality of pixel sections during a second field period through the plurality of data lines, the first field period and the second field period being divided into a plurality of subfield periods respectively.

Abstract: A gaming system is disclosed for presenting both game content and secondary content on a single display. The gaming system includes: a touch screen game display configured to display content, a gaming controller configured to generate game content, and a secondary controller configured to generate secondary content. The display manager scales at least one of the game content and the secondary content to an altered size, enabling the game content from the gaming controller to be rendered with the secondary content from the secondary controller on the touch screen game display. The gaming system also includes a coordinate transformation calculation device that receives coordinates from an input on the touch screen game display and accommodates any scaling or shifting performed on at least one of the game content and the secondary content to determine transformed coordinates corresponding to the altered size of the rendered content.

Abstract: A system, method, and computer program product are provided for enhancing a viewing experience when display content is viewed utilizing stereo glasses. In use, display content is received for being outputted utilizing a display. Further, a duration of a vertical blanking interval associated with the display content is increased for enhancing a viewing experience when the display content is viewed utilizing the stereo glasses.

Abstract: In at least one embodiment, an electro-optical device displays a right-eye image and a left-eye image for each display period. The driving circuit supplies a gradation potential to each of the pixels according to a specific gradation using image data which corresponds to the unit period in each of a plurality of unit periods in each of the display periods, and sequentially selects one or more scanning lines in a plurality of lines and supplies a gradation potential to each of the signal lines according to a specific gradation of each of the pixels which corresponds to the one or more scanning lines in a selected state in a unit period in each of the display periods. A driving control section executes overdrive of each of the pixels in the driving circuit in a first unit period in each of the display periods.

Abstract: A module circuit (11) comprises a sensor terminal (43) for feeding a sensor signal (SP) and a clock terminal (41) for feeding a pulse width-modulated clock signal (ST) having a first and a second clock phase (A, B). A signal processing circuit (40) of the module circuit (11) is coupled on the input side to the sensor terminal (43) and the clock terminal (41) and is designed to provide an output signal (SAL) dependent on the sensor signal (SP) that can be tapped in the first clock phase (A) and independent of the sensor signal (SP) that can be tapped in the second clock phase (B).

Abstract: Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged.

Abstract: Systems and methods provide automatic switching of display update properties such as screen resolution, pixel depth, and refresh rate in response to a power management event. The display update property may be decreased when power is switched from AC power to DC power, for example, when the system is unplugged from a wall outlet and is running on battery power.

Abstract: A timing controller and a Liquid Crystal Display (LCD) using the same are discussed. The timing controller according to an embodiment includes a reception unit which receives a video signal and a timing signal from a system; a control signal generation unit which generates a gate control signal and a data control signal with the timing signal, and outputs the gate control signal and the data control signal to a gate driver and a data driver, respectively; an image signal generation unit which realigns the video signal to output a realigned image signal; and a delay compensation unit which performs delay compensation for the realigned image signal with a circuit recombined according to a delay compensation value between each data drive Integrated Chip (IC) of the data driver and the image signal generation unit, and outputs the delay-compensated image signal to each data drive IC.

Abstract: Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

Abstract: A power supply circuit of a liquid crystal display device includes a first positive polarity charge charging unit including a first capacitor connected to positive and negative power terminals through switches to charge a charge, a second positive polarity charge charging unit including a second capacitor connected to the positive power terminal and a ground terminal through switches to charge a charge, a first positive polarity charge loading unit loading the charge supplied through the positive power terminal to a negative polarity terminal, a second positive polarity charge loading unit loading the charge charged in the first capacitor to a negative polarity terminal, a third positive polarity charge loading unit loading the charge charged in the second capacitor, and a positive polarity charge charging/loading control unit outputting charging control signals with a same phase to the switches, and periodically or irregularly changing durations of the charging and loading control signals.

Abstract: Provided is a stereoscopic image display device comprising a display panel displaying a multi-view image in a three-dimensional (3D) mode, a switchable barrier forming a barrier in the 3D mode, a user position detecting unit outputting a user position data including a user position information, a switchable barrier controlling unit calculating an average picture level of the multi-view image in the 3D mode and controlling an aperture ratio of the switchable barrier according to the average picture level and the user position information, a switchable barrier driving unit supplying driving voltages to divided electrodes of the switchable barrier and supplying a common voltage to a barrier common electrode, and a display panel driving unit converting the multi-view image into data voltages to supply the data voltages to data lines of the display panel and sequentially supplying gate pulses to gate lines of the display panel.

Abstract: A display device includes: a plurality of display panels arranged adjacent to each other in a line scanning direction to form one screen; a master controller configured to drive one of the display panels; and one or more slave controllers configured to drive the other display panels, each of the slave controllers corresponding to each of the other display panels. The master controller is configured to drive the display panel based on a scanning control signal and a clock signal which are generated, and output the generated scanning control signal and the generated clock signal and each of the slave controllers is configured to drive the corresponding display panel based on the scanning control signal and the clock signal inputted from the master controller.

Abstract: A display apparatus includes pixels arranged in a two-dimensional matrix pattern, each of which including a light-emitting unit and a drive circuit that drives the unit and includes a comparator circuit that compares a control pulse with potential based on signal voltage and outputs predetermined voltage based on the result, a transistor driving the unit in response to the predetermined voltage, and a current source that supplies current to the unit during driving of the transistor, includes a current-source transistor, a capacity unit connected to a gate electrode of the current-source transistor, a differential amplifier that detects a differential between voltage based on reference constant current and reference voltage, and a transistor controlling the voltage based on reference constant current depending on current flowing through the current-source transistor, and controls gate potential of the current-source transistor on the basis of output of the amplifier in synchronization with a scanning signal.

Abstract: A liquid crystal display (LCD) device and a driving method thereof for improving a working efficiency of the LCD and reducing manufacturing costs. The liquid crystal display device includes a liquid crystal display panel having liquid crystal cells at crossings of data lines and gate lines, data integrated circuit supplying pixel data via a plurality of data output channels, a gate integrated circuit driving the gate lines, a channel selector for selecting the plurality of data output channels of the data integrated circuits in accordance with a number of the data lines wherein only the selected data output channels contain the pixel data, and a timing controller for controlling the data integrated circuit and the gate integrated circuit.

Abstract: Techniques are described that can be used to adjust a refresh rate of a display device. For example, the refresh rate change can be triggered by a user application for a variety of circumstances such as a change in power source from AC to DC or display of 24 frames per second (fps) video. Contents of a primary buffer can be copied to a dummy buffer and a display engine can read video from the dummy buffer to provide video to a display. The clock rate of a clock used to read out pixels can be adjusted using software commands. Video is written to another buffer and during a vertical blanking interval, the display engine reads frames from the another buffer instead of the dummy buffer.

Abstract: The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element.

Abstract: The liquid crystal display device includes: first and second substrates disposed facing each other via a liquid crystal layer, each substrate having a plurality of pixels arranged thereon in matrix form; a first electrode formed for each pixel on the first substrate side; a second electrode formed for each pixel on the first or second substrate side; and the liquid crystal layer being driven by a liquid crystal drive voltage applied between the first and second electrodes; wherein an inequation of VLmin?VLmax<Vmax is satisfied, where VLmin is a liquid crystal drive voltage applied to the pixel to produce minimum brightness, VLmax is a liquid crystal drive voltage applied to the pixel to produce maximum brightness, and Vmax is a maximum liquid crystal drive voltage applied to the pixel.

Abstract: A source driver integrated circuit (IC) includes a logic circuit configured to receive a transmission data packet including data, a compression code indicating compression or non-compression of the data, and a clock signal, to interpret the compression code, and to generate a sleep mode enable signal based on an interpretation result, and a clock signal recovery circuit configured to enable one of a voltage-controlled delay line and a voltage-controller oscillator in response to the sleep mode enable signal.

Abstract: A source driving circuit includes an output buffer circuit to compensate for slew rate of signals used to drive a display device. The output buffer circuit includes a bias current control signal generating circuit and a channel amplifying circuit. The bias current control signal generating circuit performs an exclusive OR operation on an input signal and an output signal of a reference operational amplifier to generate a bias current control signal. The channel amplifying circuit adjusts the slew rate of a plurality of output voltage signals in response to the bias current control signal. The output signals are then used to control the display device.

Abstract: The driver IC generates a common voltage to be applied to a common electrode of pixels of a display panel, and generates a high level of a pulse voltage used for driving, by pulses, drive electrodes of a touch panel with its low level set at the common voltage based on data held by a memory region for holding voltage-designating data of the common voltage and amplitude-designating data of the pulse voltage. In addition, the driver IC outputs the common voltage to drive terminals in synchronization with the action timing of the display panel, and outputs a pulse voltage having an amplitude of the high level with respect to the common voltage to the drive terminals in synchronization with the action timing of a touch panel.

Abstract: A monitor control system capable of reprogramming the function of a LCD monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.