Abstract: One embodiment of the present invention provides a system that switches from a first graphics processor to a second graphics processor to drive a display. During operation, the system receives a request to switch a signal source which drives the display from the first graphics processor to the second graphics processor. In response to the request, the system first configures the second graphics processor so that the second graphics processor is ready to drive the display. Next, the system switches the signal source that drives the display from the first graphics processor to the second graphics processor, thereby causing the second graphics processor to drive the display.

Abstract: A computer system may comprise a graphics controller, which may support a display handler. In one embodiment, the display handler may receive configuration values comprising a quantity value and a blending order. In one embodiment, the display handler may determine the number of universal pixel planes using the quantity value. The display handler may provide a number of universal pixel planes equal to the quantity value and the universal pixel planes may be provided using a reference universal pixel plane. The display handler may render each of the universal pixel planes into a type of pixel plane indicated by the corresponding elements of the blending order.

Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.

Abstract: An electrical device supporting switchable graphics function, electrically connected with a display unit, includes a first graphic chip, a second graphic chip, a peripheral, an Embedded Controller (EC) and a processing unit. Information of a present graphic chip is stored in an EC RAM of the EC, wherein the present graphic chip is one of the first graphic chip and the second graphic chip. A control unit of the EC obtains the information of the present graphic chip from the EC RAM and controls operation status of the peripheral according to the obtained information of the present graphic chip. The processing unit obtains the information of the present graphic chip from the EC RAM. The processing unit drives the present graphic chip to process an image signal and transmit the processed image signal to the display unit for display according to the obtained information of the present graphic chip.

Abstract: Respective video feeds are provided to at least two viewers using a common display. The display is controlled to simultaneously display an image from a first video feed and an image from a second video feed. The image from the first video feed is displayed within a first wavelength band and the image from the second video feed is displayed within a second wavelength band, and the first and second wavelength bands are distinct. A first filter is selective for transmitting the first wavelength band and not transmitting the second wavelength band. A second filter is selective for transmitting the second wavelength band and not transmitting the first wavelength band. Only the first video feed image is provided to a first viewer using the first filter, and only the second video feed image is provided to a second viewer using the second filter.

Abstract: A method for offloading remote terminal services processing tasks to a peripheral device that would otherwise be performed in a computer system's processor and memory. In one embodiment, the disclosed method is utilized in a layered network model, wherein computing tasks that are typically performed in network applications are instead offloaded to a peripheral such as a network interface card (NIC).

Abstract: A method for switching decoding and rendering of a digital video stream from a first graphics processing unit (GPU) to a second GPU. The digital video stream is evaluated to determine an amount of time until a next intra-coded frame (I-frame) in the digital video stream. If the amount of time is below a threshold, decoding and rendering of the digital video stream is switched to the second GPU on the next I-frame in the digital video stream and decoding the digital video stream by the first GPU is stopped. If the amount of time is above the threshold, the digital video stream is decoded on both the first GPU and the second GPU, the rendering of the digital video stream is switched to the second GPU, and decoding the digital video stream by the first GPU is stopped.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: Techniques for implementing a secure graphics architecture are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module, and the graphics management module may be operative to receive graphics information from the processor circuit, generate graphics processing information based on the graphics information, and send the graphics processing information to a graphics processor circuit arranged to generate graphics display information based on the graphics processing information. In this manner, security threats such as screen capture attacks and/or theft of content protected media streams may be reduced. Other embodiments may be described and claimed.

Abstract: An image processing apparatus includes a plurality of image processing module parts, a module arbiter part, and a DMAC (Direct Memory Access Controller) part. Each of the image processing module parts includes a module core for executing a predetermined image processing. The plurality of image processing module parts is connected to the module arbiter part. The module arbiter part arbitrates memory access which is given by the plurality of image processing module parts through a bus. The DMAC part is connected between the module arbiter part and the bus, and executes memory access related to the arbitration result obtained by the module arbiter part.

Abstract: The described embodiments provide a system that facilitates a switch from using a first graphics-processing unit (GPU) to using a second GPU to drive a display. During operation, upon generation of a request to switch from using the first GPU to using the second GPU as a signal source for driving the display, the system obtains a transform (such as a lookup table) that enables the displayed color output from the second GPU to substantially match the displayed color output from the first GPU. The system then makes the transform available for use by the second GPU in driving the display.

Abstract: A printing apparatus includes a first processor which is connected to a first memory and converts print data into an image data format based on a page description language, a second processor which is connected to a second memory and performs image processing for print data of the image data format to generate data of a format interpretable by a printing unit, and a communication control unit which externally receives print data and transfers the received print data to either the first memory or second memory based on a descriptor. The second processor determines the format of received print data. When the print data has the page description language format, the first memory is set as the transfer destination in the descriptor. When the print data has the image data format, the second memory is set as the transfer destination in the descriptor.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: The desire to use an Accelerated Processing Device (APD) for general computation has increased due to the APD's exemplary performance characteristics. However, current systems incur high overhead when dispatching work to the APD because a process cannot be efficiently identified or preempted. The occupying of the APD by a rogue process for arbitrary amounts of time can prevent the effective utilization of the available system capacity and can reduce the processing progress of the system. Embodiments described herein can overcome this deficiency by enabling the system software to pre-empt a process executing on the APD for any reason. The APD provides an interface for initiating such a pre-emption. This interface exposes an urgency of the request which determines whether the process being preempted is allowed a grace period to complete its issued work before being forced off the hardware.

Abstract: The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision.

Abstract: A main processor collects the edge information and color information of the pixels of a rendering target image using a rendering command, and sends the collected edge information and color information of the pixels to a sub-processor of the succeeding stage. The sub-processor sends the edge information and color information of a left rectangular region to a sub-processor, and also renders a right rectangular region and, upon receiving a process wait signal from the sub-processor, sends the rendering result to the sub-processor. The sub-processor renders the left rectangular region and sends the rendering result to the outside, and also sends, to the outside, the rendering result of the right rectangular region acquired by sending a process wait signal to the sub-processor.

Abstract: Disclosed are methods and apparatus for augmenting a user's multimedia consumption experience. The methods comprise whilst the user is consuming the multimedia presentation using a first device, that device provides (to one or more remote processors) information that may be used to identify a relevant location. The one or more processors use this information to identify the location and acquire a virtual environment. This virtual environment may be a virtual representation the location. The virtual environment is presented to the user on a second (companion) device. Using the second device, the user may explore the virtual environment and interact with virtual objects therein.

Abstract: A portable terminal that includes a first processing core configured to process data; a second processing core, which is faster than the first processing core, configured to process the data; and a storage unit configured to store multimedia data. The first and second processing cores are integrated into a single chipset, and are configured to be individually enabled or disabled based on a workload. The portable terminal is configured to be operated in one of a standby state and an operating state, to play back the multimedia data stored in the storage unit, and for Internet access.

Abstract: A message passing scheme for MAP inference on Markov Random Fields based on a message computation using an intermediate input vector I, an output message vector M, an auxiliary seed vector S, all of equal length N, and a pairwise function r=d(x,y), where r,x,y are real numbers, includes: for each element j of vector S, do S(j)=j consider an index distance ?=2?floor(log2(N)); repeat while ?>0 for each index of vector I, namely i, do in parallel: consider the set of all indices within distance A from a given i, augmented by i; for every k belonging to this set, calculate its distance from i using the function: d(i,k)+I(S(k)); find the minimum distance and call n the index corresponding to this minimum distance do S(i)=S(n) ?=floor (?/2) for each j of vector M, do M(j)=I(S(j))+d(j,S(j)).

Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.

Abstract: Three dimensional scenes may be managed between a central processing unit and a graphics processing unit using shared and unified graphics processing unit memory. A shared bus memory may be synchronized between the central processing unit and the graphics processing unit. The shared bus memory may be used for more often updated components and other memory may be used for less often updated components. In some embodiments, if the graphics processor and the central processor use a common processor instruction set architecture, data can be sent from the central processor to the graphics processor without serializing the data.

Abstract: Apparatus having corresponding methods comprise a processing core performance monitoring module adapted to receive indications of performance levels of a plurality of processing cores, the plurality of processing cores comprising a central processing unit (CPU), a video accelerator, and a graphics accelerator; a video accelerator performance monitoring module adapted to receive an indication of a performance level of the video accelerator; a graphics accelerator performance monitoring module adapted to receive an indication of a performance level of the graphics accelerator; and a processor core management module adapted to dynamically allocate at least one of a pre-processing task and a post-processing task of a multimedia workload to any one of the video accelerator, the graphics accelerator, and the CPUprocessing cores based on the performance levels of the video accelerator, the graphics accelerator, and the CPU.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: Among other things, dynamically selecting or configuring one or more hardware resources to render a particular display data includes obtaining a request for rendering display data. The request includes a specification describing a desired rendering process. Based on the specification and the display data, hardware is selected or configured. The display data is rendered using the selected or configured hardware.

Abstract: A rendering device includes a temporary memory, plural rendering processors, and a rendering controller. The temporary memory stores one or more rendering instructions and rendered results therefor in association with each other. The plural rendering processors each perform rendering processing in accordance with a rendering instruction, store the one or more rendering instructions and rendered results in association with each other in the temporary memory, when one or more similar rendering instructions exist for pages for which rendering processing was consecutively performed, and read and use the rendered results, in a case where rendered results associated with one or more rendering instructions are stored in the temporary memory. The rendering controller controls assigning a given rendering instruction to a corresponding one of the rendering processors in accordance with a given page editing instruction and causing the corresponding one of the rendering processors to perform rendering processing.

Abstract: Methods, apparatuses, and computer readable media are disclosed for responding to requests. A method of responding to requests may include receiving requests comprising callback functions. The one or more requests may be received in a first memory associated with processors of a first type, which may be CPUs. The requests may be moved to a second memory. The second memory may be associated with processors of a second type, which may be GPUs. GPU threads may process the requests to determine a result for the requests, when a number of the requests is at least a threshold number. The method may include moving the results to the first memory. The method may include the CPUs executing the one or more callback functions with the corresponding result. A GPU persistent thread may check the number of requests to determine when a threshold number of requests is reached.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores.

Abstract: The time needed for back-end work can be estimated without actually doing the back-end work. Front-end counters record information for a cost model and heuristics may be used for when to split a tile and ordering work dispatch for cores. A special rasterizer discards triangles and fragments outside a sub-tile.

Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Abstract: An apparatus to widen the light dispersion pattern of a light source shining through an overlay window from the viewing side of an electrical computer system. The overlay window is coupled to a panel of the system. The overlay window includes a transparent material, which has a first surface facing the light source and a second surface facing away from the light source to define a viewing side. An opaque material can be disposed on the first surface to partially cover the first surface to form a viewing window. A first diffusing mechanism is disposed on the first surface, and a second diffusing mechanism is disposed on the second surface. In response to the passage of the light output through the viewing window, the light dispersion pattern of the light output from the viewing side of the overlay window has a viewing angle of up to about 180 degrees.

Abstract: A method includes rendering an object of a three dimensional image via a pixel shader based on a render context data structure associated with the object. The method includes measuring a performance statistic associated with rendering the object. The method also includes storing the performance statistic in the render context data structure associated with the object. The performance statistic is accessible to a host interface processor to determine whether to allocate a second pixel shader to render the object in a subsequent three-dimensional image.

Abstract: A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.

Abstract: In general, this disclosure relates to techniques for using graphics instructions and state information received from a graphics device to visually create a graphics image. Performance analysis may also be conducted to identify potential bottlenecks during instruction execution on the graphics device. One example device includes a display device and one or more processors. The one or more processors are configured to receive a plurality of graphics instructions from an external graphics device, wherein the graphics instructions are executed by the external graphics device to display a graphics image, and to receive state information from the external graphics device, wherein the state information is associated with execution of the graphics instructions on the external graphics device. The one or more processors are further configured to display, on the display device, a representation of the graphics image according to the graphics instructions and the state information.

Abstract: Backlit LCD displays are becoming commonplace within many vehicle applications. The unique advantage of this invention is that it optimizes system power savings for display of low dynamic range (LDR) images by dynamically controlling spatially adjustable backlighting. This is accomplishes through use of a control technique that takes into account the sequential nature of the video display process.

Abstract: A data processing apparatus in which pipeline processing is performed comprises a control unit that controls a data processing sequence, a first processing unit that begins first data processing by inputting data on the basis of a start signal, outputs data subjected to the first data processing, and outputs a completion signal to the control unit after completing the first data processing, and a second processing unit that begins second data processing by inputting the data subjected to the first data processing on the basis of a start signal, outputs data subjected to the second data processing, and outputs a completion signal to the control unit after completing the second data processing. The control unit outputs a following start signal to the first processing unit and the second processing unit upon reception of the completion signal of the first data processing and the second data processing respectively.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Abstract: A software layer is disposed between an application and a driver. In use, the software layer is adapted to receive an object from the application intended to be rendered by a first graphics processor. Such software layer, in turn, routes the object to a second graphics processor, based on a policy.

Abstract: A secondary graphics processor control system includes a secondary graphics processor. A controller is coupled to the secondary graphics processor. The controller detects the start of an application that is associated with a secondary graphics processor and then determines a power capability of a battery. The controller then either prevents enablement of the secondary graphics processor if the power capability is below a predetermined threshold such that only a primary graphics processor processes graphics for the application, or allows enablement of the secondary graphics processor if the power capability is above the predetermined threshold such that the secondary graphics processor processing graphics for the application. The primary graphics processor may be an integrated graphics processing unit (iGPU) provided by a system processor that is mounted to a board, and the secondary graphics processor may be a discrete graphics processing unit (dGPU) that is coupled to the board.

Abstract: The disclosed embodiments provide a system that configures a computer system to switch between graphics-processing units (GPUs). In one embodiment, the system drives a display using a first graphics-processing unit (GPU) in the computer system. Next, the system detects one or more events associated with one or more dependencies on a second GPU in the computer system. Finally, in response to the event, the system prepares to switch from the first GPU to the second GPU as a signal source for driving the display.

Abstract: A system and method force a display device to receive the output produced by a graphics processing unit that is configured as the video graphics array (VGA) boot device for display of critical system screens. A hybrid computer system that includes multiple graphics processors configures a display multiplexor to select image data from one of the multiple graphics processing units for output to the display device. When a critical system event occurs and the graphics processing unit that is selected is not configured as the VGA boot device, system basic input/output system (BIOS) interfaces are used to configure the multiplexor to select the one graphics processing unit that is configured as the VGA boot device to output the critical system screen to the display device.

Abstract: One embodiment of the present invention sets forth a technique for detecting duplicate vertex indices in parallel and batching indices defining multiple primitives for parallel primitive processing. A lookback cache breaks the dependent loop for the miss processing. Because each index is compared to all previous indices (duplicate or not), each index is not dependent on whether the previous indices have hit or missed. This allows the comparison operation that detects the duplicate vertex indices to be fully pipelined. The duplicate vertex indices are removed to reduce the number of indices that define the primitives in the batch. Multiple, independent rasterizer units operate concurrently on the different batches of graphics primitives to render multiple primitives per system clock.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: An automated method of quantifying a set of processing resources used by an image transform operation is described. The method receives a set of image processing instructions for performing the transform operation, and, for the set of image processing instructions, generates data that estimates the amount of processing resources required to perform the set of image processing instructions. The method associates the data with the set of image processing instructions, the association allowing evaluation of the data at run-time to facilitate execution of the set of image processing instructions on a particular processing unit having a particular set of processing resources. In addition, an automated method of concatenating a plurality of image processing instruction sets, where each image processing instruction set includes data representing an estimate of processing resources required by the image processing instruction set is described.

Abstract: An image processing device, in a case in which an image processing module, uses in image processing a processor that is different than a processor used in image processing by an image processing module of a preceding stage, is connected at a subsequent stage, carries out transfer processing that transfers image data, that has been written into a buffer by the image processing module of the preceding stage, to a buffer for transfer that is reserved in a memory space corresponding to the processor that the image processing module of the subsequent stage uses in image processing, and carries out processing that causes the image processing module of the subsequent stage to read-out the image data transferred to the buffer for transfer.

Abstract: An electronic device comprises at least two graphics processors, referred to herein as an integrated graphics processor and a discrete graphics processor. In some circumstances, the device may be switched between the integrated graphics processor and the discrete graphics processor. In some embodiments, techniques are implemented to lock temporarily the screen display on the output of a controller while the device executes a switch between graphics processors, thereby eliminating, or at least reducing, the presence of a blank output display on the electronic device. Other embodiments may be described.

Abstract: A method for utilizing a CUDA based GPU to accelerate a complex, sequential task such as video decoding, comprises decoding on a CPU headers and macroblocks of encoded video, performing inverse quantization (on CPU or GPU), transferring the picture data to GPU, where it is stored in a global buffer, and then on the GPU performing inverse waveform transforming of the inverse quantized data, performing motion compensation, buffering the reconstructed picture data in a GPU global buffer, determining if the decoded picture data are used as reference for decoding a further picture, and if so, copying the decoded picture data from the GPU global buffer to a GPU texture buffer. Advantages are that the data communication between CPU and GPU is minimized, the workload of CPU and GPU is balanced and the modules off-loaded to GPU can be efficiently realized since they are data-parallel and compute-intensive.

Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.