Abstract: Pixels output a first signal based on signal charge of a part of photoelectric conversion units of multiple photoelectric conversion units, and a second signal based on signal charge of multiple photoelectric conversion units. An imaging apparatus outputs signals based on the first signals and signals based on the second signals by reducing the number of signals based on the first signals as compared to the number of signals based on the second signals.

Abstract: Disclosed is a thin film transistor substrate which facilitates to realize a bottom gate structure where a gate electrode is disposed below an active layer, and to increase an area for a storage capacitor, and a display device including the same, wherein the thin film transistor substrate may include a light shielding layer, a buffer layer for covering the light shielding layer, and a driving transistor prepared on the buffer layer while being overlapped with the light shielding layer, and provided to supply a driving current to an organic light emitting device.

Abstract: The present application provides a reset circuit for a shift register circuit, a shift register circuit, a gate driving circuit, a display apparatus, and a driving method. The reset circuit comprises a first adjustment control circuit having an input terminal configured to receive a ground line signal, and a control terminal configured to receive a first control signal; a second adjustment control circuit having an input terminal configured to receive an adjustment signal via an adjustment signal input terminal, a control terminal configured to receive a second control signal, and an output terminal configured to be coupled to an output terminal of the first adjustment control circuit; and a storage circuit having a first terminal connected to the output terminals of the second adjustment control circuit and the first adjustment control circuit, and a second terminal connected between a reset signal input terminal and a transistor.

Abstract: A data driver of a microLED display includes clock generators that generate pulse width modulation (PWM) clocks of corresponding primary colors respectively; counters that receive the PWM clocks of corresponding primary colors respectively and accordingly generate corresponding PWM signals; and comparators associated with corresponding data channels respectively for comparing a held data signal with the corresponding PWM signal, thereby generating a comparison result signal. In one embodiment, the data driver further includes switches configured to electrically short output nodes of channel amplifiers of corresponding primary colors respectively for testing uniformity of microLEDs of one color.

Abstract: Disclosed is a phasing adder including delay charge transfer units including holding and transferring units which obtain signal charge amounts that are not amplified and which send and receive the signal charge amounts across a predetermined plurality of stages while holding the signal charge amounts for a predetermined time in each stage and a delay adder which performs phasing addition of the signal charges which are held for a predetermined number of stages in the delay charge transfer unit, and electric capacity of each first holding unit, which is the first stage among the plurality of stages in the holding and transferring unit, where the signal charges are obtained and held at a time of ultrasound wave reception is greater than electric capacity of each of later holding units where the signal charges are to be held in a second stage and stages thereafter.

Abstract: A source driver circuit includes a receiver, a plurality of amplifying buffers, and a control logic circuit. The receiver receives a data signal and a control signal through an input terminal. Each of the amplifying buffers outputs a driving signal generated based on the image data signal through an output terminal. The control logic circuit controls the receiver and the plurality of amplifying buffers based on the control signal. When a power-down signal is provided to the receiver, the control logic circuit is to turn off at least one of the receiver and the plurality of amplifying buffers.

Abstract: The present invention provides a display device comprising: a display panel including a data line, a gate line, and a pixel; a data driver configured to output a data signal to the data line; a gate driver configured to output a gate signal to the gate line; and a signal controller configured to control the data driver, and the gate driver, wherein at least one of the data driver and the gate driver comprises a first current monitoring unit configured to monitor output current of the at least one of the data driver and the gate driver.

Abstract: The present disclosure provides a color cast compensation method, which includes: obtaining a first gray value of a first pixel electrode currently to be charged; determining a second gray value of a second pixel electrode on a previous row sharing a same data line with the first pixel electrode; and obtaining a target charging voltage of the first pixel electrode based on the first gray value and the second gray value. The present invention solves the problem of display quality affected by rough fonts, caused by jaggies appearing on a triple-gate type display panel.

Abstract: A display degradation compensation system and method for adjusting the operating conditions for pixels in an OLED display to compensate for non-uniformity or aging of the display. The system or method sets an initial value for at least one of peak luminance and an operating condition, calculates compensation values for the pixels in the display, determines the number of pixels having compensation values larger than a predetermined threshold compensation value, and if the determined number of pixels having compensation values larger than said predetermined threshold value is greater than a predetermined threshold number, adjusts the set value until said determined number of pixels is less than said predetermined threshold number.

Abstract: A display screen and a display device are provided. The display device includes: a first display screen; a display screen group arranged on a back surface of the first display screen, the display screen group including at least one second display screen, and a display surface of the second display screen facing the first display screen; and a rotating shaft, the rotating shaft connecting a first side edge of each of the second display screens in the display screen group with a first side edge of the first display screen and being perpendicular to the first display screen and the second display screen. The display device has characteristics of adjustable display screen size and strong flexibility in use.

Abstract: An apparatus includes an active region, a source driving circuit, and a light emitting driving circuit. The active region includes an array of light emitting elements corresponding to an array of pixels arranged in M rows and N columns. The number of the array of light emitting elements is k times of the number of the array of pixels. The apparatus includes xM light emitting lines and (k/x)N source lines, wherein x is a positive fraction, and each of xM and (k/x)N is a positive integer. The source driving circuit is operatively coupled to the active region via the (k/x)N source lines and configured to write display data of a frame to the array of light emitting elements. The light emitting driving circuit is operatively coupled to the active region via the xM light emitting lines and configured to cause the array of light emitting elements to emit light.

Abstract: There are disclosed a display substrate and a display device. The display substrate comprises a common electrode line, a plurality of pixel units with each comprising a pixel electrode and a plurality of first switch units disposed respectively between the common electrode line and the pixel electrodes. Each of the first switch unit is configured to be turned on within a pre-set time period after the display substrate is powered off to connect the pixel electrode to the common electrode line and be turned off when the display substrate is powered on to disconnect the pixel electrode from the common electrode line. In this way, after the power-off, the charges stored in the pixel electrode are neutralized in the common electrode line. Thus, the pixel electrode and the common electrode can be discharged by the same discharge circuit, which guarantees no DC residue in the discharged pixel electrode.

Abstract: A liquid crystal display of a three TFT structure includes arrayed pixel units, a data drive chip, a row drive chip, a timing controller, and a discharge module. The discharge module includes control terminals and voltage output terminals. The control terminals of the discharge module are respectively connected to control terminals of the timing controller. The first pixel unit includes three TFTs, a first liquid crystal display unit, and a second liquid crystal display unit. The three TFTs include a main TFT, a sub TFT, and a shared TFT. The voltage output terminal of the discharge module supplies a first discharge voltage when the first pixel unit is in the state of positive polarity driving and supplies a second discharge voltage when the first pixel unit is in the state of negative polarity driving. The first and second discharge voltages are both greater than a voltage of the common electrode.

Abstract: A flexible display and a method of manufacturing the same are disclosed. In one aspect, the flexible display includes a flexible display panel including an active area displaying configured to display an image and an inactive area extending towards the outside of the active area, and a plurality of wires disposed over the flexible display panel in the inactive area and transmitting configured to transmit an electric signal to the active area. A bending hole is disposed at a corner where two adjacent edges of the flexible display panel meet in the inactive area. The bending hole is interposed between the plurality of the wires and the active area. The corner is folded so as to define a folding region.

Abstract: A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part (220) configured to generate a reference gradation voltage based on a first or second gamma characteristic of the display panel, using first and second power supply voltages (VH) and (VL) inputted through first and second external terminals (PA2, PA3); and a third external terminal (PA4) for externally outputting said reference gradation voltage. The source driver IC chip further includes first and second gradation voltage generating parts configured to generate first and second gradation voltages respectively, using a reference gradation voltage based on a first gamma characteristic inputted through a fourth external terminal and a reference gradation voltage having a second gamma characteristic inputted through a fifth external terminal respectively.

Abstract: Memory is reserved in a virtualized computing environment for graphics processing of each child partition in the computing environment. A video memory controller can identify video settings for child partitions. The video memory controller can determine an amount of memory for graphics processing for a child partition based on the video settings for that child partition. The video memory can also request an amount of memory to be reserved for that child partition based on the calculated amount of memory. Reserving memory for graphics processing of child partitions in this way allows for a sufficient amount of memory to be reserved for a child partition without wasting memory resources by reserving significantly more memory than is needed for the child partition.

Abstract: A measurement method and apparatus for a residual direct-current component and a system where the measurement method for a residual direct-current component includes: selecting a section of data of a first predetermined length from a received signal; performing fast Fourier transform on the selected data to obtain a frequency-domain signal of the data; calculating a power spectrum of the frequency-domain signal of the transformed data; and finding out a maximum peak value of the power spectrum in a frequency offset range, and taking power of the maximum peak value as power of the residual direct-current component. With the embodiments of this disclosure, a residual direct-current component of an optical transmitter may be measured at a receiver end of a coherent optical communication system, thereby avoiding a diagnosis error of a communication network, and improving performance of the communication system.

Abstract: Disclosed are an in-cell touch type touch display device that includes a touch display panel, where a plurality of touch sensors are disposed, and a driving circuit unit. Each of the plurality of touch sensors are disposed to correspond to a plurality of subpixels, and each of the plurality of touch sensors may include one or more touch switches. The one or more touch switches disposed in each of the plurality of touch sensors divisionally drive the plurality of touch sensors by 1/n (where n is a natural number equal to or more than two).

Abstract: A power supply circuit includes a comparison circuit, a preset value setting circuit, a reset detecting circuit and a reset signal generating circuit. The comparison circuit compares a first and second voltage to output a comparing result. The first and second voltages correspond to a first and second preset value, respectively. When the comparison result shows that the second voltage is greater than the first voltage, the preset value setting circuit outputs the second preset value; otherwise it outputs a third preset value, which is greater than the first preset value. The reset detecting circuit determines whether the operation voltage of the power supply circuit drops to the preset value outputted by the preset value setting circuit, and outputs a control signal accordingly. The reset signal generating circuit determines whether to output a reset signal for resetting gate lines in a display panel based on the control signal.

Abstract: Discussed are a built-in gate driver capable of improving output characteristics of the gate driver by reducing load of clock lines and a display device using the same. The built-in gate driver can include a shift register, a first clock group and a second clock group located in a non-display region of a display panel. The shift register includes a plurality of stages for individually driving gate lines of a display region. The first clock group includes clock lines arranged at a first side of the shift register. The second clock group includes clock lines arranged at a second side of the shift register. Each of the clock lines includes a main line and a branch line branched from the main line and connected to a corresponding stage. A branch line belonging to a corresponding clock group of any one of the first and second clock groups does not overlap a main line belonging to the other clock group.

Abstract: A display may have an array of display pixels. Digital display data may be received by a digital-to-analog converter that converts the digital display data to analog display data. The magnitudes of the analog display data signals can be controlled by a regulated voltage received by the digital-to-analog converter. A brightness controller may have multiple peak luminance control (PLC) profiles. In accordance with an embodiment, a brightness setting may be processed by a lookup table to identify a pair of PLC profiles that is interpolated in order to obtain the desired regulated voltage. In accordance with another embodiment, a single PLC profile may be used that is a function of a combined parameter that takes into account both average frame luminance and the brightness setting. In accordance with yet another embodiment, a lookup table that specifies brightness setting offset values may be used to directly modulate the brightness setting.

Abstract: A display panel control system and a display device are disclosed. The control system includes a system chip is configured for receiving video signals and for analyzing the video signals to obtain driving signals and timing signals, and a driving control board is configured for receiving the driving signals and the timing signals, and for controlling a display panel to display in accordance with the driving signals and the timing signals. The control system integrates the function of obtaining the driving signals and the timing signals on the system chip so as to simplify the structure of the display panel control system and to reduce the manufacturing cost.

Abstract: A liquid crystal display device includes: a display unit configured to pixels in a display region, a pixel drive circuit configured to apply voltage to liquid crystals, a memory configured to store therein a setting signal indicating whether to apply voltage to the liquid crystals in the display region, and two switch elements for switching coupling with the pixel drive circuit; and a controller configured to rewrite the setting signal stored in the memory when a mode in which the display unit is operated is switched, between a first mode causing the display unit to perform display output in accordance with a gradation signal generated based on image data, and a second mode causing the display unit to perform display output in accordance with the setting signal stored in the memory.

Abstract: The voltage transmission circuit includes: a multiplexer for transmitting positive and negative voltages ranging +VDD to ?VDD selectively; and a demultiplexer for receiving the positive and negative voltages and output them at positive and negative outputs. The voltage transmission circuit is arranged by use of elements each having a withstand voltage of which the absolute value is not 2|VDD|, but |VDD|. While transmitting positive voltages, the multiplexer is configured not to be applied by negative voltages, the multiplexer and demultiplexer are controlled by signals each having a potential of 0 V to +VDD, and the demultiplexer outputs the positive voltages at the positive output. While transmitting negative voltages, the multiplexer is configured not to be applied by positive voltages, the multiplexer and the demultiplexer are controlled by signals each having a potential of ?VDD to 0 V, and the demultiplexer outputs the negative voltages at the negative output.

Abstract: The invention provides an OLED display and a source driver. The output channels of source driver are divided into odd-numbered (ODD) and even-numbered (EVEN) output channels. With the odd-even channel selection module (33) in source driver to control the logic circuit and driver module (31) to select only odd-numbered (ODD), only even-numbered (EVEN) output channels or both for output based on strobe enabling signal (EN) and odd-even selection signal (SEL). Moreover, through rapid switching between high and low of the odd-even selection signal (SEL), the switching of outputting to only odd-numbered (ODD) and only even-numbered (EVEN) output channels is achieved so that odd-numbered pixel units and even-numbered pixel units in OLED display emit light alternatingly. Without changing pixel structure and reducing opening ration, while ensuring normal display, the invention shortens the light-emitting time of OLED inside each pixel to delay OLED display ageing.

Abstract: Provided is a control apparatus for an image pickup apparatus that can synchronize an image sensor with a frame period from an external device, such as a display apparatus, without use of any frame buffer, while optimizing the frequency of a clock signal used for the operation of the image sensor. An image sensor (11) receives a trigger signal from an external device (2), such as a display apparatus, and image data from an image sensor (11); calculates, for each frame, information of a time difference from the trigger signal to a time at which to start the output of the image data; and establishes, on the basis of the information of the time difference, a frame period of the image sensor (11) such that the time difference is accommodated within a given range, thereby allowing the image data to be supplied to the external device (2) within a given time difference relative to the trigger signal, though some degree of variation occurring in each frame.

Abstract: The control circuit includes a PCB and a timing control board having a first connection terminal, a switch, and an operation circuit. The first connection terminal is connected to a control terminal of the switch turning on and off the switch. An input terminal of the switch has a first voltage and an output terminal is connected to the operation circuit. The PCB includes sequentially positioned second, third, and fourth connection terminals. The third connection terminal has a voltage different from those on the second and fourth terminals. When the first connection terminal is connected to the third connection terminal, the switch is turned on, the output terminal has the first voltage, and the operation circuit is powered to function. When the first connection terminal is connected to the other connection terminals, the switch is turned off, the output terminal has zero voltage, and the operation circuit stops to function.

Abstract: A display device and a driving method thereof can reduce or prevent deterioration of image quality caused by ripples of a power voltage. A display device includes a gamma reference voltage generator generating a plurality of gamma reference voltages using a power voltage. A gamma selection signal generator generates a gamma selection signal corresponding to at least one gamma reference voltage among the gamma reference voltages and the power voltage. A gamma data supply unit stores a plurality of gamma data sets and outputs a gamma data set corresponding to the gamma selection signal from among the gamma data sets. A data driver generates a data signal using the gamma data set supplied from the gamma data supply unit and the gamma reference voltages. A display unit includes data lines transmitting the data signal.

Abstract: An integrated circuit device boosts an output voltage which is to be boosted based on the reference power supply voltage, based on another power supply voltage before the reference power supply voltage is supplied.

Abstract: Among data voltages applied to a plurality of pixels on a display panel, a first data voltage is shifted from a first original data voltage by a first value, a second data voltage is shifted from a second original data voltage by a second value, and a third data voltage is shifted from a third original data voltage by a third value to compensate for AC and DC afterimages. A common voltage generator provides an optimal common voltage for the third data voltage when the temperature of the liquid crystal panel assembly is lower than a reference temperature and provides an optimal common voltage for the first data voltage or the second data voltage when the temperature of the liquid crystal panel assembly is higher than or equal to the reference temperature. The first, second, and third values correspond to respective kickback voltages of the respective gray level data voltages.

Abstract: A liquid crystal display device in which pixels having a memory function are arranged includes: a display drive unit performing display driving by a driving method for obtaining halftone gray scales by setting plural frames as one cycle and temporarily changing gray scales of respective pixels within one cycle; and a pixel drive unit supplying a voltage having the same phase as, or the reverse phase to, a common voltage the polarity of which is inverted in a given cycle and applied to counter electrodes of liquid crystal capacitors to pixel electrodes of the liquid crystal capacitors. The pixel drive unit supplies an intermediate voltage between high- and low-voltage sides of the common voltage to the pixel electrodes of the liquid crystal capacitors at the time of transition from the supply of the voltage having the same phase to the supply of the voltage having reverse phase.

Abstract: An electro-optical device includes a first storage capacitor that has a first electrode and a second electrode, and a second storage capacitor that has a third electrode and a fourth electrode, and a first pixel circuit. The first pixel circuit includes a first transistor having a first gate, a first drain, and a first source, an electro-optical element, a second transistor through which a first data line is electrically connected to the first gate during the second transistor is in an on-state, and a third transistor through which the first gate is electrically connected to the first drain or the first source. The second electrode and the third electrode are electrically connected to the first data line.

Abstract: A pixel circuit includes a driving transistor, a switching transistor, and a light emitting element, and the light emitting elements are formed on a semiconductor substrate. A first substrate potential is supplied to the switching transistor, and a second substrate potential, different from the first substrate potential, is supplied to the driving transistor.

Abstract: A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels. The reference signal has a first logic level or a second logic level. The driving circuit also includes a switch circuit configured to receive the reference signal and an enable signal, and to provide the enable signal to the logic circuit when the reference signal is at the first logic level. A display apparatus may be provided that includes the driving circuit.

Abstract: A display device according to an embodiment includes a display panel, a driver, a power supply unit, and a power control unit. The power control unit may control the power supply unit in synchronization with a driving period of a device driving the display panel, and control one or more of synchronization signals of a scan driver, a data driver, and a timing controller and a switching frequency of a power generation transistor of the power supply unit to be synchronized.

Abstract: An LCD panel includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate is provided with a first electrode thereon. The first electrode is provided with a plurality of stripe-like control electrodes for controlling a viewing angle of the LCD panel. The second substrate is provided with a second electrode and a third electrode thereon. The second electrode is a common electrode for inputting a common voltage to the LCD panel. The third electrode is a pixel electrode formed in each pixel of the LCD panel. When no bias voltage is applied to the stripe-like control electrodes of the first electrode, the LCD panel is displayed with a wide viewing angle; and when a bias voltage is applied to the stripe-like control electrodes of the first electrode, the LCD panel is displayed with a narrow viewing angle.

Abstract: A source driver includes a buffer device including a plurality of buffers corresponding to a plurality of data lines, each of the plurality of buffers respectively including an amplifier configured to amplify an input signal and an output driver configured to output a driving signal to a corresponding data line among the plurality of data lines; and a switch device including a charge sharing switch configured to electrically connect the plurality of data lines to one another during a charge sharing operation, each of the amplifiers including a first current mirror having a reference current path including a first node and an output current path including a second node, and the first node of the reference current path and the second node of the output current path are electrically connected to each other during the charge sharing operation.

Abstract: A display apparatus includes a first substrate including a display area and a non-display area, a gate driver positioned in the non-display area of the first substrate and including a plurality of stages cascaded, and at least one spacer disposed on the gate driver, where each of the plurality of stages includes a transistor including a first electrode connected to a clock terminal to which a clock signal is input, a second electrode connected to an output terminal which outputs a gate signal, and a gate electrode, and a capacitor including a first capacitor electrode connected to the gate electrode of the transistor and a second capacitor electrode connected to the output terminal, and the at least one spacer is disposed on the capacitor.

Abstract: The invention discloses an array substrate and a driving method thereof, and a display device, and the array substrate includes: a common voltage generation unit, a timing control unit, a data voltage generation unit, a switch control unit and pixel units, wherein the switch control unit is connected to the common voltage generation unit, the timing control unit, the data voltage generation unit, the common voltage line and the data line, and the switch control unit is used to load a common voltage signal on the common voltage line and load a data voltage signal on the data line when a current frame of image is displayed, and load the common voltage signal on the data line and load the data voltage signal on the common voltage line when a next frame of image is displayed.

Abstract: A display system includes an array of light emitting diodes (LEDs), first and second driver chips, and one or more protection chips on a display substrate. The first and second driver chips are to drive a first group of LEDs of the array of LEDs and a second group of LEDs of the array of LEDs, respectively. Each protection chip includes one or more electro-static discharge (ESD) protection devices to assist with protecting the driver chips from damage caused by an ESD event. In one embodiment, each ESD protection device is connected between one or more signal lines, one or more power supply voltage lines, and an electrical ground line of the display substrate. In one embodiment, at least one protection chip comprises one or more electric overstress (EOS) protection devices to assist with protecting the driver chips from damage caused by an EOS event.

Abstract: A display apparatus includes a display panel, a timing controller and a data driver. The display panel includes a data line and first and second pixels connected to the data line. The timing controller generates a data signal and a data kickback control signal in response to input image data. The data driver generates first and second data voltages in response to the data signal, generates a data kickback signal in response to the data kickback control signal, processes the data voltages and the data kickback signal, and outputs the first data voltage to the data line during a first duration, the second data voltage to the data line during a second duration, and a first kickback data voltage to the data line during a first data kickback duration. The first data kickback duration is between the first and second durations.

Abstract: The present invention provides a liquid crystal display panel, comprising: a control terminal of the first main thin film transistor on the nth row of the pixels connected to a branch of the scanning lines to which the nth row of the pixels correspond; the control terminal of the second main thin film transistor on the nth row of the pixels connected to a first branch of the scanning line of the (n+1)th row; the control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels connected to a branch of the scanning lines of the (n+1)th row.

Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.

Abstract: Methods and systems of controlling an electronic device that executes at least one application include receiving a multipoint input; detecting input points of the multipoint input; and generating a layer for executing the at least one application based on the detected input points of the multipoint input.

Abstract: A gate driver on array (GOA) circuit and a display device are provided. The GOA circuit is formed on an array substrate, and has a plurality of GOA units. Each of the GOA units has a drive module, a pull-down module, a pull-down output module, and a pull-up output module, which has a forward and reverse scanning function and avoids providing a forward and reverse scanning control unit and receiving a signal of the forward and reverse scanning control unit by connecting a circuit input of a pull-down output module and a drive module.

Abstract: A distributed pulse-width modulation system includes an array of pulse-width modulation elements, each element including a digital memory for storing a multi-bit digital value and a drive circuit that drives an output device in response to the multi-bit digital value stored in the digital memory. A system controller includes a memory for storing a multi-bit digital value for each element and a communication circuit for communicating each multi-bit digital value to each corresponding pulse-width modulation element.

Abstract: A driving apparatus and a method for driving a display panel thereof are provided. The driving apparatus includes an output buffer, a switch, an adjusting circuit, a digital-to-analog converter and a code detecting unit. The output buffer provides an output voltage to a load according to a static current determining a speed of the output voltage reaching a target voltage for driving the load. The switch is coupled between the output buffer and the load in series, and is turned on or off according to a control signal. The code detecting unit detects an input code. The adjusting circuit determines whether the input code varies when the control signal is enabled, and disables a high driving ratio signal when the input code does not vary when the control signal is enabled. An enabling period of the high driving ratio signal is different from an enabling period of the control signal.

Abstract: A source driver circuit includes a receiver, a plurality of amplifying buffers, and a control logic circuit. The receiver receives a data signal and a control signal through an input terminal. Each of the amplifying buffers outputs a driving signal generated based on the image data signal through an output terminal. The control logic circuit controls the receiver and the plurality of amplifying buffers based on the control signal. When a power-down signal is provided to the receiver, the control logic circuit is to turn off at least one of the receiver and the plurality of amplifying buffers.

Abstract: The electrode member according to the embodiment includes: a substrate; and an electrode part on the substrate, wherein the electrode part includes a sensing electrode and a wire electrode, at least one electrode of the sensing electrode and the wire electrode includes an opening part and the electrode part has a black color.

Abstract: A liquid crystal display device includes: a first substrate; a second substrate positioned parallel to the first substrate; a liquid crystal layer between the first substrate and the second substrate. A black matrix disposed on one of the first substrate and the second substrate and configured to define a pixel region. A lower pixel electrode on the first substrate corresponding to the pixel region. An upper insulating layer disposed on the lower pixel electrode and having at least one groove. An upper pixel electrode disposed on the upper insulating layer and receiving a data signal from a thin film transistor, the data signal applied from a data line.