Abstract: A method of driving a display panel is disclosed. In one aspect, the display panel includes a plurality of pixels, each of the pixels including a first transistor connected to a first gate line and a pixel electrode and a second transistor connected to a second gate line and the pixel electrode. The method including alternately providing the first gate line with a gate signal and a reverse bias signal and alternately providing the second gate line with the gate signal when the first gate line is provided with the reverse bias signal and the reverse bias signal when the first gate line is provided with the gate signal.

Abstract: A first gate driver that drives a gate bus line corresponding to a first sub-pixel section and a second gate driver that drives a gate bus line corresponding to a second sub-pixel section are monolithically formed inside a panel. A shift register inside the second gate driver has a configuration where stages corresponding to respective rows and dummy stages each disposed for each row, are connected in series with one another. In such a configuration, a frequency of a clock signal for controlling an operation of the second gate driver is made twice as large as a frequency of a clock signal for controlling an operation of the first gate driver.

Abstract: According to one embodiment of the present invention, a timing controller for a display, includes a first unit, a second unit and a third unit. The first unit is configured to generate an image signal from a first input signal. The second unit is configured to generate a multitude of timing signals and a control signal from a multitude of second input signals, the control signal being generated after the multitude of timing signals are generated. The third unit is configured to generate a multitude of first signals from the multitude of timing signals after receipt of the control signal from the second unit. The image signal and the multitude of first signals are configured to drive the display when the timing controller is connected to the display.

Abstract: In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors T6A, T6B are connected between the output terminal OUT and AC power sources VA, VB. At least one of T6A, T6B is brought into ON state and T6A, T6B are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where T6A, T6B are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where T6A, T6B are in OFF state.

Abstract: A flat display device includes a flat panel including a plurality of gate lines; a first gate driving portion connected to odd gate lines among the plurality of gate lines; a second gate driving portion connected to even gate lines among the plurality of gate lines; a driving mode selection portion generating a driving mode signal corresponding to source output inputted thereto; and a timing control portion operating in a moving image mode or a still image mode in response to the driving mode signal, wherein the first and second gate driving portions alternately operate per a frame in the still image mode, or wherein the first and second gate driving portions alternately operate per a field in the moving image mode, in which the field is shorter than the frame.

Abstract: A display apparatus, an integrated circuit and method thereof are disclosed. The display apparatus includes a frame buffer, a controller circuit, and a display driver circuit. The frame buffer is configured to retain a plurality of image frames to be displayed. The controller circuit, coupled to the frame buffer, is configured to determine whether a change in the image frames has occurred and whether a refresh time is expired. The display driver circuit, operatively coupled to the frame buffer and adapted to couple to an active display device, is configured to receive the image frames to be displayed from the frame buffer and dynamically refreshing the active display device when the change is determined or when a refresh time is expired.

Abstract: A liquid crystal display device including a liquid crystal panel, a gate driver configured to supply gate signals to gate lines on the liquid crystal panel, a data driver configured to supply data voltages to data lines on the liquid crystal panel, and a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines.

Abstract: A driving circuit with a feed through voltage compensation includes multiple gate scanning lines, multiple storage capacitance lines and multiple stages of common driving units. The common driving unit includes a gate driver and a storage capacitance driver, where the gate driver is connected to a gate scanning line to output a gate scanning signal, and the storage capacitance driver is connected to a storage capacitance line to output a storage capacitance signal. The storage capacitance signal outputted from the storage capacitance driver is adapted to compensate the gate scanning signal output from the gate driver. The driving circuit with the feed through voltage compensation allows a large gate-to-drain parasitic capacitance of the pixel, and the width of the black matrix may become smaller; therefore the pixel aperture ratio may be increased, the cost may be reduced, or the power consumption may be reduced.

Abstract: A shift register for reducing size of a display apparatus through a reduction in falling edge time of a scan pulse. The shift register includes stages for sequentially outputting carry pulses and scan pulses. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage with a level substantially equal to the first discharge voltage, and supplying the carry pulse to at least one of an upstream stage and a downstream stage, a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage value than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line, and a node controller for controlling voltages at nodes connected to the carry output unit and the scan output unit.

Abstract: A display panel driving apparatus includes an image pattern analyzing part, a clock signal generating part and a data driving part. The image pattern analyzing part is configured to analyze an image pattern of an image data. The clock signal generating part is configured to generating a clock signal having a different pulse width according to the image pattern of an image data. The data driving part is configured to drive a data line of a display panel in response to the clock signal. Thus, power consumption and heating of the data driving part may be decreased.

Abstract: A display device includes display panel includes a first source driver including a first input terminal and a first output terminal connected to the display panel; a first gate driver including a first input-output terminal, a second input-output terminal connected to the first input-output terminal, and a second output terminal connected to the display panel; a timing controller including a first terminal for outputting or inputting a first signal to or from the first input-output terminal and a second terminal; a first signal line connected to the first terminal; a second signal line connected to the second terminal; and a third signal line connected to the first source driver and the timing controller for transmitting a second signal indicating a display direction of the image data. The first source driver operates according to the first signal from the first terminal or the second terminal selected.

Abstract: The present invention provides a drive IC, a display device and a loading method that enable signals of different differential formats to be loaded without resulting in circuit redundancy. Namely, a drive IC includes an input section, a holding section, a selection section, and an output section. The input section includes a first input circuit and a second input circuit. When data of RSDS format is loaded, a selection section selects for output to the output section data held in a holding section, that temporarily stores data output from the input section. When mini-LVDS format data is loaded, the selection section selects the data output from the input section for output to the output section. When the mini-LVDS data is loaded, a switch switches the output destination of the output section, such that data is rearranged in the desired sequence and externally output.

Abstract: A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: An electronic apparatus system is provided. The electronic apparatus system includes a register, a display mode computation unit, a display device and a control circuit. The register stores image information having a data input refresh frequency. The display mode computation unit generates a display mode control signal by computation based on an image characteristic categorization of the image information. The display device includes a display panel having a plurality of pixel units. The control circuit controls a display mode and a drive mode of the display panel according to the display mode control signal to further adjust a display refresh frequency of the display panel.

Abstract: A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.

Abstract: Systems, methods, and devices are disclosed, including a device having a liquid-crystal display (LCD) panel that includes a transistor-degradation circuit. In some embodiments, the transistor-degradation circuit is configured to output a signal indicative of a change in a property of a transistor on the LCD panel over time.

Abstract: Aspects of the present invention relate to a display device, a timing controller, and an image display method. When a frame of an input image signal including an odd-field signal and an even-field signal is received, a timing controller outputs a gate scanning clock (GCK) signal and an output enable (OE) signal in an interlaced scanning manner, to separately scan the odd-field image and the even-field image in the interlaced scanning manner in real time. The interlaced scanning manner is used for the interlaced signal, thereby saving a storage equipped in a converter.

Abstract: A liquid crystal display (LCD) and method of driving the same are disclosed. In one aspect, the LCD includes a display panel that includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels each electrically connected to a corresponding gate line and a corresponding data line. The LCD also includes a timing controller that receives present frame data, stores previous frame data, and outputs first line data of the previous frame data and a data driver that converts the first line data to a first previous line data voltage and applies the first previous line data voltage to the data lines during a portion of a vertical blank period between a present frame and a previous frame.

Abstract: Disclosed herein is a display apparatus, including: a display pixel section including a plurality of pixels each including a plurality of subpixels arrayed in a two-dimensional lattice pattern; a plurality of pixel switches for individually driving the plural subpixels; and a plurality of scanning lines to each of which a pair of pixel switch groups each including a series of ones of the pixel switches arrayed along one of the two-dimensional directions of the pixel switches are connected; the pair of pixel switch groups being arranged in an opposing relationship to each other with the scanning line interposed.

Abstract: Aspects of the present invention relate to methods and systems for controlling power consumption with a power controlling display device. Some aspects relate to a power controlling display device that receives a notification of a power control event that may control internal display components as well as connected power consuming devices. Some aspects relate to methods and systems for automatically compensating a displayed image when display backlight levels are modified in response to a power control event.

Abstract: Each of image-signal-line drive circuits includes a timing controller that generates a control signal controlling itself and other image-signal-line drive circuit, and a master/slave selection circuit that sets itself as a master mode image-signal-line drive circuit or a slave mode image-signal-line drive circuit based on a selection signal to be given from outside. From among the plurality of image-signal-line drive circuits, the master mode image-signal-line drive circuit gives the control signal to the slave mode image-signal-line drive circuit.

Abstract: According to one embodiment, a circuit includes: a synchronous driver configured to generate a control signal in synchronization with an output pulse of an AC/DC converter; and an LED current controller configured to start to control a current of an LED in response to the control signal, and configured to output a stop signal for stopping the control signal when a predetermined LED current is detected; wherein the synchronous driver is caused to stop the control signal by the stop signal.

Abstract: A system performs a method for detecting display driver error. The method includes sending a first command signal to a display driver to operate according to a first operating state that includes the display driver sending a synchronization signal, and monitoring for the synchronization signal during a first time period after sending the first command signal. The method further includes sending a second command signal to the display driver to operate according to a second operating state that includes the display driver withholding sending the synchronization signal, and monitoring for the synchronization signal during a second time period after sending the second command signal. In addition, the method includes detecting a display driver error based on results of the monitoring during at least one of the first or the second time periods.

Abstract: A display device includes first transistors provided for every scanning line and second transistors having a first electrode connected to each scanning line and a second electrode to which a reference potential is inputted. A first electrode of the first transistor is connected to any one of gate lines belonging to a first group. A control electrode of the first transistor is connected to any one of gate lines belonging to a second group. A control electrode of the second transistor is connected to any one of reverse gate lines belonging to a second group. A scanning line drive circuit intermittently outputs, when the scanning line drive circuit outputs a non-selective scanning voltage to any one of the gate lines belonging to the second group, a selective reversal scanning voltage to a reverse gate line corresponding to the gate line in the reverse gate lines belonging to the second group.

Abstract: A display device including a display panel displaying a still image and a moving image and a signal controller controlling signals to drive the display panel, wherein the signal controller includes a frame memory storing image data of the still image and providing the image data to the display panel, and the display panel is driven with a first scan ratio when displaying the moving image and is driven with a second scan ratio that is lower than the first scan ratio when displaying the still image.

Abstract: Provided are a display device and a method for driving the same. The display device includes: a plurality of display modules; a plurality of display module drivers for respectively driving the display modules; a data divider receiving data signals for displaying an image on the display device and separating the received data signals into output data signals corresponding to each respective display module driver; and a timing control signal generator for generating a timing control signal to be supplied commonly to the display module drivers.

Abstract: A liquid crystal display includes a substrate, a plurality of signal lines, a gate driver, and a sealant. The substrate includes a display area and a peripheral area outside the display area. The signal lines are integrated with the substrate and include a clock signal line. The gate driver includes a stage located between the clock signal line and the display area. The stage is integrated with the substrate and is configured to apply a gate voltage to the display area. The sealant is distributed over part of the peripheral area. A seal region where the sealant is distributed includes a seal line, and the clock signal line is located within the seal line. The clock signal line is located further away from the stage than the other signal lines.

Abstract: An electro-optic device includes an electro-optical panel and a polarization axis conversion unit that emits transmission lights corresponding to a first image or a second image with the polarization axis of the first image intersecting the polarization axis of the second image, by converting the polarization axis of the lights emitted from the electro-optical panel. The electro-optic device further includes a scanning signal supply unit supplying scanning signals through the plurality of scanning lines and an image signal supply unit supplying a first image signal corresponding to a first image to the plurality of pixel sections during a first field period and supplying a second image signal corresponding to a second image to the plurality of pixel sections during a second field period through the plurality of data lines, the first field period and the second field period being divided into a plurality of subfield periods respectively.

Abstract: A field-sequential display is operated in one of a color mode or a grayscale mode. In the color mode, a video source provides image content in the form of multiple-color image data having a frame rate of X Hz and a display controller uses the multiple-color image data to drive the field-sequential display so as provide multiple-color image content at the field-sequential display. In the grayscale mode, the display controller generates grayscale image data from the multiple-color image data and the display controller then drives the field-sequential display with the grayscale image data at a lower frame rate of Y Hz. While in the grayscale mode, the display controller can take advantage of the enhanced contrast provided by the grayscale image content to reduce or disable backlighting at the field-sequential display. The reduced timing requirements afforded by the lower frame rate, as well as the reduction or elimination of backlighting, can reduce power consumption compared to the color mode.

Abstract: An imaging device includes a pixel section and an amplification unit which amplifies the signal of the pixel section. The amplification unit includes an input capacitor having first and second nodes, an amplification circuit, a first feedback capacitor connected between the input capacitor and an output portion of the amplification circuit, a first MOS transistor switch connected in series with the first feedback capacitor, a second MOS transistor switch which is connected in series with the first feedback capacitor, and has a drain and a source connected to each other, a second feedback capacitor connected between the input capacitor and the output portion, a third MOS transistor switch connected in series with the second feedback capacitor, and a fourth MOS transistor switch which is connected in series with the second feedback capacitor, and has a drain and a source connected to each other.

Abstract: A gate shift register and a display device using the same are disclosed. The gate shift register includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output a scan pulse. A k-th stage of the plurality of stages includes a scan direction controller for converting a shift direction of the scan pulse in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller for controlling charging and discharge operations of each of Q1, Q2, QB1, and QB2 nodes, a floating prevention unit for applying a low potential voltage to a gate electrode of a discharge TFT based on a voltage of the QB1 node or the QB2 node, and an output unit for outputting first and second scan pulses.

Abstract: A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data.

Abstract: A liquid crystal display device and a driving method thereof capable of simplifying of a hardware construction of the liquid crystal display device driven by the impulsive driving method and minimizing capacitance of memory for storing data are provided.

Abstract: In a bi-directional shift register and a liquid crystal display device having the bi-directional shift register, the shift register further includes a dummy stage for resetting a last stage. The dummy stage is reset by a control signal of the last stage or by the output signal of the dummy stage. Therefore, power consumption and layout area may be reduced. The shift register includes a plurality of stages and two dummy stages, and two selection signals for selecting shift direction is applied to each of the stages.

Abstract: A display device according to an embodiment comprises: a display panel; a data driver that supplies a data signal to the display panel; a gate driver that supplies a gate signal to the display panel; and a timing driver that controls the data driver and the gate driver and comprises a voltage controlled oscillator of which frequency is varied according to a control signal generated in the timing driver.

Abstract: A scan driver may include: a first scan driving block, outputting a second clock signal to a first output terminal according to an input signal, in synchronization with a first clock signal; and a second scan driving block, outputting the first clock signal according to the output signal of the first scan driving block to a second output terminal, in synchronization with the second clock signal, wherein the first scan driving block and the second scan driving block simultaneously output an entire clock signal, according to a level of a simultaneous light emission control signal.

Abstract: A controller or control method may be designed or configured to operate without information about the current temperature of the device and/or the device's environment. Further, in some cases, the controller or control method is designed or configured to control transition of an optical device to an intermediated state between two end states. For example, the controller may be configured to control a transition to a state of transmissivity that is intermediate between two end states of transmissivity. In such case, the device has three or more stable states of transmissivity.

Abstract: Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged.

Abstract: A driving circuit for a display device, for reducing power consumption of a data driver, and a method of driving the driving circuit are disclosed. The driving circuit includes a data driver for maintaining buffers of the data driver in an on state every preset specific frame period and maintaining the buffers in an off state every remaining period except for specific frame periods in a refresh mode for processing image data of one image for the specific frame periods only.

Abstract: A timing controller and a Liquid Crystal Display (LCD) using the same are discussed. The timing controller according to an embodiment includes a reception unit which receives a video signal and a timing signal from a system; a control signal generation unit which generates a gate control signal and a data control signal with the timing signal, and outputs the gate control signal and the data control signal to a gate driver and a data driver, respectively; an image signal generation unit which realigns the video signal to output a realigned image signal; and a delay compensation unit which performs delay compensation for the realigned image signal with a circuit recombined according to a delay compensation value between each data drive Integrated Chip (IC) of the data driver and the image signal generation unit, and outputs the delay-compensated image signal to each data drive IC.

Abstract: A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14).

Abstract: A liquid crystal display apparatus includes a liquid crystal panel and a panel driving device. The panel driving device includes a timing control circuit, a gate driving circuit, and a source driving circuit. The source driving circuit includes a low voltage differential signal (LVDS) receiver, a driving voltage generator, and a controller. The LVDS receiver includes a plurality of receive circuits and a power saving control circuit. Each of the receive circuit performs level conversion upon a data LVDS to generate a logic signal, and operates in a selected one of a normal energy consuming mode and a power saving mode. The power saving control circuit controls the receive circuits to operate in the power saving mode when the power saving control circuit does not receive a power adjustment signal from the controller.

Abstract: Disclosed are a timing controller and an OLED display device using the same. The timing controller includes a reception unit, an image signal generation unit, and a control signal generation unit. The reception unit receives a plurality of video signals and a timing signal which are transferred from a system. The image signal generation unit realigns the video signals to generate a plurality of image signals. The control signal generation unit analyzes the video signals to determine whether a current input image is a static image or a moving image, and generates a plurality of control signals according to the determined result. When the current input image is determined as the static image, the control signal generation unit generates a plurality of control signals which allow a panel to be driven at a change frame driving frequency lower than a reference frame driving frequency necessary for driving the moving image.

Abstract: The present invention aims to provide a driving control circuit of a display device, which includes a plurality of data driving circuits each having a timing controller merged with a source driver. The data driving circuits are configured to synchronize data of the respective data driving circuits and compensate for a difference between a data enable signal and a gate output enable signal, when an abnormal display signal is received.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A LCD panel in which a pixel has a first sub-pixel area and a second sub-pixel area, each area having a storage capacitor. Each pixel has a first gate line for providing a first gate-line signal for charging the first and second storage capacitors, and a second gate line for providing a second gate-line signal for removing part of the charges in the second storage capacitor to a third capacitor after the first gate-line signal has passed. The width of the first and second gate-line signals and their timing can be varied so that the first gate-line signal provided to a row can be used as the second gate-line signal to one of the preceding rows. In some embodiments, a pixel in each row has a duplicate pixel arranged to similarly receive the first and second gate-line signals, but data signals are received from different data lines.

Abstract: According to an aspect, a display device includes: a display section that has a first period to consume predetermined power and a second period to consume less power than in the first period, and power consumption of which periodically changes by repeating the first period and the second period; a smoothing capacitor that stabilizes power supplied to the display section; and a power consumption unit that consumes the supplied power in the second period.

Abstract: A display, a pixel circuitry and an operating method of the pixel circuitry are provided. The display includes a source driver and a pixel circuitry. The source driver converts a first pixel data to a first polarity data voltage and a second polarity data voltage during a first frame period and converts a second pixel data to a third polarity data voltage and a fourth polarity data voltage during a second frame period. The pixel circuitry is coupled to the source driver. The pixel circuitry stores the first polarity data voltage and the second polarity data voltage during the first frame period, displays the first polarity data voltage and the second polarity data voltage during a first sub-period and a second sub-period of the second frame period respectively, and stores the third polarity data voltage and the fourth polarity data voltage during the second frame period.

Abstract: A liquid crystal display device and a method for driving the same are disclosed. The liquid crystal display device includes a liquid crystal panel, a gate driver unit, a clock generator, and a temperature compensation unit. The liquid crystal panel includes a pixel array. The gate driver unit is utilized for generating a plurality of driving signals to drive the pixel unit. The clock generator is electrically coupled to the gate driver unit. The temperature compensation unit is electrically coupled to the gate driver unit and the clock generator. The temperature compensation unit is utilized for adjusting an output of the clock generator to compensate the driving signals of the gate driver unit according to a temperature variance.