Abstract: A data driver includes buffers, bias circuits, and a bias signal generator. The buffers respectively output data voltages corresponding to pixel image data. The bias circuits generate bias currents independent of each other and apply the bias currents to respective ones of the buffers. The bias signal generator generates a plurality of bias signals. Each of the bias circuits include a selector and a bias current generator. The selector selects one bias signal among the bias signals based on corresponding pixel image data and outputs the selected bias signal as a final bias signal. The bias current generator generates a corresponding bias current among the bias currents based on the final bias signal.

Abstract: The present disclosure discloses a programmable Gamma voltage output device having a non-volatile memory (NVM), a controller, a digital signal generation module, a digital to analog converter (DAC), and output verification module. The NVM is configured for duplicating a copy of a corresponding voltage data code when programming the voltage data code. The controller is configured for sending control signals to the digital signal generation module in accordance with the voltage data code. The digital signal generation module is configured for outputting digital signals to the DAC in accordance with the control signals. The DAC is configured for converting the digital signals to a Gamma voltage. The output verification module is configured for verifying whether the Gamma voltage is within a predetermined voltage range. In addition, a display device is also disclosed.

Abstract: An A liquid-crystal adaptive optics actuator comprising a two-dimensional array of pixels (14), wherein each pixel (14) is connected to a control circuit by means of a control line signal path (16, 20) that comprises an electrical interconnection (16) and a meandering resistor (20), each resistor having a resistance value selected to equalize the RC time constant of each control line signal path associated to each pixel. Each control line is thus capable of carrying one or more control signals and the control line signal path is configured such that all the pixels respond to the control signals with a uniform response time.

Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: An electro-phoretic display and a method for driving the same are provided, where the electro-phoretic display has a plurality of pixel units. The method includes: setting a plurality of particle tightening time periods and a plurality of gray level displaying time periods for the pixel units respectively, where each of the gray level displaying time periods is arranged after each corresponding particle tightening time period; providing a plurality of particle tightening voltages to the pixel units for tightening the particles of the pixel units respectively during the particle tightening time periods, and providing a plurality of display driving voltages to the pixel units during the gray level displaying time periods. The particle tightening time periods and/or the gray level displaying time periods are determined by a plurality of display gray level data corresponding to the pixel units.

Abstract: To reduce the occurrence of flicker in an image with almost no movement and reduce the occurrence motion blur in an image with movement, an image processing apparatus detects movement information from acquired image data. The image processing apparatus causes a display unit to perform first light emission to display a first frame, and also causes the display unit to perform second light emission to display a second frame, the first frame and the second frame corresponding to one frame of the acquired image data. The image processing apparatus controls at least either light emission time periods of the first light emission and the second light emission or light emission luminances of the first light emission and the second light emission based on the movement information.

Abstract: A method for efficient data input may include displaying a user interface, detecting a plurality of positions of an object, and, controlling a display screen to display a data content, in response to a plurality of movements of the object. If the controller determines the object moved substantially in a first direction, the display screen modifies the data content based on a group of data choices. If the controller determines the object moved substantially in a second direction, the controller stores, into a memory, the data content currently being displayed on the display screen.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: A Light-Emitting Diode (LED) driving circuit and a control system includes: a driving control circuit and a constant current channel group circuit, wherein the driving control circuit includes: a logic control circuit and a clock delay circuit; the logic control circuit is connected with the constant current channel group circuit, and is configured to control the ordered switching-on or switching-off of the constant current channel group circuit by virtue of a data control signal; and the clock delay circuit is connected with the logic control circuit, configured to acquire a timing control signal synchronous with the data control signal and output the timing control signal and integrated in the LED driving circuit.

Abstract: A display apparatus includes a display panel having a first portion and a second portion, a gate driver configured to drive a first gate line group in the first portion of the display panel starting at a first scan start point and to drive a second gate line group in the second portion of the display panel starting at a second scan start point, the second scan start point being different from the first scan start point, a first data driver configured to output a first data voltage to a first data line group in the first portion and a second data driver configured to output a second data voltage to a second data line group in the second portion.

Abstract: A timing controller, OLED display having the same and method of for driving the display are disclosed. The timing controller includes a failure mode determiner that can receive an input signal and determine whether the OLED display is in a failure mode based on the input signal. The timing controller also includes a failure mode generator configured to store a fail signal, output the fail signal in the failure mode, and selectively output a multiplexed signal including one of the input signal or the fail signal based on whether the OLED display is in the failure mode. The timing controller further includes a failure mode controller configured to receive the multiplexed signal from the failure mode generator, store the multiplexed signal, and selectively output the multiplexed signal of a current frame or the multiplexed signal of a previous frame based on whether the OLED display is in the failure mode.

Abstract: A data driver includes buffers respectively outputting data voltages corresponding to pixel image data, bias units corresponding to the buffers in a one-to-one correspondence and driving the buffers, respectively, and a global setting part applying control level values to the bias units. Each of the bias units includes a bias signal generating unit that selects one control level value among the control level values based on a corresponding pixel image data among the pixel image data and generates a bias signal having a control level corresponding to the selected control level value and a current generating unit that generates a corresponding bias current in response to the bias signal and applies the corresponding bias current to a corresponding buffer among the buffers.

Abstract: The disclosure relates to a method for controlling signal values on gate lines, a gate driving circuit and a display device. The method comprises: for each of gate lines in the valid display area, in a first frame in any two adjacent frames of image, connecting a gate connecting line in a first layer to a gate line by a first strobe unit and applying a first signal value to the gate line; in a second frame, connecting a gate connecting line in a second layer to the gate line by a second strobe unit and applying a second signal value to the gate line. It may address the issue of H-line Mura due to different impedances of wires in the gate layer and the S/D layer.

Abstract: A liquid crystal display includes: a liquid crystal capacitor; a first switching element which transmits a data voltage to the liquid crystal capacitor; a second switching element connected to the liquid crystal capacitor; and a transformation capacitor connected to the second switching element. A difference between a first time when the first switching element is turned on and a second time when the second switching element starts is turned on is greater than 1 horizontal period and less than 1 frame period.

Abstract: The present disclosure provides an array substrate, which includes a flexible substrate and an array layer formed on the flexible substrate. The array layer includes: data lines, gate lines, thin film transistors and a driving unit. The driving unit is configured to output data driving signals to connected data lines. The data lines includes a first data line connected to thin film transistors of a first number and a second data line connected to thin film transistors of a second number. The number of sub-signals in a data driving signal outputted to the first data line by the driving unit within a time period of one frame is the first number. The number of sub-signals in a data driving signal outputted to the second data line by the driving unit within a time period of one frame is the second number.

Abstract: Disclosed herein is a display device including: a display section configured to have a plurality of scanning signal lines to which respective scanning signals are applied, the display section performing line-sequential scanning by repeating interruption and resumption of the line-sequential scanning on a basis of the plurality of scanning signals, and displaying an image; and a scanning section configured to generate the plurality of scanning signals such that transition times on a pulse termination side of the respective scanning signals are equal to each other.

Abstract: An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.

Abstract: A liquid crystal display device capable of consuming less power and a method for driving the liquid crystal display device are provided. The liquid crystal display device includes a pixel portion, a light supply portion sequentially supplying lights of a plurality of hues to the pixel portion, a counter counting the number of frame periods, a signal generator determining timing of inverting the polarity of an image signal every plural consecutive frame periods by using data on the number of frame periods counted by the counter, and a controller inverting the polarity of the image signal in accordance with the timing. A plurality of pixels are provided in the pixel portion. The image signal whose polarity is inverted every plural frame periods is input to the plurality of pixels.

Abstract: There is provided a liquid crystal display apparatus capable of preventing image degradation when driving a liquid crystal panel. In the liquid crystal display apparatus, a control unit, when there are more pixels indicating the first gradation than the second gradation, controls the supply state of the pixel voltage simultaneously supplied to the plurality of pixel electrodes to prolong the time period between the timing of changing the supply state of the pixel voltage corresponding to the first gradation and the timing of changing the supply state of the pixel voltage corresponding to the second gradation so as to become longer than that when there are fewer pixels indicating the first gradation than the second gradation.

Abstract: A gate driver is disclosed. The disclosed gate driver includes a shift register configured to generate a shift signal. The shift signal is based on a gate start signal and a gate clock signal. The gate driver further includes a gate drive signal generator configured to generate a gate drive signal. The gate drive signal is based on a gate control signal and the shift signal. The rising edge of the gate control signal precedes the falling edge of the shift signal, and the falling edge of the gate control signal follows the falling edge of the shift signal. The gate drive signal falls from a second voltage to a third voltage in response to the falling edge of the shift signal and rises from the third voltage to a first voltage in response to the falling edge of the gate control signal. The first voltage is higher than the third voltage but lower than the second voltage.

Abstract: In one or more example embodiments, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.

Abstract: Systems and methods for efficiently generating display driver timing signals are provided. In one example, display driver circuitry of an electronic display may provide a negative voltage from a negative voltage supply to display control circuitry during a first period and may provide a positive voltage from a positive voltage supply to the display control circuitry during a second period. After providing the negative voltage during the first period but before providing the positive voltage during the second period, the display driver circuitry may precharge the capacitance of the display control circuitry to ground. In this way, the positive voltage supply substantially does not supply charge to raise the voltage on the capacitance of the display control circuitry from the negative voltage to ground.

Abstract: A driving apparatus applied in a liquid crystal display is disclosed. The driving apparatus at least includes a first latch, a second latch, an output buffer, and a slew rate enhancing module. The first latch is used to store a second data signal. The second latch is used to store a first data signal. The first data signal is previous to the second data signal. The slew rate enhancing module is used to compare the first data signal and the second data signal to generate a compared result, and correspondingly output a control signal to the output buffer according to the compared result to control a driving current of the output buffer.

Abstract: A thin film transistor includes a semiconductor pattern on a base substrate, the semiconductor pattern including an input area, an output area, and a channel area between the input area and the output area, a first insulating layer covering the semiconductor pattern, a control electrode on the first insulating layer, the control electrode overlapping the channel area, a second insulating layer covering the control electrode, an input electrode connected to the input area, an output electrode connected to the output area, and a heat discharge electrode on the second insulating layer, the heat discharge electrode being connected to the control electrode.

Abstract: An object of the present invention is to, in an organic EL display device in which an initialization voltage is applied, extend the time period usable to write a video voltage as compared with the conventional art. In order to achieve this object, the organic EL display device includes a plurality of pixels each including an organic EL element; a plurality of video lines that supply a video voltage to each of the plurality of pixels; a plurality of scanning lines that supply a scanning voltage to each of the plurality of pixels; a unit that supplies a selection scanning voltage concurrently to an N number of scanning lines among the plurality of scanning lines, and supplies an initialization voltage to each of the plurality of video lines, in a k'th scanning period; and a unit that supplies a selection scanning voltage sequentially to the N number of scanning lines, and supplies video voltages to each of the plurality of video lines, in (k+1)th through (k+N)th scanning periods respectively.

Abstract: A control board in a display device includes terminals and a control circuit. The control circuit is configured to output a control signal an image signal through the terminals and to generate a drive voltage in response to a feedback signal, which is fed back to a second terminal of the terminals when a source voltage is applied to a first terminal of the terminals.

Abstract: A source driving circuit includes an output buffer circuit to compensate for slew rate of signals used to drive a display device. The output buffer circuit includes a bias current control signal generating circuit and a channel amplifying circuit. The bias current control signal generating circuit performs an exclusive OR operation on an input signal and an output signal of a reference operational amplifier to generate a bias current control signal. The channel amplifying circuit adjusts the slew rate of a plurality of output voltage signals in response to the bias current control signal. The output signals are then used to control the display device.

Abstract: A LCD display includes a light source section, a LCD panel including a plurality of pixels each having sub-pixels of R, G, B, and Z, and a display control section including an output signal generation section. The display control section performs a display drive on the sub-pixels with use of the respective output video signals, and performs a lighting drive on the light source section with use of the lighting signal. The output signal generation section generates output video signals corresponding to the respective four colors, based on the input video signals, and generates a lighting signal of the light source section, based on the input video signals, to perform a predetermined dimming processing, based on both the input video signals and the generated lighting signal, and finally generates the output video signals through performing a predetermined color conversion processing, based on a resultant video signal from the dimming processing.

Abstract: There is provided an organic light emitting display device capable of reducing power consumption by adjusting a voltage according to an input image and deterioration of the organic light emitting display device and a method of driving the same.

Abstract: A liquid crystal display comprises: a first data drive circuit that supplies a data voltage to data lines present in a first portion and a third portion on the screen of a liquid crystal display panel in response to a first source output enable signal; and a second data drive circuit that supplies the data voltage to data lines present in a second portion and a fourth portion on the screen of the liquid crystal display panel in response to a second source output enable signal. The first source output enable signal controls the data voltage output timing and charge sharing timing of the first data drive circuit. The second source output signal controls the data output timing and charge sharing timing of the second data drive circuit in a different way from the first data drive circuit.

Abstract: A highly reliable semiconductor device that includes a transistor including an oxide semiconductor, which can display a high-definition image and can be manufactured with a high yield. The semiconductor device includes a pixel portion including a plurality of pixels, a gate signal line driver circuit portion, and a source signal line driver circuit portion including a first circuit that controls timing of sampling video signals and a second circuit that samples the video signals in accordance with the timing and then inputs the sampled video signals to the pixels. The second circuit includes a plurality of transistors in each of which an oxide semiconductor stacked layer is used as a channel formation region, the first circuit and the second circuit are electrically connected to each other by a wiring, and the wiring is electrically connected to gates of at least two transistors of the plurality of transistors.

Abstract: A dual-gate-driven lateral pixel arrangement structure includes two horizontally adjacent primary pixel regions having each three vertically adjacent secondary pixel regions forming a grid of six secondary pixel regions, and six thin-film transistors disposed in each of the six secondary pixel areas. The structure also includes two gate lines and three data lines crossing each other and electrically isolated from each other. Each data line is connected to the source of two thin-film transistors having the gate connected to a different gate line. The two gate lines are interposed between the three secondary pixel regions or arranged along a side or opposite sides of the primary pixel regions in a first direction. The three data lines are arranged between the primary pixel regions and along a side or opposite sides of the primary pixel regions in a second direction different from the first direction.

Abstract: In a 3D image display device and a driving method thereof, a left-eye image and a right-eye image are displayed at a 3D display frequency higher than a 2D display frequency in a 3D mode. The left-eye image or the right-eye image is applied to a data line as data voltages having the same polarity and the same magnitude throughout at least two consecutive frames. A gate-on voltage is applied to a plurality of gate lines crossing the data line sequentially at an interval of a compensation gate-on application time calculated based on a total data delay value.

Abstract: An image processing unit including an always on circuit block and a non-always on circuit block is provided. When operating under a first operation mode, the non-always on circuit block receives a bias voltage from a power supply unit, so as to perform an image processing operation on an image input signal. When operating under a second operation mode, the non-always on circuit block stops receiving the bias voltage from the power supply unit, so as to stop the image processing operation, and at least a microcontroller of the non-always on circuit block is powered down. One of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying the bias voltage to the non-always on circuit block according an event trigger signal, such that the non-always on circuit block enters the second operation mode from the first operation mode.

Abstract: A driving circuit includes at least one output end, at least one driving voltage module, and at least one signal module. The output end receives and outputs an analog voltage. The at least one driving voltage module is connected with the at least one output end and generates a driving voltage, wherein the driving voltage module determines a voltage value of an output voltage according to a relation between an analog voltage and the driving voltage and transmits the output voltage to the at least one output end. The at least one signal module is connected with the at least one output end and outputs an analog data according to the analog voltage, wherein the at least one driving voltage module stores a residual voltage of the at least one signal module when the at least one signal module converts the analog voltage and the analog voltage is larger than the driving voltage.

Abstract: An image display device includes a display element selectively implementing a 2D image and a 3D image and a patterned retarder. The display element includes a pixel array including a plurality of subpixels, which are respectively formed at crossings of column lines and row lines. The patterned retarder includes a plurality of first retarders, each of which transmits light from the display element as a first polarization component, and a plurality of second retarders, each of which transmits the light from the display element as a second polarization component. The first retarders and the second retarders are alternatively arranged.

Abstract: A method for reducing double images of a frame is disclosed. The frame is divided into a plurality of regions. The method includes generating a plurality of output enable (OE) signals, which are utilized to respectively adjust a plurality of conduction durations of a plurality of gate lines of the corresponding regions. The OE signals are outputted to a gate driver for generating a plurality of scan signals of the corresponding regions. The gate lines, which correspond to the regions, are driven by the gate driver according to the scan signals.

Abstract: A method of generating image compensation data for a display device includes concurrently measuring, by a first image compensation device, first luminance values and first color coordinate values from an image displayed at a display panel in the display device, a number of the first color coordinate values being less than a number of the first luminance values; concurrently generating first luminance data and first color coordinate data associated with the image based on the first luminance values and the first color coordinate values, respectively; and generating first image compensation data for compensating the image based on the first luminance data, the first color coordinate data, a reference luminance value and a reference color coordinate value.

Abstract: A method on an electronic device is described. A touch screen display of the electronic device is actively controlled in a higher-power mode of operation. Actively controlling the touch screen display in the higher-power mode is discontinued to enter a lower-power mode of operation. In the lower-power mode: at least one first control signal is provided to the touch screen display; in response to the at least one first control signal, a first portion of the touch screen display is activated and a first portion of a graphic is displayed on a first area of the touch screen display within the first portion; occurrence of a first user interaction that corresponds to the first portion of the graphic during the display of the first portion of the graphic is determined; and user interaction data is stored for the first portion of the graphic based on the first user interaction determination.

Abstract: A method on an electronic device is described. A touch screen display of the electronic device is actively controlled in a higher-power mode of operation. Actively controlling the touch screen display in the higher-power mode is discontinued to enter a lower-power mode of operation. In the lower-power mode: at least one first control signal is provided to the touch screen display; in response to the at least one first control signal, a first portion of the touch screen display is activated and a first portion of a graphic is displayed on a first area of the touch screen display within the first portion; occurrence of a first user interaction that corresponds to the first portion of the graphic during the display of the first portion of the graphic is determined; and user interaction data is stored for the first portion of the graphic based on the first user interaction determination.

Abstract: To reduce current noise by reducing the current peak value and the current rise slope, a data driver includes a delay unit and a plurality of output circuits. The delay unit sequentially delays a control signal and outputs delay control signals. The output circuits start outputting in response to the delay control signals. The delay unit generates the delay control signals to be output to the output circuits.

Abstract: The present disclosure provides a chamfer circuit in a driving system of a liquid crystal display (LCD) panel and a uniformity regulating system and method. The chamfer circuit comprises a discharging resistor. The discharging resistor is an adjustable resistor, a resistance of the adjustable resistor is adjustable. In the present disclosure, a slope of a chamfered section is changed by regulating the resistance of the discharging resistor to change uniformity of the LCD panel. In this way, the discharging resistance is regulated without replacing the discharging resistor, and the uniformity of the LCD panel is regulated in accordance with each piece of the LCD panel.

Abstract: There is provided an interference removing method of an image system including the steps of: respectively acquiring different numbers of images within two brightness intervals having different brightness variations using an image sensor having a sampling frequency; lighting a light source with a lighting frequency, which is a half of the sampling frequency, and synchronizing to the sampling frequency; and subtracting a first image, which is associated with the lighting of the light source, acquired in a later brightness interval of two adjacent brightness intervals having identical brightness variations by a second image, which is associated with a sampling time of the first image, acquired in an earlier brightness interval of the two adjacent brightness intervals. The present disclosure further provides an image system.

Abstract: In order to provide a display device and a method for driving a display device, each of which is capable of repairing a disconnection in a data signal line and further reduces electric power consumption, a display device (1) includes a repair amplifier control section (14) for causing a repair amplifier circuit (12) to operate at a low-performance level during any period within a period from when scanning of pixels in the display area in the display device (1) is finished to when next scanning is started.

Abstract: A driving method of a liquid crystal display (LCD) panel comprises a scan driving process and a data driving process. In the scan driving process, overlapping time regions are formed simultaneously between a positive edge and a negative edge of the scan lines when a drive of a last row of a scan line is switched to drive of a next row of the scan line. In the data driving process, when a time of data signal corresponding to the last row of the scan line overlaps a time of the overlapping time regions, the data signal corresponding to the next row of the scan line are outputted.

Abstract: A flat panel display is provided. In particular, a flat panel display including a driving circuit in which a timing controller and a data driver for driving a panel are mounted in a single IC, and a driving circuit thereof are provided. The flat panel display includes a display panel having a plurality of pixels, a gate driver controlling the plurality of pixels, and a plurality of driving circuits processing and converting an image signal and outputting the same to a display panel in a normal mode. The driving circuits generate a black image signal according to a synchronization signal.

Abstract: A liquid crystal display device includes an array substrate, a counter substrate and a liquid crystal layer held between the array substrate and the counter substrate. A display portion having a plurality of pixels arranged in a matrix is formed of the substrates and the liquid crystal layer. Each of the pixels includes a pixel electrode and a counter electrode arranged opposing to the pixel electrode. A driving portion is formed on the array substrate to supply a pixel voltage to the pixel electrode. A correcting circuit is formed on the array substrate to correct the voltage supplied to the pixel electrode by adding a predetermined DC voltage to the voltage supplied to the pixel electrode corresponding to gradations to be displayed in the pixel.

Abstract: A level shifter for a liquid crystal display is disclosed. The level shifter includes a pull-down transistor which includes a source terminal, to which the gate low voltage is supplied, and a drain terminal connected to an output terminal of the level shifter, and discharges a voltage of an output terminal of the level shifter, and an output stabilization circuit which is connected to a gate terminal of the pull-down transistor, controls a gate voltage of the pull-down transistor in the process of a power-on sequence, and discharges an output voltage of the level shifter.

Abstract: A driving circuit includes a first PWM driving module and a second PWM driving module. The first PWM driving module generates a first square-wave signal to drive a first illumination unit according to a first data signal of a data stream, wherein the first square-wave represents an illumination period of the first illumination unit in a display cycle. The second PWM driving module generates a second square-wave signal to drive the second illumination unit according to a second data signal of the data stream, wherein the second square-wave signal, which has a different phase with the first square-wave signal, represents an illumination period of the second illumination unit in the display cycle.