Abstract: The present invention discloses a timing controller and a liquid crystal display comprising the same, wherein, the timing controller comprises a data converting module (10) for converting inputted serial video stream data into parallel video stream data, and a memory (30) for storing the parallel video stream data, and also comprises an output module (50) connected with the memory (30) for generating a predetermined clock signal and outputting the parallel video stream data under the control of the predetermined clock signal. With the technical solution of the present invention, the problem in the prior art is solved that the rate of the outputted video stream data is affected by the input. In addition, as the outputted video stream data is controlled by the clock signal it generates, this solves the problem of long locking duration of the timing controller in the prior art.

Abstract: A method on an electronic device is described. A touch screen display of the electronic device is actively controlled in a higher-power mode of operation. The higher-power mode is discontinued to enter a lower-power mode of operation. In the lower-power mode: a first control signal is provided to the touch screen display and a first image is displayed on a first area of the touch screen display; occurrence of a first touch input that corresponds to the first area is determined and in response thereto, a second control signal is provided to the touch screen display and each action icon of a set of action icon is displayed on the touch screen display; occurrence of a second touch input that corresponds to an action icon is determined and in response thereto, an action indication for the current display session is selected and a corresponding selected action is performed.

Abstract: An exemplary image displaying method for a display device includes steps of: providing display data to pixels of the display device for displaying images; taking a special amount of frame of images as an image group, making polarities of a same pixel being of adjacent two frame of images in the image group and using a same polarity inversion in the adjacent two frame of images be different from each other, and making polarities of a same pixel being of the last frame of image in a former one of adjacent two image groups and of the first frame of image in a latter one of the adjacent two image groups and using the same polarity inversion in the last and first frame of images be the same with each other.

Abstract: A display device with a timing controller is disclosed. In one aspect the display includes first and second gate drivers, first and second gate lines extending in first and second directions from the first and second gate drivers, data lines extending in a third direction, a display panel including pixels connected to the first and second gate lines and the data lines, data driving circuits each driving corresponding data lines in response to an output start signal and a data signal, and a timing controller. The timing controller sets an output timing of the data signals according to a distance in the first direction between the first gate driver and the data driving circuits when the first gate lines are driven and sets an output timing of the data signals according to a distance in the second direction between the second gate driver and the data driving circuits when the second gate lines are driven.

Abstract: A display device and a method for driving the same are discussed. The display device includes a display panel including a common electrode commonly connected to pixels, a display driving circuit for applying a data voltage to the pixels during a vertical active time, and a sensor driving circuit which applies a gesture sensing driving signal to the common electrode during a vertical blank time and senses a gesture input.

Abstract: An electro-optic device includes pixel electrodes; a data line block for providing an image signal to a first pixel electrode group and a second pixel electrode group in one column of pixel electrodes arrayed in a line in a first direction, the data line block being configured by data line pairs in which a pair of a first data line and a second data line extending in the first direction is arranged for each column; an image signal supplying unit for sequentially providing an image signal in time-series to each of the data line pairs configuring the data line block from one end of each of the data line pairs; and an inspection voltage supplying unit for supplying an inspection voltage from another end of each of the data line pairs each to the data line block and separately to each of the first data line and the second data line.

Abstract: Low power consumption is realized focusing on the refresh interval of a low leakage display panel. Display systems and microcomputers are described herein. One embodiment of a display system includes a display driver. The driver receives an enable signal from the outside, stops the display operation of an internal circuit in an inactive state of the enable signal, and resumes the display operation of the internal circuit in an active state. Instead of the enable signal, a command supplied from the outside may be used. When resuming the display operation, the display driver performs control to make the start timing of the display operation earlier for a circuit that requires a long time for activation. A microcomputer that outputs an enable signal or a command controls the output or the output stop of display data according to the state of the enable signal or the command.

Abstract: A display device includes: a display unit including a plurality of pixels and a plurality of division areas; a data driver configured to apply a data signal corresponding to image data to the display unit, and to control a slew rate of the data signal, based on a bias voltage; and a bias controller configured to control the data driver so that the slew rate of the data signal is changed for each division area, based on a luminance variation of the image data corresponding to each of the division areas.

Abstract: A three-dimensional image display apparatus includes a display panel configured to display an image and including gate lines, data lines, and pixels connected to the gate lines and the data lines, a data driver configured to drive the data lines, a gate driver configured to drive the gate lines, a lens panel configured to refract light of the image displayed by the display panel, a lens driver configured to drive the lens panel, a lens controller configured to control the lens driver, and a timing controller configured to control the data driver, the gate driver, and the lens driver in response to an image signal and a control signal. The lens controller and the timing controller are mounted on the same control board.

Abstract: Methods of adaptive image compensation are provided. A method of adaptive image compensation includes receiving illumination information sensed by a light sensor. The method includes calculating image characteristic information by analyzing an input image. The method includes determining a frame rate responsive to at least one among the illumination information, the image characteristic information, and a frame rate control signal. Moreover, the method includes compensating the input image responsive to the frame rate. Related apparatuses and image processing systems are also provided.

Abstract: There is disclosed a gate driver, a driving circuit, and a liquid crystal display (LCD), wherein the gate driver comprises input terminals for inputting a CPV signal, an OE signal, and an STV signal, and output terminals for outputting a CKV signal and a CKVB signal, and a processing circuit is connected between the input terminals and the output terminals for processing the CPV signal, the OE signal, and the STV signal such that a preset time interval is present between the falling edge of the CKV signal and the rising edge of the CKVB signal during one period of the CKV signal, or a preset time interval is present between the rising edge of the CKV signal and the falling edge of the CKVB signal during one period of the CKVB signal.

Abstract: A liquid crystal display device supplies an active scan signal to each scan line while skipping a portion of a plurality of the scan lines, per one horizontal scan period, in a direction of the m-th to the first scan lines, by a first scan line drive circuit, and supplies the active scan signal to each scan line while skipping the portion of the plurality of the scan lines, per one horizontal scan period, in a direction of the m+1-th to the 2m-th scan lines, by a second scan line drive circuit. Therefore, the liquid crystal display device synchronizes with a timing of supplying the active signal with the first scan line drive circuit and the second scan line drive circuit, and supplies a data signal whose polarity is inverted to a positive polarity potential and a negative polarity potential per one horizontal scan period, to a data line.

Abstract: A method of differently producing driving clock signals for a shift register of a gate lines driving circuit of a Liquid Crystal Display (LCD), the method includes the steps of determining whether an ambient temperature is greater than or not in comparison to a predetermined threshold temperature; in response to the determining indicating that the ambient temperature is greater, using a first ON voltage and a first charge canceling method; and in response to the determining indicating that the ambient temperature is not greater, using a second ON voltage and a second charge canceling method, where the second ON voltage is different from the first ON voltage and where the second charge canceling method is different from the first charge canceling method. The second charge canceling method may have a shorter duration than that of the first charge canceling method. The second ON voltage may be greater than the first ON voltage.

Abstract: A method of refreshing a memory array for a driving circuit includes generating a word-line scanning signal corresponding to a word-line of a memory array, and turning on a plurality of memory cells corresponding to the word-line of the memory array according to the word-line scanning signal to refresh the plurality of memory cells corresponding to the word-line of the memory array, wherein the memory has a first number of bit-lines and a second number of word-lines.

Abstract: Disclosed is an image display device capable of reducing power consumption and improving display quality. The image display device includes pixels disposed at portions at which scanning lines and data lines intersect with each other; a scanning driving unit driving the scanning lines; a data driving unit driving the data lines; a driving frequency selecting unit generating a selecting signal including information on a driving frequency using data supplied from an external system; and a timing controlling unit controlling the scanning driving unit and the data driving unit using the driving frequency included in the selecting signal.

Abstract: A display device including a display panel displaying a still image and a moving image and a signal controller controlling signals to drive the display panel, wherein the signal controller includes a frame memory storing image data of the still image and providing the image data to the display panel, and the display panel is driven with a first scan ratio when displaying the moving image and is driven with a second scan ratio that is lower than the first scan ratio when displaying the still image.

Abstract: A stereoscopic image display device includes: a display panel including pixels; a liquid crystal lens panel disposed above the display panel, where the liquid crystal lens panel includes a first substrate, a second substrate disposed opposite to the first substrate, division electrodes disposed on the first substrate, a common electrode disposed on the second substrate, and a liquid crystal layer disposed between the first and second substrate; a common voltage supply unit configured to supply a common voltage to the common electrode; and a driving voltage supply unit configured to supply driving voltages to the division electrodes, where the liquid crystal layer of the liquid crystal lens panel is implemented as lenses by an electric field generated based on the driving voltages supplied to the division electrodes and the common voltage supplied to the common electrode, and the common voltage is driven as an alternating current voltage.

Abstract: A display device includes a panel displaying an image using image data and including a common electrode to which a common voltage is applied; a timing controller providing the image data to the panel and outputting a correction voltage corresponding to the image data; and a power supply unit generating a compensation voltage using a panel common voltage and the correction voltage and providing the compensation voltage to the panel, wherein the panel common voltage is a voltage measuring the common voltage applied to the panel.

Abstract: A method of driving a display panel is disclosed. In one aspect, the display panel includes a plurality of pixels arranged in odd and even rows and a plurality of odd and even gate lines respectively connected to the pixels of the corresponding odd and even rows. The method includes outputting odd gate signals to the odd numbered gate lines during two consecutive subframes and outputting even gate signals to the even numbered gate lines during two consecutive subframes. A frame is divided into two subframes.

Abstract: An image display device is capable of displaying an image, in which occurrence of color unevenness is suppressed. A method of driving the image display device is also disclosed. In an area above the dotted line, red light is transmitted in a first sub-frame period. In second and third sub-frame periods, light blocking data are respectively supplied as green data and blue data. Therefore, green light and blue light cannot be transmitted through the area. Hence, a red image with no color unevenness is displayed in the area. In contrast, in an area under the dotted line, the red light is transmitted in the first sub-frame period, and the green light is transmitted in the second sub-frame period. As a result, in a viewed image of the area, there is color unevenness where green is mixed to red.

Abstract: The present invention relates to a gate driving circuit, and an array substrate and a display panel thereof, wherein gate driving circuit includes multi-level gate driving units. A gate driving unit of each level comprises a starting unit, an energy storage unit, a pull-up unit, a first pull-down unit, a second pull-down unit and a third pull-down unit, wherein the second pull-down unit is coupled to the energy storage unit and a gate line, and configured to intermittently generate a second control signal based on a driving voltage, a clock pulse signal and a second reference voltage, and to pull the driving voltage and a gate signal on the gate line down to the second reference voltage.

Abstract: This display includes a driving voltage output portion outputting a driving voltage when receiving a display-on signal. The driving voltage output portion includes a delay circuit portion provided between a first switching element and a second switching element for delaying output timing for the driving voltage with respect to input timing for the display-on signal by delaying switching of the second switching element.

Abstract: A flat panel display includes a signal generator to generate data signals to respective data lines via an output terminal or to generate a control signal for controlling switches. The signal generator includes a first voltage supply unit to supply, to the output terminal, a voltage of a first voltage sources, a voltage stabilizing unit to raise or drop the voltage supplied to the output terminal, and a second voltage supply unit to supply, to the output terminal, a voltage from a second voltage source, after the voltage of the output terminal is raised or dropped.

Abstract: A liquid crystal display wherein power consumption of a gate drive circuit is reduced and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal panel having pixel regions defined by intersection of a plurality of gate lines and a plurality of data lines, a timing controller to output a clock pulse selectively having a first voltage level, second voltage level and third voltage level of different voltage levels and a data control signal, a gate drive unit to drive the gate lines in response to the clock pulse, and a data drive unit to drive the data lines in response to the data control signal.

Abstract: Disclosed is an LCD device in which a control signal is received and transmitted via a transmission line to be used for receiving and transmitting LVDS video signal between a timing controller and a source drive IC, the LCD device comprising a liquid crystal display panel for display an image; a data driver for driving data lines of the liquid crystal display panel through a plurality of source drive ICs; and a timing controller for outputting a packet signal obtained by combining a control signal and video signal to the source drive IC, wherein the source drive IC separates and outputs the control signal and video signal from the packet signal transmitted from the timing controller.

Abstract: A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.

Abstract: A method, system and computer program product for driving a display device by a display system is provided. The display system includes a processor, a first display controller, a second display controller and the display device. The first display controller receives display frames that are sent by the processor. The first display controller drives the display device when the processor sends new display frames. When the same display frames are continually sent by the processor, the control of the display device is switched to the second display controller, which is optimized for low-power operation. The control of the display device is switched in proximity to an input vertical synchronization (V-sync) pulse.

Abstract: The invention provides an image display device capable of reducing the transmission delay of a scanning signal. A plurality of scanning signal lines are wired in one pixel circuit row. Pixel circuits of the pixel circuit row are connected to any of the plurality of scanning signal lines.

Abstract: A method for reducing power consumption of a liquid crystal display system includes: a timing controller receiving an image signal of a frame; the timing controller generating a gate control signal and a source control signal according to the image signal; a gate driving circuit driving odd scan lines of a plurality of scan lines in turn and then driving even scan lines of the plurality of scan lines in turn according to the gate control signal; and a source driving circuit charging a plurality of sub pixels included in a liquid crystal panel through a plurality of data lines according to the source control signal, driving sequence of the plurality of scan lines, and data voltages corresponding to the image signal. Voltages of the plurality of data lines are switched one time at most, and a common voltage of the liquid crystal panel is a direct current voltage.

Abstract: A display device with an integrated touch screen and a method of driving the same are provided. The display device with an integrated touch screen includes a gate driver that is configured with a plurality of stages that include a pull-up transistor and first and second pull-down transistors and are respectively connected to a plurality of gate lines. The method includes: turning on the pull-up transistor to output a pull-up signal to each of the plurality of gate lines and, after the pull-up signal is outputted, turning on the first pull-down transistor to output a pull-down signal to each of the plurality of gate lines, during an image output period in each frame; and turning on the second pull-down transistor to output the pull-down signal to each of the plurality of gate lines, during a touch sensing period in each frame.

Abstract: A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Abstract: An electronic apparatus system is provided. The electronic apparatus system includes a register, a display mode computation unit, a display device and a control circuit. The register stores image information having a data input refresh frequency. The display mode computation unit generates a display mode control signal by computation based on an image characteristic categorization of the image information. The display device includes a display panel having a plurality of pixel units. The control circuit controls a display mode and a drive mode of the display panel according to the display mode control signal to further adjust a display refresh frequency of the display panel.

Abstract: A display device includes: a plurality of drive electrodes; a plurality of detection electrodes intersecting the plurality of drive electrodes; and a scan driving unit performing a first scan drive and a second scan drive. The first scan drive allows a display drive signal for driving the display elements to be applied to each of the plurality of common drive electrodes, and the second scan drive allows a touch detection drive signal for detecting an external proximity object to be applied to each of the plurality of common drive electrodes.

Abstract: A timing controller utilized in a display device includes an image processing circuit, a luminance adjusting circuit, a data converting circuit and a driving signal generating circuit. The image processing circuit performs image processing on image data of an image signal. The luminance adjusting circuit adjusts luminance of the processed image data according to a luminance characteristic of the display panel of the display device. According to a pixel arrangement of the display panel, the data converting circuit converts the adjusted image data to display data provided to a driving circuit of the display panel. The driving signal generating circuit generates a driving signal to control the driving circuit according to a synchronous signal of the image signal.

Abstract: A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors (8,10) are provided for selectively isolating the charge storage node from a first voltage input (9,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (10). The first transistor forms part of the voltage follower circuit.

Abstract: An LCD panel being driven in an overlapping drive mode by applying a gate high voltage during n horizontal synchronous intervals is disclosed. The LCD panel includes: a plurality of gate lines; and a gate driver configured to include a plurality of stages connected to the plurality of gate lines. The plurality of stages are grouped in a plurality of stage groups each including n stages. Odd-numbered stage groups each allows the n stages to be arranged in a Z shape with having a display area therebetween. Even-number stage groups each allows the n states to be arranged in an inverse-Z shape with having the display area therebetween.

Abstract: A display device includes a display panel including a gate line and a data line, a gate driver that outputs a gate voltage to the gate line according to a gate output enable signal, a data driver that outputs a data voltage to the data line, a detecting circuit that detects a state of a clock signal. The state of the clock signal includes a normal or abnormal state. A masking circuit performs a masking operation for the gate output enable signal according to the state of the clock signal and a level of a reset signal, where the level of the reset signal includes a first or second level corresponding to a power-on or off of the display device, respectively.

Abstract: The invention discloses a liquid crystal driving method and apparatus for black frame insertion of an image, and a liquid crystal display device. The method includes, in a black frame insertion period after the frame period ends, sending, by a timing controller, a row of black image data to a register of a source driver; and in the black frame insertion period, maintaining, by the register, the row of black image data being output until the black frame insertion period ends, so as to enable the row of black image data to refresh each row of liquid crystal cells. Accordingly, the complexity of driving processes and the data calculations in the black frame insertion are greatly reduced.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: When normal driving is switched to intermittent driving simultaneously with switching from a video image to a still image, a flicker may occur due to a response delay caused by dielectric anisotropy of liquid crystal. A display device has a first mode (video image driving) in which driving is performed at a first frame frequency and a second mode (still image driving) in which the driving is performed at a second frame frequency lower than the first frame frequency. When the first mode is switched to the second mode, the display device first performs the driving at a frame frequency higher than the second frame frequency for at least one frame and then, the driving is switched to be performed at the second frame frequency.

Abstract: A timing controller, a display device using the timing controller, and a method for driving the timing controller are discussed. The timing controller includes a frequency change sensing unit, that measures a length of an (n?1)th frame period and a length of an nth frame period, where n is a natural number equal to or greater than 2, and outputs timing signals of a low logic level when a length difference between the (n?1)th frame period and the nth frame period is greater than a predetermined first threshold value, a scan timing control signal output unit for outputting a scan timing control signal based on the timing signals, and a data timing control signal output unit controlling a data driving circuit based on the timing signals.

Abstract: A display device includes a display panel, a timing controller which receives a first image signal and a first control signal from an external device and outputs a second image signal and a second control signal, and a data driving part including a plurality of source integrated circuits (“IC”s) having different channel numbers based on a distance thereof from the timing controller, in which the data driving part receives the second image signal and the second control signal and outputs a third image signal and a third control signal to the display panel.

Abstract: A method of driving a display panel is provided. The method includes displaying a first image on at least one odd-numbered horizontal line of the display panel along a first direction and a second direction during a first period of a frame period and displaying a second image on at least one even-numbered horizontal line of the display panel along the first direction and second direction during a second period of the frame period.

Abstract: A ubiquitously mountable image display system includes a shape-reconfigurable display screen component to which is attached a plurality of circuit modules each having at least one light source. The shape-reconfigurable display screen component is formed of a material that accommodates flexing of the display screen component without creating a perceivable aberration in separation distance between two or more picture elements of an image that is rendered upon a viewing plane of the display screen component when light from the plurality of light sources is directed towards the viewing plane.

Abstract: A semiconductor device includes: a trimming object circuit configured to use a trimming circuit to adjust an output based on a trimming value; and a trimming value setting circuit configured to set the trimming value. The trimming value setting circuit includes: a register configured to volatilely store a pseudo-trimming value set with reference to a trimming table such that an output value of the trimming object circuit becomes equal to a target value; a trimming value storage configured to non-volatilely store a final trimming value, wherein the final trimming value is set by correcting the pseudo-trimming value with reference to a trimming value correction table such that the output value of the trimming object circuit, which is obtained based on the pseudo-trimming value, becomes equal to the target value; and a selector configured to select one of the pseudo-trimming value and the final trimming value as the trimming value.

Abstract: A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts.

Abstract: It is an object to reduce power consumption of a display device which can perform multi-gray scale display and to suppress deterioration of an element included in the display device. The usage of a display device includes a first initialization period in which the gray scale level of an entire pixel portion is converted into a first gray scale level and a second initialization period in which the gray scale level of an entire pixel portion is converted into a second gray scale level. In the first initialization period, scanning of a plurality of signals and weighting of a holding period of each signal are performed. Therefore, the small number of scanning of signals can realize voltage application for an appropriate time with respect to each of a plurality of gray scale storage display elements included in the display device.

Abstract: In one or more example embodiments, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.

Abstract: A display driving method comprises the steps of: determining a first target-level voltage and a second target-level voltage of a signal of the scan line; determining a first switch time and a second switch time according to an RC loading of the scan line; determining at least one first precharge-level voltage and at least one second precharge-level voltage according to the first target-level voltage, the second target-level voltage, the first switch time, and the second switch time; and outputting the first precharge-level voltage, the first target-level voltage, the second precharge-level voltage, and the second target-level voltage to drive the display panel, wherein the first precharge-level voltage is switched to the first target-level voltage after the first switch time, and the second precharge-level voltage is switched to the second target-level voltage after the second switch time.

Abstract: In one embodiment of the present application, a display controller is capable of changing a refresh rate, indicative of how often a screen displayed on a display device having a plurality of pixels is switched, between a low refresh rate of 40 Hz and a normal refresh rate of 60 Hz and generates (i) a dot clock (reference clock) serving as a timing signal indicative of a timing of operation in the display device, (ii) video data indicative of an image to be displayed on the screen, (iii) Hsync for defining a horizontal period of a display on the screen, and (vi) Vsync for defining a vertical period of the display on the screen, so as to supply the dot clock, the video data, Hsync, and Vsync to the display device, wherein the display controller includes a dot clock generation circuit for generating the reference clock whose frequency is constant without depending on a change of the refresh rate.