Of Electronic Circuit Chip Or Board Patents (Class 348/126)
  • Patent number: 7181058
    Abstract: A method and system are provided for inspecting electronic components mounted on printed circuit boards utilizing both 3-D and 2-D data associated with the components and the background on which they are mounted on the printed circuit board. Preferably, a 3-D scanner in the form of a solid state dual detector laser images the components and solder paste on the printed circuit board to obtain the 3-D and 2-D data. Then, a high speed image processor processes the 3-D data to find the locations of the leads and the solder paste. Then, the high speed image processor processes the 2-D data together with the locations of the leads and the solder paste to distinguish the leads from the solder paste. The high speed image processor may calculate centroids of feet of the leads, average height of the feet and border violation percentage of the solder paste.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: February 20, 2007
    Assignee: GSI Group, Inc.
    Inventors: John J. Weisgerber, Donald J. Svetkoff, Donald K. Rohrer
  • Patent number: 7177458
    Abstract: A method for automatically optically inspecting an electrical circuit (12), comprising: acquiring at least one optical image of an electrical circuit (12); generating at least one first inspection image from the at least one image and determining regions of candidate defects (236) therefrom; generating at least one additional inspection image for regions surrounding candidate defects (236), said at least one additional inspection image at least partially including optical information not included in the at least one first inspection image; and determining whether the candidate defect (236) is a specious defect by inspecting the at least one additional inspection image.
    Type: Grant
    Filed: September 10, 2000
    Date of Patent: February 13, 2007
    Assignee: Orbotech Ltd.
    Inventors: Nissim Savareigo, Dan Shalom, Nur Arad
  • Patent number: 7149343
    Abstract: Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or “defect artifacts,” that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: December 12, 2006
    Assignee: Marena Systems Corporation
    Inventors: Marian Enachescu, Sergey Belikov
  • Patent number: 7149340
    Abstract: A method and system for detecting defects in a physical mask used for fabricating a semiconductor device having multiple layers is disclosed, where each layer has a corresponding mask. The method and system include receiving a digital image of the mask, and automatically detecting edges of the mask in the image using pattern recognition. The detected edges, which are stored in a standard format, are imported along with processing parameters into a process simulator that generates an estimated aerial image of the silicon layout that would be produced by a scanner using the mask and the parameters. The estimated aerial image is then compared to an intended aerial image of the same layer, and any differences found that are greater than predefined tolerances are determined to horizontal defects. In addition, effects that the horizontal defects may have on adjacent layers are analyzed to discover vertical defects.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: December 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Paul Filseth, Neal Callan, Kunal Taravade, Mario Garza
  • Patent number: 7145162
    Abstract: The invention provides a method and an apparatus for determining a height of a point on a wire loop. A height gauge device is positioned over the point on the wire loop to be measured. Incident light is projected from the height gauge device for illuminating the point. The height gauge device receives reflected light produced from the incident light and a processor coupled to the height gauge device determines from a characteristic of the reflected light the height of the said point relative to a reference surface. Further methods and apparatus for finding a position and height of a highest point on the wire loop are also provided.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: December 5, 2006
    Assignee: ASM Assembly Automation Ltd.
    Inventors: Xiao Hui Cheng, Wing Hong Leung
  • Patent number: 7133550
    Abstract: A pattern inspection method in which an image can be detected without an image detection error caused by an adverse effect to be given by such factors as ions implanted in a wafer, pattern connection/non-connection, and pattern edge formation. A digital image of an object substrate is attained through microscopic observation thereof, the attained digital image is examined to detect defects, while masking a region pre-registered in terms of coordinates, or while masking a pattern meeting a pre-registered pattern, and an image of each of the defects thus detected is displayed. Further, each of the defects detected using the digital image attained through microscopic observation is checked to determine whether its feature meets a pre-registered feature or not. Defects having a feature that meets the pre-registered feature are so displayed that they can be turned on/off, or they are so displayed as to be distinguishable from the other defects.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: November 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hiroi, Masahiro Watanabe, Chie Shishido, Aritoshi Sugimoto, Maki Tanaka, Hiroshi Miyai, Asahiro Kuni, Yasuhiko Nara
  • Patent number: 7116817
    Abstract: A method and apparatus for inspecting a wafer in which a focused charged particle beam is irradiated onto a surface of a wafer on which patterns are formed through a semiconductor device fabrication process, a secondary charged particle image of a desired area of the wafer is obtained by detecting secondary charged particles emitted from the surface of the wafer, and information about image feature amount of each pattern within the desired area from the obtained secondary charged particle beam image. The information about image feature amount is compared with a preset value, and on the basis of a result of the comparison, a quality of patterns which have been formed around the desired area is estimated, and information of a result of the estimation is outputted.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: October 3, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Maki Tanaka, Masahiro Watanabe, Kenji Watanabe, Mari Nozoe, Hiroshi Miyai
  • Patent number: 7113629
    Abstract: A pattern inspecting apparatus includes a substrate support table, a table driver for driving the substrate support table through actuators, a camera, an image processor, and a controller connected to a keyboard and a CRT. The image processor has a chip comparing inspection unit for executing a chip comparing inspection, a cell comparing inspection unit for executing a cell comparing inspection, an image memory, an integrating decision unit for integrating results of inspection by the chip comparing inspection unit and results of inspection by the cell comparing inspection unit and making a final decision as to the presence of a defect, and an area memory.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: September 26, 2006
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Hiroyuki Onishi
  • Patent number: 7110591
    Abstract: A system and method for recognizing markers on, e.g., a PCB (printed circuit board). In one aspect, a system for recognizing a marker in an image comprises an image capture module (14) for extracting image features associated with an input image of a ROI (region of interest) captured through a lens 15, an image processor (16) comprising a first marker recognition processor (17) for recognizing a marker in the input image based on a normalized correlation and a second marker recognition processor (18) for recognizing a marker in the input image based on gray value histograms; a training module 19 for building template images and histograms that are used by the image processor (16) to detect a marker in the input image and a database (20) for indexing and storing trained template images and trained histograms.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: September 19, 2006
    Assignee: Siemens Corporate Research, Inc.
    Inventors: Claus Neubauer, Ming Fang
  • Patent number: 7075565
    Abstract: An automated optical inspection system includes a plurality of asynchronously triggerable cameras for providing image data of an object, such as a printed circuit board. The circuit board is divided into fields of view that are to be imaged in one or more cameras in one or more lighting modes. Each location on the board can be imaged by each camera in a plurality of lighting modes in a single pass across the board. The image data for each of the cameras can be concurrently transferred directly to main memory for opportunistic analysis by the main computer. The system allows the full bandwidth of the cameras to be utilized for reducing the inspection time of the board.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: July 11, 2006
    Assignee: Landrex Technologies Co., Ltd.
    Inventors: Douglas W. Raymond, Richard D. Fleming
  • Patent number: 7053395
    Abstract: A system for inspecting a specimen, such as a semiconductor wafer that uses a laser light source for providing a beam of light. The beam is applied to a traveling lens acousto-optic device having an active region and responsive to an RF input signal to selectively generate plural traveling lenses in the active region. The traveling lens acousto-optic device is operative to receive the light beam and generate plural flying spot beams, at the respective focus of each of the generated traveling lenses. A light detector unit, having a plurality of detector sections, each detector section having a plurality of light detectors and at least one multi-stage storage device operative to receive in parallel an input from the plurality of light detectors, is used to generate useable scan data. Information stored in each of the storage devices is serially read out concurrently from the multiple stages.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 30, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Haim Feldman, Emanuel Elyasaf, Nissim Elmaliach, Ron Naftali, Boris Golberg, Silviu Reinhorn
  • Patent number: 7031511
    Abstract: A defect candidate area extraction part determines whether or not each object pattern divisional area obtained by dividing picked-up image data of a printed board having through holes (holes) has a different portion exceeding a prescribed allowance between the same and a positionally corresponding area of a master pattern thereby determining whether or not each object pattern divisional area is a defect candidate and extracting a defect candidate area. Further, a defect determination part determines whether or not each through hole is defective on the basis of a result of comparison between hole information as to the through hole present in the object pattern divisional area extracted from the plurality of object pattern divisional areas as the defect candidate area and hole information as to a through hole present in an area of the master pattern corresponding to the defect candidate area. Thus provided is a hole inspection apparatus capable of correctly and efficiently inspecting holes.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: April 18, 2006
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Norio Asai
  • Patent number: 7024031
    Abstract: A system for inspecting components is provided. The system includes an axial lighting system that illuminates the component with axial lighting to allow one or more features of the component to be located, such as by causing protruding features to be brighter than the background and recessed features to be darker than the background. An off-axis lighting system illuminates the component with off-axis lighting in the absence of the axial lighting to allow the component to be inspected to locate one or more features, such as a bump contact.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: April 4, 2006
    Assignee: August Technology Corp.
    Inventors: Ramiro Castellanos-Nolasco, Sanjeev Mathur, John Mark Thornell, Thomas Casey Carrington, Hak Chuah Sim, Clyde Maxwell Guest, Charles Kenneth Harris
  • Patent number: 7016526
    Abstract: A method is provided for the detection of defects on a semiconductor wafer by checking individual pixels on the wafer, collecting the signature of each pixel, defined by the way in which it responds to the light of a scanning beam, and determining whether the signature is that of a faultless pixel or of a pixel that is defective or suspect to be defective. An apparatus is also provided for the determination of such defects, which comprises a stage for supporting a wafer, a laser source generating a beam that is directed onto the wafer, collecting optics and photoelectric sensors for collecting the laser light scattered by the wafer in a number of directions and generating corresponding analog signals, an A/D converter deriving from said signals digital components defining pixel signatures, and selection systems for identifying the signatures of suspect pixels and verifying whether the suspect pixels are indeed defective.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: March 21, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Zeev Smilansky, Sagie Tsadka, Zvi Lapidot, Rivi Sherman
  • Patent number: 6987874
    Abstract: A tool useful for defect analysis can be provided in which a surface image of the whole single die is detected, and the surface image of the whole detected die, information of defect position and a magnified image of a defect region are displayed together at a time so that the operator can intuitively grasp what circuit pattern the defect or the like is located on within a die.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 17, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takenori Hirose, Mineo Nomoto
  • Patent number: 6978041
    Abstract: An object of the present invention is to increase efficiency in review work by appropriately narrowing down review work that verifies shapes of visual defects relating to an enormous amount of defects detected by a visual inspecting apparatus with high sensitivity. In order to appropriately extract defect information from an inspecting apparatus, a filter function and a sampling function are prepared by unitizing the functions. As a result, defects as review targets are narrowed down and extracted automatically using the filter function and the sampling function in combination. In addition, sequencing the filter conditions and the sampling conditions and registering the sequence enables automatic filtering and sampling on the basis of information on a wafer as a review target, and thereby only defect information on the review target is extracted.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: December 20, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Isogai, Hitoshi Komuro, Hideo Wada, Katsuharu Shoda
  • Patent number: 6952492
    Abstract: A method and apparatus for inspecting a semiconductor device in which failure occurence conditions on a whole wafer are estimated by calculating the statistic of potential contrasts in pattern sections from sampled images to implement higher throughput, and defective conditions of a process are detected at an early stage with the help of time series data of the estimate result.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: October 4, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Maki Tanaka, Masahiro Watanabe, Kenji Watanabe, Mari Nozoe, Hiroshi Miyai
  • Patent number: 6950549
    Abstract: In a visual inspection method and apparatus, a picture processing unit converts an original picture, obtained by taking a photograph of a BGA illuminated by a ring illuminator from above, using a camera, and labels a binary picture obtained by this binary conversion. Then, it forms a rectangle circumscribing an outer circumference of a labeling picture obtained by the labeling, and inverts a labeling picture within the formed circumscribing rectangle, and removes a portion of a region formed by the outer circumference and the circumscribing rectangle in a picture obtained by the inversion, and then generates an inspection picture by adding a picture obtained by the removal to the labeling picture, and accordingly judges a pass or rejection of the inspection target sample based on the generated inspection picture. Thus, the inspection can be carried out at high accuracy irrespectively of a low cost.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: September 27, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yoshihiro Sasaki, Masahiko Nagao
  • Patent number: 6950548
    Abstract: A method and system create a geometric object model for use in machine vision inspection. A pixel image representation of an object is acquired. Based on this pixel image representation, part models for the parts of the object are generated. Each part model corresponds to a different part of the object. From the part models of the object, a model for the entire object can be created. Using this created object model, a test inspection is performed on a set of test images, and each of the test images is associated with a set of known inspection measurements. The test inspection produces a set of testing inspection measurements. If the test inspection yields satisfactory performance, the object models created are stored.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 27, 2005
    Assignee: Cognex Corporation
    Inventors: Ivan A. Bachelder, Yun Chang, Yasunari Tosa, Venkat Gopalakrishnan, Raymond Fix, Rob Milligan, Therese Hunt, Karen Roberts
  • Patent number: 6943826
    Abstract: To facilitate the debugging an imaging device having a large number of pixels, a debugging apparatus has an image view display for qualitatively displaying pixel characteristics in a first range of the imaging device, and a code view displaying unit for quantitatively displaying numerical or symbolic data of individual pixels in a second range that is smaller than the first range and designated in an area displayed by the image view display.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: September 13, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Hiroshi Tatekawa, Yukio Nishimura, Katsumi Sakamoto
  • Patent number: 6941009
    Abstract: The invention concerns a method for evaluating pattern defects on a wafer surface, comprising the following steps: acquiring the surface data of a plurality of individual image fields (4) of a series-produced wafer (1); storing the data in a reference data set and making it available as reference data for the inspection of further wafers of the same series; inspecting, successively in time, the individual image fields (4) on the surface of a wafer (1) presently being examined; retrieving from the reference data set a reference datum corresponding to the respective individual image field (4) presently being inspected; comparing the surface of each individual image field (4) currently being inspected to the corresponding reference datum; if one or more deviations are identified, subsequently classifying the deviations into critical and noncritical defects in terms of the functionality of the chip; and simultaneously updating or adding to the reference data set.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: September 6, 2005
    Assignee: Leica Microsystems Jena GmbH
    Inventor: Joachim Wienecke
  • Patent number: 6940537
    Abstract: To provide an inspecting apparatus of a printed state or the like in a flexible printed circuit board which requires no skill, generates no error by oversight and further improves an operation efficiency, a substrate feeding out unit (2), a substrate inverting unit (4), a camera inspecting unit (5), a substrate inverting unit (9) and a defect point marking unit (10) for a printed state or the like are sequentially placed on working tables (1, 1) along a moving direction of a flexible printed circuit board, in this order, the substrate inverting units (4, 9) respectively invert the flexible printed circuit board, the camera inspecting unit (5) detects a print defect point by means of a camera (8), and the defect point marking unit (10) applies a marking to the print defect point by a laser marker (13) on the basis of a signal output from the camera inspecting unit (5).
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 6, 2005
    Assignee: Minami Co., Ltd.
    Inventor: Takehiko Murakami
  • Patent number: 6937753
    Abstract: An automated defect inspection system has been invented and is used on patterned wafers, whole wafers, broken wafers, partial wafers, sawn wafers such as on film frames, JEDEC trays, Auer boats, die in gel or waffle packs, MCMs, etc. and is specifically intended and designed for second optical wafer inspection for such defects as metalization defects (such as scratches, voids, corrosion, and bridging), diffusion defects, passivation layer defects, scribing defects, glassivation defects, chips and cracks from sawing, solder bump defects, and bond pad area defects.
    Type: Grant
    Filed: April 29, 2000
    Date of Patent: August 30, 2005
    Assignee: August Technology Corp.
    Inventors: Jeffrey O'Dell, Thomas Verburgt, Mark Harless, Steve Herrmann
  • Patent number: 6925202
    Abstract: A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: August 2, 2005
    Assignee: Synopsys, Inc.
    Inventors: Linard Karklin, Linyong Pang, Lynn Cai
  • Patent number: 6901160
    Abstract: The present invention provides a method and an apparatus for evaluating the surfaces of substrates for three dimensional defects. The present invention uses low-angled lighting positioned on opposite sides of the substrate. A camera positioned above the substrate captures two images thereof, one using the first light source and one using the second. The first and second images are subtracted from one another to create a third image. Camera data suggestive of three dimensional features is emphasized by subtracting the two images and can be evaluated. A fourth image may be created by selecting the minimum values between the first and second images on a point-by-point basis. The fourth image also provides useful information in evaluating three dimensional defects.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: May 31, 2005
    Assignee: Electro Scientific Industries
    Inventors: Kenneth Chapman, Sam Dahan
  • Patent number: 6870951
    Abstract: One embodiment of the invention provides a system that facilitates auto-alignment of images for defect inspection and defect analysis. The system operates by first receiving a reference image and a test image. Next, the system creates a horizontal cut line across the reference image and chooses a vertical feature on the reference image with a specified width along the horizontal cut line. The system also creates a vertical cut line across the reference image and chooses a horizontal feature on the reference image with the specified width along the vertical cut line. Finally, the system locates the vertical feature and the horizontal feature on the test image so that the reference image and the test image can be aligned to perform defect inspection and defect analysis.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: March 22, 2005
    Assignee: Numerical Technologies, Inc.
    Inventor: Lynn Cai
  • Patent number: 6853744
    Abstract: An improved circuit board inspection system incorporates a technique that confirms observed electrical connection defects. The improved circuit board inspection system applies a localized investigative routine upon portions of a printed circuit board having one or more identified defects. The technique accounts for the slope of a portion under test of the printed circuit board and provides results that are more accurate from inspection systems that report electrical connection defects.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: February 8, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Horst Mueller, Sunit Bhalla, Kris Kanack, Stig Oresjo
  • Patent number: 6850637
    Abstract: An optical inspection system with an improved illumination system. The improved illumination system used to illustrate the invention has a base formed from a printed circuit board. Substrates for mounting lighting elements, which are exemplified by light emitting diodes, are formed also on printed circuit boards. These circuit boards have serrated edges and the diodes are mounted to the serrations. This configuration allows the light emitting elements to be focused on the focal point. Also in the exemplary illumination system, the light emitting elements have different beam widths so that variations in the illumination intensity as a function of elevation angle are reduced.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: February 1, 2005
    Assignee: Teradyne, Inc.
    Inventor: John B. Burnett
  • Patent number: 6810139
    Abstract: A method is provided for the detection of defects on a semiconductor wafer by checking individual pixels on the wafer, collecting the signature of each pixel, defined by the way in which it responds to the light of a scanning beam, and determining whether the signature is that of a faultless pixel or of a pixel that is defective or suspect to be defective. An apparatus is also provided for the determination of such defects, which comprises a stage for supporting a wafer, a laser source generating a beam that is directed onto the wafer, collecting optics and photoelectric sensors for collecting the laser light scattered by the wafer in a number of directions and generating corresponding analog signals, an A/D converter deriving from said signals digital components defining pixel signatures, and selection systems for identifying the signatures of suspect pixels and verifying whether the suspect pixels are indeed defective.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: October 26, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Zeev Smilansky, Sagie Tsadka, Zvi Lapidot, Rivi Sherman
  • Publication number: 20040201669
    Abstract: A web inspection system provides detection of web flaws along the machine direction and cross direction of a web. The detectable percent contrast between good web material and bad web material in one embodiment approaches noise level. The web inspection system utilizes a multiple of smart cameras connected to a host computer via an ethernet hub. Each smart camera includes a line scan camera for producing digital pixels, a means for lighting and pixel correction on a pixel by pixel basis, a web edge detector for monitoring the edges of a web, a multi-pipeline flaw detection pre-processor for detecting very small changes in the web material, a run length encoder for generating data regarding the location of each group of potential flaws in a cross direction, a 2D blob detector and analyzer for generating data regarding the location of block flaws along a machine direction, and an inspect/reject analysis for determining the actual flaw data from the potential flaw data.
    Type: Application
    Filed: April 13, 2004
    Publication date: October 14, 2004
    Inventors: Sujoy D. Guha, Chris M. Kiraly, Robin D. Becker
  • Publication number: 20040150714
    Abstract: The apparatus includes: an illumination system having a planar printed circuit board, and a plurality of light producing elements mounted on the planar printed circuit board and divided into at least one area, a control system, wherein the light producing elements can be selected from at least one area and lighted to illuminate by the control system, and a flat thin lens system in front of and connected to the illumination system to focus the lights emitted from the light producing elements onto any position of the printed circuit board. The method applied to proposed apparatus includes steps of: (a) choosing a position, (b) setting the illumination conditions, (c) producing the required illumination through focusing the lights on the chosen position, (d) recording the image of chosen position, (e) displaying the image, (f) comparing the recording image with the referencing image, and (g) making a record of comparison.
    Type: Application
    Filed: July 1, 2003
    Publication date: August 5, 2004
    Applicant: Test Research, Inc.
    Inventor: Don Lin
  • Patent number: 6771819
    Abstract: A system and method for object inspection that includes an image recognition program stored on a tangible medium for classifying and subclassifying regions of interest on an image. The image recognition program can be used in an image inspection system to determine defects on objects such as printed wiring assemblies. The image recognition program is executable to collect raw image data, segment out rectangular regions of interest that can be component sites defined by CAD data, preprocess each region of interest by scaling, gain and offset correction, and gamma correction, generating a set of image spaces for each region of interest using a set of spatial image transforms, generating features on the image spaces, scoring the features, comparing the feature scores to a knowledge base of feature scores to make a class determination for the features, generating a presence/absence decision confidence for the features, calculating a class determination and decision confidence for each region of interest.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: August 3, 2004
    Assignee: Intelligent Reasoning Systems, Inc.
    Inventors: Mark R. DeYong, Jeff E. Newberry, John W. Grace, Thomas C. Eskridge
  • Patent number: 6760060
    Abstract: An observation apparatus includes a CCD sensor which has, on a light-receiving surface, pixel lines each including a plurality of pixels, sequentially shifts charge signals of the pixels of each line, which are generated upon receiving light, to the adjacent line, and sequentially outputs the charge signals through the line at one end; an illuminating device for illuminating a moving observation target with a laser beam; an imaging device for focusing scattered light from the moving observation target to form an image on the light-receiving surface; and a driving circuit for driving the CCD such that the shift speed of the charge signals matches the moving speed of the image on the light-receiving means. In some cases, the CCD sensor and the driving circuit has a function of shifting the charge signals in a direction perpendicular to the shift direction.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: July 6, 2004
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Kazuo Moriya
  • Patent number: 6760471
    Abstract: A system and method for compensating pixel values in an inspection machine for inspecting printed circuit boards includes an image acquisition system for providing pixel values from a digitized image to a compensation circuit. The compensation circuit applies one or more compensation values to the digitized pixel values to provide compensated digitized pixel values for storage in a memory. The compensated digitized pixel values are then available for use by an image processor which implements inspection techniques during a printed circuit board manufacturing process. With this technique, the system corrects the errors on a pixel by pixel basis as the pixel values representing an image of a printed circuit board are transferred from the image acquisition system to the memory.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 6, 2004
    Assignee: Teradyne, Inc.
    Inventor: Douglas W. Raymond
  • Patent number: 6757421
    Abstract: A method and apparatus for determining defects in a circuit pattern. An image including a circuit pattern is acquired. An outline of the circuit pattern is extracted and a contour image is generated. A shape of a contour in the contour image is evaluated to determine whether a defect exists.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: June 29, 2004
    Assignee: Cognex Corporation
    Inventor: Kazutoshi Kubo
  • Patent number: 6750899
    Abstract: A novel inspection system for inspecting an article of manufacture, such as a printed circuit board, is disclosed, where the system includes a strobed illuminator adapted to project light through a reticle so as to project a pattern of light onto an area of the printed circuit board. A board transport responsively positions the board to at least two distinct positions, where each position corresponding to a different phase of the projected light. Also included is a detector adapted to acquire at least two images of the area, each image corresponding to one of the at least two different phases. An encoder monitors the movement of the board and outputs a position output, and a processor connected to the encoder, the board transport, the illuminator and the detector controlledly energizes the illuminator to expose the area as a function of the position output, the processor co-siting the at least two images and constructing a height map image with the co-sited images.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: June 15, 2004
    Assignee: CyberOptics Corporation
    Inventors: David Fishbaine, Timothy A. Skunes, Eric P. Rudd, David M. Kranz, Carl E. Haugan
  • Patent number: 6744913
    Abstract: A system for locating features in image data is provided. The system includes a first component system. The first component system compares first component data, which can be pixel data of a first user-selected component of the feature, to first test image data, which can be selected by scanning image data of a device, such as a die cut from a silicon wafer. The system also includes second component system that is connected to the first component system, such as through data memory locations of a processor. The second component system compares second component data to second test image data if the first component system finds a match between the first component data and the first test image data. The second test image data is selected based upon the first test image data, such as by using a known coordinate relationship between pixels of the first component data and the second component data.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: June 1, 2004
    Assignee: Semiconductor Technology & Instruments, Inc.
    Inventors: Clyde Maxwell Guest, John Mark Thornell
  • Patent number: 6738503
    Abstract: A notch inspection method based on shading pattern matching for inspecting notches on semiconductor packages or like objects. A template is created to characteristically express brightness gradations of a notch edge in a picture, i.e., to represent the notch edge in pixels constituting contiguous bright and dark portions of the edge. The template may be created on the basis of notch size information or notch size measurements. The template is checked against pictures under inspection in shading pattern matching whereby presence of a notch is determined. Computations of shading pattern matching are omitted regarding portions of the notch edge where brightness remains unchanged.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: May 18, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Sakaue, Toshiya Ijichi
  • Patent number: 6710320
    Abstract: An imaging device is provided which includes an LED, a telecentric lens which collimates LED light and converts light reflected by an object, a half mirror which reflects the LED light toward the telecentric lens and allows transmission of the reflected light converged by the telecentric lens, a diaphragm, and a two-dimensional imaging element.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: March 23, 2004
    Assignee: Olympus Optical Co., Ltd.
    Inventor: Shunsuke Kurata
  • Patent number: 6707552
    Abstract: A test fixture for testing circuit components includes at least one test bar, at least one tray, a test pedestal, a transportable test stage, a pickup collet, a first camera, and a second camera. Each test bar contains at least one circuit component. Each tray contains at least one test bar. The test pedestal is adapted to hold at least one test bar. The transportable test stage includes at least one tray and the test pedestal. The transportable test stage transports the circuit component under test from the pickup collet to the test site and return. The trays and test pedestal are in a fixed position with respect to the test stage. The pickup collet picks up test bars from the trays and the test pedestal. The pickup collet also places the test bars in the trays and on the test pedestal. The first camera is used to visually align the pickup collet and components on the test stage, and read test bar identification codes. The second camera is used to visually align the test bars with a test site.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: March 16, 2004
    Assignee: Triquint Technology Holding Co.
    Inventors: Steven S. Gilmore, John Leiby, John S. Rizzo, Kenneth R. Weidner
  • Patent number: 6700603
    Abstract: An inspection system for inspecting discrete wiring patterns on a continuous substrate sheet of a flexible material by making the use of the substrate sheet as a feeding carrier. The system is capable of assuring accurate positioning of the wiring patterns (14) for reliable inspection even with the use of the flexible substrate sheet (10) as the sole feeding carrier. The inspection system includes an inspection zone (30) provided with camera (51, 54) for inspecting the individual wiring patterns (14) and detecting a position of said wiring pattern on the substrate sheet. A draw-in roller (31, 32) is provided to introduce the substrate into the inspection zone. Associated with the draw-in roller is a draw-out roller (32, 33) which draws out the substrate sheet from the inspection zone and is positioned to define the inspection zone between the draw-in roller and the draw-out roller as well as to give a tension to the substrate sheet for extending the substrate sheet straight through the inspection zone.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: March 2, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Tetsuya Okuchi, Hiroyuki Ishiguro, Yoshio Mori, Takeshi Kitamura
  • Patent number: 6696679
    Abstract: A method for focusing on disk-shaped objects with patterned and unpatterned surfaces includes imaging of the patterned and unpatterned surfaces on a disk-shaped object for defect detection and defect classification by using various preset values of a focus regulation system to acquire the image sequence. At least one preset value is learned on the basis of an image sequence at least at one position in a substantially flat reference region of the surface of the disk-shaped object. A regulated adjustment is provided of a measurable distance from a carrier plane to a reference plane, wherein the carrier plane serves as a support for the disk-shaped objects. The distance is adjusted by applying the at least one preset value, which is overlaid on the regulation system, a focus state is evaluated by an image processor according to at least one rule, and the at least one preset value is ascertained therefrom.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: February 24, 2004
    Assignee: Leica Microsystems Wetzlar GmbH
    Inventors: Michael Graef, Uwe Graf, Joachim Wienecke, Guenter Hoffmann, Karl-Heinz Franke, Lutz Jakob
  • Patent number: 6697154
    Abstract: A system has a projection lens directing on-axis light and low level LEDs directing light to blind microvias. A high resolution camera captures blind microvia images and an image processor recognizes defects according to classifications according to reflected light area and centroid position. The lens is telecentric for particularly effective image capture in blind microvias. The system also has an array of 6000 back lighting LEDs providing illumination for capture of images by a camera. These images are analyzed by the image processor to detect defects such as blocked through microvias.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: February 24, 2004
    Assignee: MV Research Limited
    Inventors: Mark Douglas Owen, Adrian Boyle, Niall Dorr, James Mahon, Peter Conlon
  • Patent number: 6693664
    Abstract: A method and system for fast on-line electro-optical detection of wafer defects featuring illuminating with a short light pulse from a repetitively pulsed laser, a field of view of an electro-optical camera system having microscopy optics, and imaging a moving wafer, on to a focal plane assembly optically forming a surface of photo-detectors at the focal plane of the optical imaging system, formed from six detector ensembles, each ensemble including an array of four two-dimensional CCD matrix photo-detectors, whereby each two-dimensional CCD matrix photo-detector produces an electronic image of a large matrix of two million pixels, such that the simultaneously created images from the different CCD matrix detectors are processed in parallel using conventional image processing techniques, for comparing the imaged field of view with another field of view serving as a reference, in order to find differences in corresponding pixels, indicative of the presence of a wafer die defect.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: February 17, 2004
    Assignee: Negevtech
    Inventor: Gad Neumann
  • Patent number: 6690819
    Abstract: A method and apparatus for accurately recognizing most of components available in the market with moderate illuminating condition in high speed image processing are disclosed. After imaging a component having a predetermined electrode pattern, a core electrode 32 is extracted with the image being swept from a corner 33a (S1) through a small window. A H0V0 coordinate system is implemented with the core electrode set as its origin to observe its neighbor electrodes (S2). At this state, electrodes are sequentially extracted through a small window placed in an area predicted from previously extracted electrodes. Thereafter, an extracted electrode pattern is produced, and coordinates of its electrodes are obtained. Then, the extracted electrode pattern is collated with the predetermined electrode pattern by overlaying with each other for positioning (S3).
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: February 10, 2004
    Assignee: Juki Corporation
    Inventor: Takashi Teraji
  • Publication number: 20040021769
    Abstract: A method for detecting artifacts produced during film scanning in a scanning device, the method includes the steps of (a) providing film having a plurality of frames with an area of substantially constant density; (b) scanning the area of substantially constant density by the scanning device; (c) generating a profile consisting of the average of substantially all pixels at substantially the same location in the area of substantially constant density; and (d) detecting an artifact based on comparing the profile to a first threshold.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Applicant: Eastman Kodak Company
    Inventors: Scott McCloskey, Keith A. Jacoby, Robert W. Kulpinski, Douglas W. Christoffel
  • Patent number: 6687397
    Abstract: A system and method for object inspection that includes an image recognition program stored on a tangible medium for classifying and subclassifying regions of interest on an image. The image recognition program can be used in an image inspection system to determine defects on objects such as printed wiring assemblies. The image recognition program is executable to collect raw image data, segment out rectangular regions of interest that can be component sites defined by CAD data, preprocess each region of interest by scaling, gain and offset correction, and gamma correction, generating a set of image spaces for each region of interest using a set of spatial image transforms, generating features on the image spaces, scoring the features, comparing the feature scores to a knowledge base of feature scores to make a class determination for the features, generating a presence/absence decision confidence for the features, calculating a class determination and decision confidence for each region of interest.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: February 3, 2004
    Assignee: Intelligent Reasoning Systems, Inc.
    Inventors: Mark R. DeYong, Jeff E. Newberry, John W. Grace, Thomas C. Eskridge
  • Patent number: 6683682
    Abstract: An electronic component inspection equipment effective to prevent reflection of a virtual image in which among side walls of a vessel for accommodating an electronic component, an image pick-up direction to a first side wall is set in a direction of Brewster angle &PSgr;B1 of the first side wall, a first prism and a first polarized light beam splitter are disposed on the image pick-up direction, an image pick-up direction of a second side wall is set in a direction of Brewster angle &PSgr;B2 of the second side wall, and a second prism and a second polarized light beam splitter are disposed on the image pick-up direction.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: January 27, 2004
    Assignee: Cognex Technology and Investment Corporation
    Inventors: Yasuyoshi Suzuki, Masashi Higashi, Akihiko Souda
  • Publication number: 20040001140
    Abstract: A semiconductor chip mounting apparatus able to raise the positional accuracy when mounting a semiconductor chip on a package including a stage on which the substrate is carried, a visible light source for directly illuminating the substrate from above the stage, a semiconductor chip conveying means for holding from one surface the semiconductor chip comprised of silicon formed to a thickness through which visible light can pass and conveying it on the substrate carried on the stage, a capturing means arranged at a position facing the stage and capturing visible light passing through the semiconductor chip held by the semiconductor chip conveying means so as to capture patterns formed on the substrate carried on the stage and the semiconductor chip, and a positioning means for positioning the semiconductor chip on the substrate based on the patterns of the substrate and the semiconductor chip captured by the capturing means.
    Type: Application
    Filed: June 26, 2003
    Publication date: January 1, 2004
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Murayama
  • Patent number: 6657656
    Abstract: A plurality of BGA packages are formed in a work, and alignment marks are put at least on the top and rearmost ones of the BGA packages. The top BGA package is stopped in an image pick-up area, and an alignment mark image and a ball image are picked up while relative movement between the work and a camera is started. Ball images of the second and the following BGA packages are picked up while the relative movement between the camera and the work is continued, the relative movement is stopped when a ball image of the last BGA package is picked up, and an alignment mark image of the rearmost BGA package is picked up after the relative movement is stopped. The positions of balls are calculated while the posture of the work as a whole is taken into consideration, and judgment is made as to whether the positions of balls are good or bad.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: December 2, 2003
    Assignee: Shibuya Kogyo Co., Ltd.
    Inventors: Ryoichi Ueda, Tohru Kesyo, Yoshihisa Kajii, Koji Shimada