Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: An image display device comprises a first clock generator for generating and outputting a first clock based on input horizontal synchronizing signals corresponding to horizontal lines making up input image signals, a second clock generator for generating and outputting a second clock, storage configured so as to accumulate image data sampled from the input image signals based on the first clock using the first clock output from the first clock generator and read out the accumulated image data using the second clock output from the second clock generator, a controller for outputting control signals for controlling the cycle of output horizontal synchronizing signals at the time of reading out and displaying the accumulated image data from the storage, according to image size information of the input image signals, cycle information of the input horizontal synchronizing signals, display panel size information, and cycle information of the second clock, and a synchronizing signal generator for outputting the out

Abstract: This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user's display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved.

Abstract: A ramp generator for use in a video mixing system to produce various transition effects between edited video frames. The ramp generator produces a ramp signal R according to the equation R=Ah+Bv+C. The ramp signal R corresponds to a video frame comprised of v video lines (where v is an integer from 0 to m), each video line having h pixels (where h is an integer from 0 to n), and where A, B, and C are coefficients. Multiple ramp signals can be combined to a ‘solid’ signal. Solid signals can be used to generate masks or wipe patterns. Each ramp be edge modulated before combining into a solid signal. A solid signal can also be solid modulated.

Abstract: A PLL circuit for a CRT monitor horizontal drive signal includes a phase comparator, charge pump, LPF, VCO, frequency divider, and switching circuit. The phase comparator compares the phase of an input horizontal sync signal with that of an internal reference signal and outputs a phase difference signal. The charge pump outputs a charge pump signal in accordance with the phase difference signal. The LPF converts the charge pump signal into a voltage control signal. The oscillation frequency of the VCO is controlled in accordance with the voltage control signal output. The frequency divider frequency-divides an output from the voltage controlled oscillator and outputs a CRT monitor horizontal drive signal phase-locked by a horizontal sync signal. The CRT monitor horizontal drive signal is used to generate the internal reference signal.

Abstract: A stabilizing circuit for stabilizing a horizontal transistor of a video display device. The stabilizing circuit includes a transient state detector for detecting a transient state of a phase locked loop circuit in a horizontal drive circuit due to a change in an operation mode of a video card in a computer system. A micro-computer outputs vertical and horizontal synchronous signals with frequencies before the change in the operation mode of the video card when the transient state detector detects the transient state of the phase locked loop circuit. The transient state detector detects the transient state of the phase locked loop circuit according to a direct current level variation based on a phase difference between a horizontal synchronous signal from the micro-computer and a horizontal drive signal from the phase locked loop circuit.

Abstract: An input image signal is converted into a digital form in an A/D converter 6 by clock pulses 53 from VCO 4 of a PLL circuit 1. The frequency of the clock pulses 53 is fixed. After the number of scanning lines is converted in a primary processing circuit 7, the digital image signal is written in field memory 10. The image signal is read out from the field memory 10 by second clock pulses 63 generated in a PLL circuit 11. A frequency divider 15 in the PLL circuit 11 is changed in frequency division ratio by a control signal. As a result, the sampling number in one horizontal period of the image signal read out from the field memory 10 is changed. Since the number of pixels in the effective image period of the image signal written in the memory is constant, by changing the sampling number in one horizontal period on the read-out side, the ratio of the effective image period relative to one horizontal period can be changed to adjust the horizontal size.

Abstract: A phase lock loop (PLL) circuit has an oscillation circuit operating in synchronism with a horizontal synchronizing signal. The PLL circuit also has a DC level decision circuit for deciding the DC level of a vertical synchronizing signal during a return period, and a logic circuit for automatically selecting the oscillation circuit according to the DC level decided in the DC level decision unit. Thus, even if there is an increase in the oscillation characteristics, this PLL circuit can automatically select the necessary oscillation characteristics without a need for expanding an operation frequency of a voltage controlled oscillation circuit.

Abstract: An apparatus comprises a source of a first signal synchronized to deflection, the first signal including a first portion representative of a retrace interval, means coupled to a first video signal and responsive to a second signal representative of the retrace interval for generating a second video signal having a blanking interval, and, means responsive to a third signal representative of the blanking interval and to the first signal for generating the second signal so as to control the phase of the blanking interval relative to the retrace interval.

Abstract: A video display apparatus displays pictures from broadcast sources of standard or high definition pictures and may also display computer generated images. To display these sources a horizontal deflection signal generator is operable at a plurality of frequencies. The deflection signal generator comprises a controlled oscillator generating a output signal. A divider divides the output signal to form a horizontal frequency signal. A phase detector receives the horizontal frequency signal and a synchronizing signal and generates an analog signal for coupling to the oscillator. A digital to analog converter generates a voltage from a digital data word and couples the voltage to the oscillator. The voltage determines a center frequency of the oscillator and the analog signal controls the oscillator to synchronize with the synchronizing signal.

Abstract: A horizontal electron-beam deflector capable of preventing circuits from being damaged due to disturbance such as electric discharge with a simple and small circuit configuration, wherein an AFC circuit inputs a control signal indicating a frequency from a computer, the control signal is output to a deflection circuit, the AFC circuit generates a horizontal synchronization pulse signal, and the deflection circuit generates a horizontal deflection signal while controlling a voltage by using the control signal input from the AFC circuit.

Abstract: A cathode ray tube display apparatus having a protection circuit which cuts off supply of a synchronization signal, i.e., the horizontal and/or vertical synchronization signals, to a cathode ray tube driving circuit in response to a state signal indicating when frequencies of the synchronization signals exceed a limited range. The protection circuit prevents the cathode ray tube driving circuit from being damaged by abnormal variations in the frequencies of the synchronization signals.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A display apparatus for selecting a display mode, based on the horizontal and vertical synchronizing signals and an analog video signal supplied from a host with multiple display modes, includes a mode distinction circuit for generating first to third control signals according to a display mode received from the host, a clock signal generator for generating a pixel clock signal corresponding to the display mode in response to the first and second control signals and the horizontal synchronizing signal, a voltage controller for generating adjustment signals applied to the clock signal generator to adjust the phase and frequency of the pixel clock signal according to first/second voltages and the first/second control signals, and a switching circuit for supplying or cutting off the second control signal to the clock signal generator according to the third control signal being at a first level or a second level in response to the first voltage and the third control signal.

Abstract: A horizontal deflection circuit (61) includes a horizontal oscillator circuit (51) having a horizontal oscillation IC (1). A terminal (T12) of the horizontal oscillation IC (1) is connected to respective first ends of capacitors (8a, 8b). The capacitor (8a) has a second end grounded. The capacitor (8b) has a second end connected to a collector terminal of a transistor (9). The transistor (9) has an emitter terminal grounded through a resistor (11), and a base terminal grounded through a capacitor (13) and connected to a terminal (T121) of a microprocessor (12) through a resistor (14). The horizontal oscillation IC (1) receives a voltage (VT71) at a terminal (T13) thereof and a feedback voltage (VT31) at a terminal (T15) thereof. The circuit (51) generates a signal (VT14) synchronized with a horizontal synchronizing signal (HD) applied to a terminal (T11) to output the signal (VT14).

Abstract: An image display system reproduces a dot clock on the basis of a horizontal sync signal that is generated from a host computer and displays an image on a display unit such as a ferroelectric liquid crystal display. In the host computer, a graphic card is provided with a transmitting unit for transmitting information necessary for display. The display unit comprises a receiver to receive the information necessary for the display and a change unit to change the display contents on the basis of the information received by the receiver. The information necessary for the display includes a sync signal frequency, a dot clock frequency, and an image information display period.

Abstract: A synchronous control device is disclosed which is capable of obtaining stable synchronization regardless of the kind of image source even when the automatic synchronous control circuit cannot operate in the normal manner.The device includes a phase comparator, an integrator, a horizontal oscillation circuit, and a horizontal synchronous control circuit composed of a frequency measuring section consisting of a digital frequency measuring circuit, etc. and a control section consisting of a frequency determining circuit, an oscillation frequency control circuit, etc. The frequency measuring section measures the input horizontal synchronizing frequency and transfers it to the control section as digital data, and the control section determines the true value of the input synchronizing frequency by the frequency determining circuit while monitoring the transition of the frequency data per unit time.

Abstract: In a horizontal scanning pulse control circuit, a reference clock generation circuit generates a reference clock signal in synchronization with a horizontal synchronization signal. First and second horizontal position reference pulse generation circuits generates first and second horizontal position reference pulse signals, respectively, whose phases are different with reference to the horizontal synchronization signal and corresponding to first and second pulses of said reference clock signal. First and second saw-tooth wave generation circuits generate first and second saw-tooth wave signals in response to the first and second horizontal position reference signals, respectively. First and second comparators, compare the first and second saw-tooth wave signals with a horizontal position selection voltage to generate first and second comparison signals, respectively. An RS-type flip-flop is set and reset by the first and second comparison signals, respectively.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: A process and system for synchronizing a video signal to the sampling period of a client system. The synchronization may be suitably implemented by adding or deleting trailing lines from each frame of video data to adjust the frame to match the sampling period of the client system. The synchronization system minimizes the lag between the time a video signal is delivered to the client system and the time the client system responds. The low lag time enhances the responsiveness of the client system to human inputs, and improves the suitability of the overall system to human use. The synchronization system can be achieved using suitable low-cost hardware and is therefore particularly well suited for video game or virtual reality systems designed for home use, increasing the feasibility of employing video inputs in such systems.

Abstract: A digital horizontal flyback control circuit for controlling the horizontal position of a video signal on a monitor screen receives a horizontal drive signal (21) and a flyback signal (22) generated when a video display beam is caused to move from the end of one line of the display to the beginning of a next line by an edge of a pulse of the horizontal drive signal, the flyback pulse being delayed with respect to the horizontal drive signal pulse by a flyback delay period. A measuring circuit (15) measures the flyback delay period and a subtractor circuit (17) subtracts the flyback delay from a set horizontal position (18) representing a desired delay between the flyback pulse and a reference pulse (11). A comparator (19) compares the subtraction value with the value of a clock counter (23) whose count value is reset by the reference pulse (11) and produces a set signal at an output when the subtraction value and the clock count value are the same so as to generate the horizontal drive signal pulse (21).

Abstract: A horizontal phase detection circuit and system detects the phase of the horizontal synchronization pulse for a horizontal synchronization phase lock loop using positive and negative fractional error compensation. The positive and negative fractional errors are determined to get a more accurate detection of where a horizontal synchronization pulse crosses a synchronization signal slice level. Using both positive and negative fractional compensation, the circuit and method detects the horizontal synchronization pulse width and center of the pulse. In addition, if desired, an adaptive slice level generator generates a variable slice level threshold based on a signal strength of the input video signal to facilitate improved detection in the cases where the video information is weak even after gain control has been applied.

Abstract: A video display apparatus comprises a phase-locked loop receiving a horizontal synchronous signal for generating an oscillation signal following the frequency of the horizontal synchronous signal, a tracking circuit for generating a tracking control signal for moving the frequency of the oscillation signal into a predetermined capture range of the phase-locked loop when the frequency of the horizontal synchronous signal changes, so that the frequency of the oscillation signal follows the frequency of the horizontal synchronous signal, and an output circuit receiving and amplifying the oscillation signal to output a horizontal output signal.

Abstract: An image data processing apparatus is described that prevents the period of a horizontal timing signal from being shifted. The apparatus includes a separator, a phase-locked loop, a detector, a compensator and a timing signal generator. The detector delays a reference clock signal in a shorter period than the period of the reference clock signal, in a step-like manner, to produce a plurality of delayed timing signals having step-like phase differences. The detector further contrasts the plurality of delayed timing signals with a horizontal sync signal and the reference clock signal to measure the phase difference and the period of the horizontal sync signal. The compensator sets a ratio for combining consecutive luminance data in accordance with the phase difference and the period of the reference clock signal and combines consecutive luminance data in accordance with the ratio to generate compensated luminance data.

Abstract: A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to an encoded composite video signal. An input receiving circuit receives an encoded input video signal representing video information received from input video signals. An output video signal represents the encoded input video signal in all portions of the signal except the horizontal synchronization period. During the horizontal synchronization period a current is switched through a path resistor and used to generate the voltage level of the horizontal synchronization pulse. The voltage drop across the path resistor during the horizontal synchronization period is applied directly to the output video signal thereby generating a horizontal synchronization pulse. The current switched through the path resistor is generated by a voltage drop across a current resistor.

Abstract: A video signal processor for use in a multi-color standard color video apparatus including a horizontal synchronizing signal generator and a baseband circuit provided on a same LSI chip as a video signal processor. The baseband circuit includes a switched capacitor filter having a switched capacitor array. A driving pulse generator for driving the switched capacitor filter is included on the same LSI chip and synchronizes to horizontal signals in a received video signal of a particular color-standard.

Abstract: A method of, a device for, and a storage medium for recovering horizontal synchronization from a TV-signal with the use of a PLL. The number of periods during which a predetermined degree of synchronization persists is counted and the result of the counting decreases the bandwidth of the PLL when the number of periods increases.

Abstract: A display control apparatus for forming dot clocks for display corresponding to a video signal from a first sync signal and executing a display control is constructed by a comparator for comparing the first sync signal and frequency division signals, a clock forming circuit for forming the dot clocks for display on the basis of a result of the comparator, a memory in which frequency division parameters of the dot clocks for display have been stored, a frequency division signal forming circuit for forming the frequency division signals from the frequency division parameters and the dot clocks for display, a counter for counting the first sync signal, and a changing circuit for changing the frequency division parameters stored in the memory in the case where a count value of the counter reaches a predetermined value.

Abstract: A clock signal generator and method for generating a clock signal which is synchronized with an input composite video signal. The generator comprises a synchronizing separator for separating a horizontal synchronizing signal from an input composite video signal; a burst separator for separating a color burst signal from the input composite video signal; a phase error detector for receiving the horizontal synchronizing signal, detecting a phase error and outputting a phase error signal for a previous horizontal period; a phase change detector for receiving the color burst signal, detecting a phase change of the color burst signal, and outputting a phase change signal for a present horizontal period; an adder for adding the phase error signal and the phase change signal; and a clock signal generator for receiving an output of the adding means and generating a clock signal which is synchronized with the input composite video signal.

Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a display clock signal on the basis of the frequency of the horizontal synchronizing signal. The frequency of the display clock signal is frequency-divided in accordance with a frequency-dividing value selected from among a plurality of frequency-dividing signals stored in advance, the difference in frequency between the frequency-divided display clock signal and the horizontal synchronizing signal and the phase difference between them are obtained by a phase comparator, and the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the reference signal and the horizontal synchronizing signal input to the phase comparator are held fixed to prevent a fluctuation in the outputted display clock.

Abstract: A horizontal synchronization signal generating circuit self-generates a horizontal synchronization signal if an actual horizontal synchronization signal fails to be detected in a composite video signal. Each time an edge-detection circuit detects an actual horizontal synchronization pulse, a counter and decoder are reset. An actual horizontal synchronization signal has a period of 63.5 .mu.s. If the edge detection circuit fails to detect the actual horizontal synchronization signal, then the decoder outputs a self-generated horizontal synchronization signal at 64 .mu.s and a selector circuit disables the edge detection circuit for approximately 35 .mu.s. In contrast, if the edge-detection circuit detects an actual horizontal synchronization signal, the decoder is reset before it can output the self-generated signal and the selector disables the edge detection circuit for approximately 60 .mu.s. Accordingly, a period of 35 .mu.

Abstract: A matrix addressable display includes a delay locked loop formed from a delay chain formed from several variable delay blocks and a comparator. The delay locked loop receives a horizontal sync portion of an image signal and propagates the horizontal sync through the chain of delay blocks. The output of the last delay block drives the comparator that also receives an undelayed horizontal sync component. The comparator compares the undelayed horizontal sync to the delayed horizontal sync component and produces an error signal corresponding to the phase difference. The error signal is input to each of the delay blocks. In response to the error signal, the delay of the respective delay blocks increases or decreases to reduce the phase difference between the undelayed horizontal sync component and the delayed sync component. In addition to driving the delay chain, the horizontal sync component also walks a "1" through a row driver to sequentially activate rows of the array.

Abstract: Receiving an instruction designating a frequency f by an MPU (1), a programmable clock generator (2) generates a dot clock D which has the frequency f. The dot clock D and a horizontal synchronizing signal H having a cycle T.sub.H are supplied to a counter (3). The counter (3) counts the number N of activations of the dot clock D during the cycle T.sub.H. The activation number N is supplied to a comparator (4), together with a predetermined number K which is designated by the MPU (1). The comparator (4) compares these numbers and supplies a comparison result C to the MPU (1). The MPU (1) updates the frequency f, in accordance with the comparison result C.

Abstract: An H-sync to pixel clock phase detection circuit comprising: a programmable delay line for delaying an H-sync signal; a differential clock driver circuit for producing a pixel clock signal and a pixel clock/signal from a pixel clock signal input; a first D flip-flop having D and CLK inputs and a Q output; a second D flip-flop having D and CLK inputs and a Q output; wherein the delayed H-sync signal from the programmable delay line is applied to the respective D inputs of the first and second D flip-flops, wherein the pixel clock signal from the differential clock driver circuit is applied to the CLK input of the first D flip-flop, and wherein the pixel clock/signal from the differential clock driver is applied to the CLK input of the second D flip-flop; and a third D flip-flop having D and CLK inputs and a Q output; wherein the Q output of the first D flip-flop is applied to the D input of the third D flip-flop, wherein the Q output of the second flip-flop is applied to the CLK input of the third D flip-flop;

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.snyc) that controls a line scan rate, and a vertical synchronizing signal (V.sub.snyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: A color subcarrier signal generator for use e.g, in a video converter measures the average error of the horizontal synchronizing signal frequency. The measured error is used as a compensator signal to control a direct digital synthesizer to generate a correct color subcarrier signal. The direct digital frequency synthesizer includes an address generator receiving the error signal and a look up table driven by the address generator.

Abstract: A frequency detection circuit detects the frequency of a horizontal sync signal, and generates a mode switching signal corresponding to the detected frequency. A voltage-controlled oscillator constituting a PLL circuit has a plurality of oscillation modes obtained by dividing a frequency equal to an integer multiple of the frequency of the horizontal sync signal into a plurality of frequency ranges, and oscillates signals in the respective frequency ranges in accordance with control voltages output from a filter. The oscillation modes of the voltage-controlled oscillator are switched in accordance with the mode switching signal output from the frequency detection circuit. In the voltage-controlled oscillator, since the frequency range in each oscillation mode is narrow, the oscillation gain can be suppressed low, and a deterioration in jitter characteristics can be prevented.

Abstract: The process consists in carrying out, via a phase-locked loop controlling a clock frequency, a slaving of a comparison signal to the falling edge of the line synchronization pulse, in decoding at the output of a dot counter integrated into the loop and controlled by the clock, on the one hand a value N triggering the comparison signal and corresponding to a specified position inside the line synchronization pulse relative to its falling edge, on the other hand values triggering the rezeroing of the counter and time signals synchronous with the clock and clocking the digital processing of the video signals sampled at the clock frequency.

Abstract: A horizontal synchronizing apparatus includes a source for providing a horizontal synch. signal, a horizontal deflection circuit for generating a deflection current having scanning intervals and blanking intervals repetitively successing in response to driving pulses and having retrace pulses which delay from the driving pulses as a function of a load on the horizontal deflection circuit, a phase locked loop having an input, an output and a first feedback path, for producing from the output a substantial bi-level signal synchronized to the horizontal synch. signal applied to the input, and a phase controlled loop having an input, an output and a second feedback path, for maintaining the retrace pulses synchronous with the bi-level signals.

Abstract: A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.

Abstract: A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.

Abstract: In an automatic frequency control circuit for synchronizing a horizontal deflection current of a television receiver with a horizontal sync signal, a bi-level signal which assumes either of two levels when the flyback pulse is or below a threshold value is produced, and a wider sync signal in synchronism with the horizontal sync signal and having a pulse width wider than the horizontal sync signal and equal to an odd multiple of the operating clock period is also produced. A phase comparator detects the difference in the number clock periods between a period period from a leading edge of the wider sync signal to an edge of the bi-level signal, and a period from the edge of the bi-level signal to a trailing edge of the wider sync signal. The detected difference is used to control a VCO. In an alternative configuration, a digital signal indicative of a magnitude of the flyback pulse during its rising or falling slope at an edge of the horizontal sync signal is produced and used for control of the VCO.

Abstract: To interface a video/graphic controller, which produces conventional, ana video output signals, suitable mostly for CRT type displays, to a matrix display, one of the video output signals, for example the horizontal sync signal, is encoded with the clock frequency and phase information used in generating the original video output signals. The encoded information is decoded at the display end, by extracting from it the clock information and synthesizing a clock signal which has the identical frequency and phase as the original clock used at the video/graphic controller. The replicated clock signal is used as a clock input to the matrix display, to assure that the video output signals are displayed at the correct pixel locations of the matrix display, preventing picture jitter and/or loss of video/graphics data.

Abstract: An automatic phase control apparatus for controlling the frequency of a sine wave produced from a variable frequency oscillator to be equal to that of the carrier wave of the extracted chrominance signal. A phase difference detector 4 detects a phase difference between the sine wave and the carrier wave. The detected phase difference is integrated to obtain an integrated value which is applied to the frequency oscillator for determining the oscillation frequency. A deviation detector is provided for detecting a deviation of the integrated value with respect to an expected frequency control data calculated by a calculator. When the deviation is greater than a predetermined range, the integrated value is replaced with the calculated data.

Abstract: In an automatic frequency control circuit for synchronizing a horizontal deflection current of a television receiver with a horizontal sync signal, a bi-level signal which assumes either of two levels when the flyback pulse is or below a threshold value is produced, and a wider sync signal in synchronism with the horizontal sync signal and having a pulse width wider than the horizontal sync signal and equal to an odd multiple of the operating clock period is also produced. A phase comparator detects the difference in the number clock periods between a period period from a leading edge of the wider sync signal to an edge of the bi-level signal, and a period from the edge of the bi-level signal to a trailing edge of the wider sync signal. The detected difference is used to control a VCO. In an alternative configuration, a digital signal indicative of a magnitude of the flyback pulse during its rising or falling slope at an edge of the horizontal sync signal is produced and used for control of the VCO.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: A display apparatus for receiving a picture signal having video and synchronizing components includes a matrix of display cells arranged in an array of M columns by N rows. Display cells in the matrix are individually addressable by row and column signals so as to receive the video component of the picture signal in response thereto. A first shift circuit coupled to the matrix provides the column signals in response to a first clocking signal. A second shift circuit coupled to the matrix provides the row signals in response to a second clocking signal. A synchronizing detector or gate circuit coupled to the first and second shift circuits receives the synchronizing component of the picture signal and produces the second clocking signal in response to a preselected pointer signal from the first shift circuit. A phase locked loop circuit coupled to the first shift circuit receives the second clocking signal and produces the first clocking signal in response thereto.

Abstract: Disclosed herein is an oscillator circuit used for a PIP system which displays a child picture image without distortion even when the image method of the child picture image is different from that of a parent picture image. The oscillator circuit employed in such a system includes a programmable frequency divider for frequency dividing an output of a voltage-controlled oscillator with a frequency dividing ratio to produce a frequency-divided signal and a control circuit for controlling the oscillation frequency of the oscillator 201 according to a phase difference between the frequency-divided signal and a horizontal synchronizing signal. The frequency dividing ratio for the frequency divider is changed according to the image method of the child picture image.

Abstract: The synchronized transformer-coupled power supply circuit includes a transformer 20; an input power signal coupled to a primary winding 22 of the transformer 20; voltage regulators 48-53 coupled to secondary windings 24 and 26 of the transformer 20; and a start-up circuit 10 for coupling the input power signal directly to one of the voltage regulators 48-51 until the transformer 20 reaches a desired operating level.

Abstract: A video display system comprises a video display for simultaneously displaying pictures representative of first and second video signals, having first and second synchronizing signals respectively. A switch selectably couples the video display with one of the first and second synchronizing signals. A horizontal synchronizing component of the first synchronizing signal is detected by a sensing circuit, the switch being responsive to the sensing circuit. The video display is synchronized with the first synchronizing signal when the horizontal synchronizing component of the first video signal is sensed and is otherwise synchronized with the second synchronizing signal.