Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.

Abstract: In a sync processor for determining safety of signals on the basis of a horizontal/vertical sync signal generated according to a data enable signal, the sync processor includes a digital horizontal/vertical signal generator, a selector, a digital horizontal/vertical signal detector, a horizontal/vertical polarity determination unit, and a horizontal/vertical frequency determination unit. The digital horizontal/vertical signal generator generates a digital horizontal/vertical sync signal from the data enable signal. The digital horizontal/vertical signal detector detects a signal received from the selector and generates a digital horizontal/vertical signal. The horizontal/vertical polarity determination unit counts the number of low and high durations of a horizontal/vertical sync signal and generates a horizontal/vertical polarity signal in response.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: A H-sync phase locked loop device for TV video signal is provided herein. After the TV video signal is digitalized, clamping and slicing operations are performed on the digitalized TV video signal to respectively generate a clamped signal and a sliced signal. According to the clamped signal and the sliced signal, an H-sync frequency calculator can calculate the falling and rising transients of the H-sync signal and an H-sync frequency is obtained therefrom. Because the H-sync frequency is dynamically adjusted according to the input TV video signal, the phase locking of the input TV video signal can tolerate more deviations of the H-sync by replacing a predetermined H-sync frequency.

Abstract: A circuit and method for clamping a composite video component signal at the video black level by using horizontal synchronization timing information contained within the signal and clamping the signal during a time interval in which it is at the desired black level.

Abstract: A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing count value, a trial window signal is created and the counter is reset. If a predetermined number of subsequent sync pulses occur within the trial window signal, the sync spacing count value is confirmed and stored in a sync spacing register. The windowing circuit includes a counter that generates a count value proportional to the duration between successive window signals, and compares the count value to the value stored in the sync spacing register to generate a window signal. The window signal is compared with the sync signal pass valid sync signals.

Abstract: In a liquid crystal television, a display controller prevents burning of a liquid crystal panel due to irregularity in a synchronization signal. A counter of a liquid crystal display controller detects a period of a horizontal synchronization signal and a vertical synchronization signal. A comparator compares a count value with a predetermined minimum value Min and maximum value Max. When the count value is out of a range, a synchronization pulse generator generates a synchronization pulse at a time when the period falls within a predetermined range. A selector outputs an input synchronization signal when the period is within the range and outputs the synchronization pulse obtained from the synchronization pulse generator when the period is out of the range.

Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: A method for obtaining line synchronization information items from a video signal is proposed. The inventive method is based on convolving the relevant part of an analogue video line signal with a pattern function. The result of the convolution operation is further processed to determine the time instants of the occurrence of the horizontal sync signals. The time instants are subsequently filtered to generate horizontal pulses. A video line memory allows to utilize subsequent horizontal sync signals for calculating the horizontal sync pulse of a current video line. The invention also relates to an apparatus for carrying out the method.

Abstract: The invention provides an image display apparatus that efficiently adjusts a video display even when a change takes place in an input signal. The image display apparatus includes a video input device that receives a video signal, a video display that displays an optical image based on an input signal S1 from the video input device, and a video signal adjusting device that adjusts the display setting of the video display based on a signal mode of the input signal S1. The image display apparatus further includes a determining device that causes the video display adjusting device to adjust the display setting of the video display. The determining device includes an apparatus startup detector unit that detects whether a startup of the image display apparatus creates a change in the input signal, and a signal change detector unit that detects the change in the input signal. The determining device determines whether to cause the video display adjusting device to adjust the display setting only when it is needed.

Abstract: A method for providing a horizontal scan control signal for a TV set from a horizontal synchronization signal contained in a composite video signal, the horizontal synchronization signal containing horizontal synchronization pulses and parasitic pulses, the scan control signal being provided from an oscillating signal generated by an oscillator of a phase-locked loop receiving the horizontal synchronization signal, the oscillating signal having a frequency depending on a driving signal provided from the comparison between the horizontal synchronization signal and a binary phase signal, in which, at each parasitic pulse among successive parasitic pulses between two synchronization pulses, the driving signal is successively varied in the increasing direction or in the decreasing direction.

Abstract: A video signal reproducing apparatus and method for adjusting a change in a horizontal synchronous signal. The video signal reproducing apparatus transforms a format of an input video signal, generates horizontal and vertical synchronous signals, and displays the video. The video signal reproducing apparatus includes a measurer, a comparator, and an adjustor. The measurer measures a period of the horizontal synchronous signal, the comparator compares the measured period of the horizontal synchronous signal with a predetermined reference range, and the adjustor adjusts a period of a clock signal for producing the horizontal synchronous signal, if the measured period of the horizontal synchronous signal fails to fall within the predetermined reference range.

Abstract: The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).

Abstract: Methods and systems are described for determining a slice level used for detecting an edge of a horizontal sync pulse of a horizontal line of a video signal, where the horizontal line has a plurality of samples. An exemplary method comprises low-pass filtering the video signal to generate a plurality of filtered samples; determining a first level, wherein a predetermined number of the plurality of filtered samples have levels above the first level; determining a second level, wherein the second level is a minimum level of levels for the plurality of filtered samples; and determining the slice level by adding the first level and the second level to generate a summed level, and dividing the summed level by two to determine the slice level.

Abstract: A method and apparatus for estimating a true horizontal resolution by determining a temporal spacing of a cumulated sum pattern of a detected rising feature edge. If the temporal spacing is approximately equal to n (which is a positive, non-zero integer, and is equal to the number of sub-pixels associated with a pixel) then the estimated horizontal resolution is the true horizontal resolution.

Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

Abstract: A display system is provided that reduces electromagnetic emissions of at least one frequency component of a signal in the display system. A signal that drives a display is modulated so that one or more frequency components of the driving signal are attenuated due to the modulation of the signal. In one embodiment, an LCD controller is adapted to provide a modulated row driving signal to an active matrix LCD. The input data source may be adapted to accommodate the modulated display driving signal. Alternatively, a FIFO buffer is used to buffer input data to accommodate the modulated display driving signal. In a further embodiment, a clock modulating circuit is provided to modulate the display driving signal without modifying the display controller.

Abstract: A method and apparatus for providing adaptive horizontal synchronization (sync) signal detection to identify whether a high quality television signal is being received by a television set. The method determines whether no signal is applied, whether a weak signal is applied or a strong signal is applied to the television set by sampling and processing the horizontal synchronization signal. The signals are classified by comparing the sample horizontal synchronization signals to a predefined threshold. The threshold is established based upon the type of source that produced the television signal.

Abstract: A method of automatic generation of horizontal synchronization of an analog signal to a digital display is described. Accordingly, a number of features are found and for each of a range of test Htotal values, a pixel co-ordinate value for each of the found features is calculated. A pixel co-ordinate remainder value associated with each of the pixel co-ordinate values is determined and a maximum gap value of the pixel co-ordinate remainder values associated with a true horizontal resolution. is determined.

Abstract: A method to generate an optimum phase shifted sampling clock for sampling a synchronized video signal A(t) having a synchronization signal SYNC pulse is achieved. The method comprises, first, generating a sampling clock having a first edge aligned with a trailing edge of the SYNC pulse. The sampling clock period comprises the SYNC pulse period divided by M. Second, the number of sampling clock cycles N is counted from the trailing edge of the SYNC pulse until the A(t) value at the first edge of the sampling clock exceeds a minimum value. Third, the sampling clock and the SYNC pulse are phase shifted forward until the A(t) value at the first edge of the sampling clock first exceeds a minimum value on clock cycle N?1 to thereby establish a worst case phase shift of the sampling clock. Finally, A(t) is sampled at an offset from the worst case phase shift to thereby generate an optimum phase shifted sampling clock.

Abstract: The object of the invention is to provide a video switchover detection circuit that reduces the circuit scale and allows high-accuracy detection with a smaller-scale configuration. According to the invention, the video switchover detection circuit comprises a PLL circuit composed of a phase comparator, an LPF, a VCO, and a frequency divider. In the phase comparator, the phase of an external HD as an input signal obtained by shaping the pulse of a horizontal synchronization signal is compared with the phase of an internal HD as a reference signal obtained by dividing the frequency of the output pulse of the VCO in the PLL circuit. In case the phases of the signals differ from each other, an error signal is output from the phase comparator. A first counter counts the period in which the error signal is active, or the time when the phase difference persists.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment incsc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by ?h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nomimal increment (nom_incsc) and a feed forwarded scaled version of ?h.

Abstract: An apparatus and method of interfacing video information which can provide an accurately displayed video picture irrespective of the type of a video input signal by interfacing the video display information between a main body and a monitor, and thus maintaining the optimum picture state. The apparatus includes a main body for outputting a video signal and information on a display type of the video signal, and a monitor for detecting the display type of the corresponding video signal in accordance with the display type information outputted from the main body and displaying on a display screen the video signal outputted from the main body to match the detected display type.

Abstract: An inexpensive and simple circuit for improving an image quality of a dynamic image, with appropriate processing flexibly performed for dynamic image qualities also for a plurality of input signal sources.

Abstract: For horizontal sync information HD suitable for use in image processing module, e.g., module for TBC features, image compression recording/playback features, and LCD displaying features, it would be desirable that the time base fluctuations of the video input signal is faithfully reflected and that an interpolated HD generating feature is provided. A module for generating pulses generates the trailing edges of Csync as the trailing edge HD, and switches to an interpolated HD when a dropped pulse is detected after a few microseconds delay in the leading edge relative to the standard pulse. Thus, the trailing edge HD is selected within a time base fluctuation on the order of a few microseconds and the time base fluctuation is faithfully reflected and interpolation features can also be provided.

Abstract: A system for overlaying a motion video signal onto an analog signal on a display. The system includes a motion video processing unit for receiving and processing the motion video signal into a signal having an analog video format, a video format analyzer and synchronizer device for receiving the analog signal and for determining video timing parameters and a corresponding original pixel clock of the analog signal and for controlling video timing parameters of the motion video signal to match the video timing parameters of the analog signal determined by the video format analyzer and synchronizer device so as to provide an output motion video signal which is synchronized with the analog signal and a display determining device for determining the display of the analog output signal or the synchronized output motion video signal on the display.

Abstract: A first PLL circuit (100) receives a flyback pulse (VFB) as a reference signal and outputs a clock signal (CLK1), and a delay circuit (200) outputs a flyback delay signal (VFBD) having a predetermined delay time corresponding to the amount of horizontal movement on a screen. A second PLL circuit (300) receives a horizontal synchronizing signal (VHSYNC) and the flyback delay signal (VFBD) as a reference signal and a compared signal, respectively, and generates a horizontal drive pulse (VHD). A deflection yoke (12) receives the horizontal drive pulse (VHD) and generates a flyback pulse, and a step-down transformer circuit (16) outputs the flyback pulse (VFB) whose voltage is lowered. With this constitution, it becomes possible to generate a stable horizontal drive pulse which causes no jitter on the screen when a PIN balance correction, a KEY balance correction and a horizontal position adjustment of a CRT are performed by digital processing.

Abstract: A fly-back pulse width adjustment circuit and a method for adjusting the width of a fly-back pulse which are applied to a video signal processing unit realized as one chip are provided. The fly-back pulse width adjustment circuit is built into a video signal processing unit including a video amplifier, an on screen display unit, and a horizontal/vertical synchronous signal processing unit within the video signal processing unit realized as one chip.

Abstract: A simulated burst gate signal and a video synchronization key are generated. A video decoder generates a horizontal sync pulse which is programmed to envelop a color burst, thereby simulating a burst gate signal. The offset to the horizontal sync pulse due to simulating a burst gate signal may be compensated at a video memory subsystem receiving the horizontal sync signal, in order to determine when active pixels are provided by the video decoder. Alternatively, counter circuitry external to the video decoder may be used to generate a simulated burst gate signal by counting the number of pixel clock cycles between the horizontal sync pulse and the color burst. Unlike a burst gate signal generated within a video decoder for use with color separation circuitry in the video decoder, a simulated burst gate signal allows for use of color separation circuitry external to the video decoder. Detecting a color burst using external color separation circuitry is thus also disclosed.

Abstract: The invention provides an image display apparatus that efficiently adjusts a video display even when a change takes place in an input signal. The image display apparatus includes a video input device that receives a video signal, a video display that displays an optical image based on an input signal S1 from the video input device, and a video signal adjusting device that adjusts the display setting of the video display based on a signal mode of the input signal S1. The image display apparatus further includes a determining device that causes the video display adjusting device to adjust the display setting of the video display. The determining device includes an apparatus startup detector unit that detects whether a startup of the image display apparatus creates a change in the input signal, and a signal change detector unit that detects the change in the input signal. The determining device determines whether to cause the video display adjusting device to adjust the display setting only when it is needed.

Abstract: A synchronous signal separation circuit 2 for separating horizontal synchronous signal HSn is connected to a horizontal synchronous signal detection circuit 3, which includes a switch 4, an oscillator 5 and a window signal generator 6 for generating a window signal WP. The switch 4 passes the separated horizontal synchronous signal HSn during an open-period of the window signal WP and intercepts the separated horizontal synchronous signal HSn during a close-period of the window signal. The oscillator 5 generates a rate signal having a period equal to a horizontal scan period synchronously with a change in an output signal HS from the switch circuit, and adjusts a time duration of the open period of the window signal so as to make a timing of a change in the output signal HS coincide with a generation timing of the rate signal while the open-period of the window signal is synchronized with the generation timing of the rate signal.

Abstract: A horizontal automatic frequency control (AFC) used in a display having a display device such as a cathode ray tube (CRT) is provided. The AFC circuit reduces a horizontal distortion and horizontal jitter on the CRT. The AFC circuit includes a video signal processor for demodulating and converting an input video signal into a desired signal such as a YUV signal or an RGB signal, a synchronous separator for separating a synchronizing signal from the video signal, a dual-port line memory, an Hout generator for generating a horizontal driving pulse which drives a horizontal deflection yoke, a read clock generator for generating a read clock (RCK) signal which is synchronized in phase with a flyback pulse, and a horizontal deflection driver for controlling horizontal deflection of the CRT and generating the flyback pulse. The line memory absorbs a horizontal position change of a displayed image caused by a temperature change or a load change in the horizontal deflection driver.

Abstract: A PLL circuit according avoids any large change in a frequency in a VCO (5) even if an input horizontal synchronization signal suddenly changes or a level of the frequency decreases to a predetermined value or less, or disappears. The PLL circuit comprises a switch (3) to be provided on an output side of a phase comparator (2) to control an output voltage of the VCO by connecting to an AFC filter (4) and supplying a phase difference current according to a phase difference, during the time the horizontal synchronization signal is supplied. The comparator (2) compares a phase of an Hin signal through a delay circuit (1) with a phase of a return (RET) signal through a dividing circuit (6) and a delay circuit (7) from the VCO. With this structure, the comparator does not supply any phase difference current and does not make the VCO change at the time when the Hin signal is disappeared.

Abstract: In accordance with one embodiment of the invention a spread spectrum pixel clock signal is generated to spread out the frequency bandwidth within which the peak emission of an electromagnetic interference signal occurs, so as to decrease the peak electromagnetic emission level. In one embodiment of the invention, this objective is accomplished by employing the horizontal synchronization signal of a video image to generate a periodic waveform that modulates the pixel clock reference input, such that clock signal pulses are spread out within each scan line. The modulation signal is synchronized with the horizontal synchronization signal such that each pixel location remains consistent in the horizontal and time domain.

Abstract: A video signal processor reduces the deterioration of image quality due to the superposition of noise on a sync signal included in a luminance signal. A frequency discriminator outputs a first error signal if a ratio of the frequency of a frequency-modulated signal during a sync-signal interval to the frequency of a reference frequency signal is smaller than a predetermined ratio. Alternatively, the discriminator outputs a second error signal if the ratio is greater than the predetermined ratio. If the first error signal has been input to a frequency controller a preset number of times or more during an interval before the second error signal is input thereto, the controller instructs a frequency modulator to increase the frequency of the frequency-modulated signal.

Abstract: There can be solved a problem in which a lock range is narrowed by using an oscillator such as a ceramic having a high Q and a horizontal deflection frequency generating system compatible with all horizontal deflection frequencies of a variety of television systems cannot be formed without difficulty. This system includes a frequency-fixed oscillator oscillating at a frequency f0 sufficiently higher than a deflection frequency fh in a multi-scan display, a first counter for counting a clock outputted from said oscillator in a descending order, a duration in which an integer n which results from rounding a decimal point of a value obtained by a division of f0 fh is divided by an integer m smaller than n and said first counter counts a value k thus obtained k times is set to one cycle and a duration in which a second counter for counting a value m times repeats the counting m cycles is set to one period and thereby generating a deflection frequency fh.

Abstract: A phase controller of a horizontal drive pulse fed into a horizontal deflection circuit supplying a horizontal deflection pulse, and a control method of the same are disclosed. A frequency discriminator identifies a format of video-input-signal by detecting a frequency of the horizontal sync signal. A reference phase generator generates a reference phase signal based on the output from the frequency discriminator. A sawtooth waveform generator generates a sawtooth waveform signal responsive to the output from the frequency discriminator. A phase difference voltage detector outputs a phase difference voltage responsive to the phase difference between the reference phase signal and the horizontal deflection pulse. A phase control signal generator generates a phase control signal using the phase difference voltage and the sawtooth waveform signal. Horizontal drive pulse generator outputs a horizontal drive pulse having a phase responsive to the phase control signal.

Abstract: A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a phase detector for generating a first control voltage responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.

Abstract: To provide a video signal transmission apparatus capable of correctly transmitting a digital video signal. A PLL circuit 5 has a first cutoff frequency lower than the frequency of a horizontal synchronization signal contained in a digital video signal S9. has the characteristics of causing attenuation of a signal of the frequency higher than the first cutoff frequency, performs PLL processing for a dot clock signal S14 for identifying one pixel's worth of data of the digital video signal S9, and generates a transmission clock signal 55 of the frequency N (integer of 2 or more) times the first dot clock signal S14. The PLLL circuit 6 has a second cutoff frequency higher than the frequency of the horizontal synchronization signal, tracks a signal of a frequency lower than the related second cutoff frequency, performs the PLL processing on the serial signal S2 input via the transmission cable 4, and generates a transmission clock signal S6.

Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.

Abstract: A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses.

Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Abstract: An apparatus and method for extracting vertical (V-SYNC) and horizontal (H-Blank) sync signals from a digital composite sync signal (C-SYNC) of a master video source for use in controlling a second video source, which allows for an adjustable delay relationship between the C-SYNC from the master source and the generated H-Blank. The present invention also provides a system and method for varying the responsiveness or gain of the genlocking circuit used to synchronize the system pixel clock frequency of the second video source to that of the master video signal.

Abstract: An apparatus and method for correcting jitter components of a television system which can be generated by an asynchronous signal applied externally as well as a truncation error are described. In the apparatus for correcting jitter of a television system having a horizontal driving signal generator for generating a horizontal driving signal in response to a system clock signal and a first synchronous signal, a first phase difference detector detects a first phase difference between the system clock signal and a second synchronous signal, the second synchronous signal being input from the outside of the television system, asynchronous with the system clock signal, and able to be set as the first synchronous signal. A jitter corrector corrects a jitter component included in the horizontal driving signal in response to the first phase difference and outputting a horizontal driving signal the jitter component of which is corrected.

Abstract: A computer system includes a graphics controller with a first refresh rate and a first horizontal synchronization signal; a secondary source of video data having a second refresh rate and a second horizontal synchronization signal; and a genlock unit for reconciling the first refresh rate of the graphics controller with the second refresh rate of the secondary source. The genlock unit outputs a clock signal with a frequency modulated to reconcile the first refresh rate and the second refresh rate by monitoring the phase differences of the first horizontal synchronization signal and the second horizontal synchronization signal in response to a first control signal and outputs a clock signal at a frequency corresponding to a selected clock frequency in response to a second control signal.

Abstract: The invention concerns a method for determining the quality of a video and/or television image signal. In diversity reception installations comprising several receivers, it is necessary to establish a criterion for assessing the reception signals, so as to select the receiver with the best reception. In order to determine the quality of a television image, the interfering impulses appearing in a line after a horizontal synchronization impulse are detected then their parameters are evaluated. The invention is applicable to television receivers, video recorders, diversity reception installations, in particular for mobile installations.

Abstract: A deflection apparatus capable of generating a stable deflection pulse in a deflection output circuit even when turning on the power source or changing over the frequency of horizontal synchronizing signal is disclosed. A pulse width modulation (PWM) controlled power supply circuit generates a supply voltage for obtaining a desired horizontal amplitude depending on the frequency of horizontal synchronizing signal. The PWM voltage controller discriminates the frequency of horizontal synchronizing signal, and controls the output voltage of the PWM controlled power supply circuit. An oscillation frequency switching controller discriminates the frequency of horizontal synchronizing signal, and outputs a frequency changeover signal to an oscillator so as to be an optimum oscillation frequency depending on the output voltage of the PWM controlled power supply circuit.

Abstract: For horizontal sync information HD suitable for use in image processing means, e.g., means for TBC features, image compression recording/playback features, and LCD displaying features, it would be desirable that the time base fluctuations of the video input signal is faithfully reflected and that an interpolated HD generating feature is provided.

Abstract: A horizontal display size compensation circuit for a monitor prevents a horizontal display size of a monitor screen from being changed when a horizontal frequency varies according to a video mode. A horizontal frequency is generated by a horizontal frequency generation section corresponding to each video mode. A microcomputer generates a predetermined horizontal display size compensation signal according to the horizontal frequency corresponding to each video mode and a horizontal display size adjustment signal corresponding to an input of a key input section, and a horizontal display size control section controls a horizontal display size of the monitor screen by supplying the horizontal display size adjustment signal of the microcomputer and the horizontal display size compensation signal to the horizontal frequency. Therefore, a horizontal display size of a monitor screen is prevented from varying according to a video mode.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsnyc) that controls a line scan rate, and a vertical synchronizing signal (Vsnyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.