Abstract: A multilayer chip varistor comprises a multilayer body and a pair of external electrodes formed on the multilayer body. The multilayer body has a varistor section and a pair of outer layer sections disposed so as to interpose said varistor section. The varistor section comprises a varistor layer developing a voltage nonlinear characteristic and a pair of internal electrodes disposed so as to interpose the varistor layer. The pair of external electrodes are connected to respective electrodes of the pair of internal electrodes. The relative dielectric constant of the outer layer sections is set lower than the relative dielectric constant of the region where the pair of internal electrodes in the varistor layer overlap each other.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first to fourth inner electrodes are alternately arranged, and first to fourth terminal electrodes formed on side faces of the multilayer body. The multilayer capacitor has a first capacitor portion including first and second inner electrodes, and a second capacitor portion including third and fourth inner electrodes and exhibiting a capacitance different from that of the first capacitor portion. The first inner electrodes are electrically connected to respective ones of the plurality of first terminal electrodes through lead conductors, whereas the second inner electrodes are electrically connected to respective ones of the plurality of second terminal electrodes through lead conductors. The third and fourth inner electrodes are electrically connected to the third and fourth terminal electrodes through lead conductors, respectively.

Abstract: A fused or high ESR ceramic capacitor for power applications has a fuse or resistor inserted between an end termination and a terminal for one set of alternating conductive plates in the capacitor. The length and thickness of the fuse allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application defining the added ESR for the capacitor.

Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.

Abstract: A decoupling module for decoupling high-frequency signals from A power supply line, the module including a layer (30) of dielectric material which is arranged between a first and a second metallic layer (20, 22), where the first metallic layer (20) is connected as a ground electrode of the decoupling module and the second metallic layer (22) includes at least two surfaces of different size which are consecutively electrically connected between an input connection point and an output connection point, while two respective consecutive surfaces are connected to each other by only one conducting section.

Abstract: Improved method steps for terminating multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrode and dielectric layers are provided in an interleaved arrangement and selected portions of the electrode layers are exposed. Electrically isolated anchor tabs may optionally be provided and exposed in some embodiments. Termination material is then plated to the exposed portions of the electrode layers until exposed portions of selected such portions thereof are connected. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: A capacitor module incorporating a ceramic capacitor having terminal members for reducing stress caused by thermal stress or electrostriction in the ceramic capacitor itself, and a semiconductor device using the capacitor module. The capacitor module and the semiconductor device are designed to have a reduced size and improved reliability.

Abstract: Some embodiments of the present invention include capacitors with controlled resistance.

Abstract: An electroceramic component includes a base body, contact layers on the base body, a dielectric layer in the base body that includes a single-phase perovskite ceramic having a composition of Ag(Nb1-xTax)O3, and an electrode layer in the base body containing a precious metal. The electrode layer is sintered with the dielectric layer.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers are laminated, and first to fourth outer conductors formed on the multilayer body. The multilayer body includes first to fourth inner conductors. The first and second inner conductors have respective regions opposing each other with at least one dielectric layer in between. The first and second inner conductors are connected to the third and second outer conductors respectively. The third inner conductor is connected to the first and third outer conductors, and the fourth inner conductor is connected to the second and fourth outer conductors. Two outer conductors and the remaining two outer conductors are respectively formed on first and second side faces of the multilayer body which oppose each other and are parallel to an opposing direction of the first and second inner conductors.

Abstract: An electronic component includes plural elements, a pair of terminal sections provided to each one of the elements, and a packaging material covering the elements and parts of the terminal sections. A non-conductive shielding section is provided between the terminal sections led outside the packaging material. The presence of the shielding section allows the electronic component to downsize the electronic apparatus, embody a greater density in mounting, and eliminate adverse influence to the apparatus for achieving higher performance as well as improving the durability.

Abstract: An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

Abstract: A capacitor has at least one plate of a first polarity and at least two plates of a second polarity, with a terminal electrically connected to the at least two plates of the second polarity such that the electrical plate connections are remote from an edge of the connected plates.

Abstract: A semiconductor device is disclosed which has a plurality of unit capacitive elements. At least one lead-out electrode of bottom electrodes of the unit capacitive elements of the capacitive element group is disposed along a circumference going around top electrodes as a whole of the capacitive element group, and a given capacitive element is connectable to the capacitive element group, the given capacitive element having a capacitance value that is set to eliminate effects of parasitic capacitance of at least the capacitive element group. Furthermore, the given capacitive element may consist of a capacitive element group.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.

Abstract: A capacitor structure is provided that includes a substrate, a first group of conducting strip, a second group of conducting strips, a third group of conducting strips, and a fourth group of conducting strips. The capacitor structure can further include a first set of vertical vias, a second set of vertical vias, a third sect of vertical vias and a fourth set of vertical vias.

Abstract: A multilayer inductor has a rectangular parallelepiped element body and its length in the lengthwise direction (L), length in the direction of height (H), and length in the direction of width (W) are L?0.6 mm, H?0.3 mm, and W?0.3 mm, respectively. Terminal electrodes are provided so as to cover the vertices of the element body and come round to the side face from the end faces on both sides. The radius of curvature R of the vertex of the terminal electrode is set to a value being 10% or more and 20% or less of H or W.

Abstract: A capacitor element on a chip, e.g., a MMIC chip, includes a main capacitor in parallel with a series configuration of trimming capacitors. The total capacitance value of the parallel arrangement can be increased from its inherently minimum value by applying one or more laser pulses to one or more of the trimming capacitors, such that in each case a short-circuit is produced between the metallization layer to which the pulses are applied and the other metallization layer making up the trimming capacitor.

Abstract: A combination run capacitor/positive temperature coefficient resistor/overload (CAP/PTCR/OL) module is described. The cover of the combination housing includes a capacitor compartment and terminal openings for receiving blade terminals of a run capacitor. The terminal openings in the cover align with blade receiving receptacles coupled to the PTCR start circuit. The blade terminals of a run capacitor are inserted into the receptacle openings and into electrical engagement with the blade receiving receptacles. The capacitor is supported and protected by a potting mixture filling the capacitor compartment.

Abstract: A semiconductor device, in which four pieces of strip-shaped electrodes, whose longitudinal directions are the same, are formed in each layer of a plurality of wiring layers that are provided by a same design rule with each other, simultaneously with regular wirings. In each wiring layer, two pieces each of first electrode and second electrode are formed parallelly with each other, alternately, and remote from each other. Then, the first electrodes formed in each layer are connected to each other by a first via, the second electrodes formed in each layer are connected to each other by a second via, a first structure body formed by connecting the first electrodes and the first via to each other is connected to a ground wiring, and a second structure body formed by connecting the second electrodes and the second via to each other is connected to a power source wiring.

Abstract: A method of forming a ceramic structure includes disposing substrate-forming ceramic green sheets having conductors, internal conductors, and via conductors so as to sandwich connecting member-forming ceramic green sheets having via conductors, followed by lamination and bonding thereof by pressure application, with the conductors being formed using a conductive paste primarily composed of a powdered metal, so that a ceramic laminate composed of ceramic molded bodies laminated to each other is formed. The ceramic laminate is fired at a temperature at which the substrate-forming ceramic green sheets are sintered and the connecting member-forming ceramic green sheets are not sintered and at a temperature not more than the melting point of the metal, and subsequently, the connecting member-forming ceramic green sheets are removed from the fired composite laminate, thereby forming a ceramic structure.

Abstract: A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.

Abstract: An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode and an insulating layer interposed therebetween. The first electrode includes a bulk layer comprising n-doped polysilicon. The first electrode also includes an interface layer extending from a first surface of the bulk layer to the insulating layer. The interface layer is heavily doped with phosphorus so that the depletion region of the first electrode is confined substantially within the interface layer. The method of forming the interface layer comprises depositing a layer of hexamethldisilazane (HMDS) material over the first surface of the bulk layer so that HMDS molecules of the HMDS material chemically bond to the first surface of the bulk layer. The method further comprises annealing the layer of HMDS material in a phosphine ambient so as to replace CH3 methyl groups with PH3 molecules.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are alternately laminated, and a plurality of outer conductors (first and second terminal conductors, and first and second outer connecting conductors) formed on the multilayer body. Each of the outer conductors is formed on one of two side faces of the multilayer body opposing each other. Each of the first and second inner electrodes is electrically connected to the corresponding outer connecting conductor. At least one first inner connecting conductor and at least one second inner connecting conductor are laminated in the multilayer body. Each of the inner connecting conductors is electrically connected to the corresponding terminal and outer connecting conductors. The equivalent series resistance of the multilayer capacitor is set to a desirable value by adjusting the number or position of inner connecting conductors.

Abstract: A power supply apparatus and a power supply method are described, wherein the non-polar characteristics of the electrodes of a capacitor is utilized to improve the energy utilization efficiency of a battery through reciprocating switches of polarity connection between the battery and the capacitor. The voltages of the capacitors can also stay at a near constant level using the polarity reversal mechanism.

Abstract: A high capacity silicon capacitor formed on an integrated circuit substrate includes a metal portion on the substrate; a silicon nitride (SiN) portion sputtered on the metal; a silicon (Si) portion sputtered on the silicon nitride portion, another SiN layer and finally a metal layer. The SiN layers are for increased isolation and are optional.

Abstract: In a capacitor device of the present invention includes a substrate, a plurality of lower electrodes formed on the substrate, a plurality of dielectric films formed on a plurality of lower electrodes respectively in a state that the dielectric films are separated mutually, and upper electrodes formed on a plurality of dielectric films respectively, a plurality of capacitors each composed of the lower electrode, the dielectric film, and the upper electrode are arranged on the substrate respectively, and each of the dielectric films in a plurality of capacitors has a different film thickness.

Abstract: In a chip-type electronic component of the present invention, at least one surface of a ceramic body is a convexly curved surface. Specifically, at least one surface in a thickness direction of the ceramic body may be convexly curved, and the side surface of the ceramic body may be concavely curved. Alternatively, only one surface may be a convexly curved surface. This chip-type electronic component has a high visibility and a high mechanical strength, though it is small. Moreover, in a chip-type electronic component comprising a ceramic body that is formed by alternately laminating insulating layers and conductor layers, and a pair of external electrodes, the thickness in a laminate direction at the central part between external electrodes of the ceramic body is made greater than the thickness of the end surface. This prevents breakage of the external electrodes and also enlarges the ceramic body.

Abstract: It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelectricity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

Abstract: A first inner conductor (21), a second inner conductor (23), a first inner conductor (22), and a second inner conductor (24) are disposed in the order mentioned from the top in the dielectric element (12). The first inner conductors (21, 22) are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors (23, 24) is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors (21, 22) are respectively led out. Terminal electrodes (31–34) are respectively disposed on four side surfaces of the dielectric element (12) for connection with these four inner conductors (21–24) respectively.

Abstract: A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.

Abstract: A capacitor device of the present invention includes a substrate, a float electrode formed on the substrate, a valve metal film formed on the float electrode, a dielectric film formed on the valve metal film by applying an anodic oxidation to a part of the valve metal film, and a pair of electrodes provided in areas overlapping with two different parts of the float electrode on the dielectric film respectively.

Abstract: An electrical component with a printed circuit board. The printed circuit board has an upper face and a lower face. A microprocessor is mounted to the upper face. A capacitor is mounted to the lower face. The capacitor has a first face parallel to the printed circuit board and a second face opposite to the first face. First plates and second plates are in alternating planar relationship with a dielectric therebetween and arranged in a plane perpendicular to the plane created by the circuit board. Each first plate has a first coupling tab and a power tab on opposing edges wherein the first coupling tab terminates at the first face and the power tab terminates at the second face. Each second plate of the second plates comprises a second coupling tab and a ground tab on opposing edges wherein the second coupling tab terminates at the first face and the ground tab terminates at the second face. The first coupling tab and the second coupling tab are in electrical contact with the microprocessor.

Abstract: A semiconductor component includes an insulating layer, which is configured on a semiconductor substrate and in which a capacitor structure is formed. The capacitor structure has at least two parallel metallization planes, whereby at least one of the planes is configured in a lattice and inhomogeneous structure, which are electrically connected to the first metallization plane, extended at least partially into the cavities of the latticework metallization plane.

Abstract: A stacked capacitor includes a dielectric member, a plurality of internal electrodes, and a plurality of extraction electrodes. The dielectric member is a stacked member formed of stacked dielectric layers and having at least one side surface. The internal electrodes are stacked alternately with the dielectric layers and have first edges positioned near the side surface. Each of the extraction electrodes leads from each first edge to the side surface. Each of the extraction electrodes has a width W on the side surface in a direction orthogonal to the stacking direction and is separated from adjacent extraction electrodes by a distance G on the side surface in the direction orthogonal to the stacking direction. The width W and distance G are set such that 1.2?W/G?4.0.

Abstract: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

Abstract: A circuit board includes two planes. A via spans the planes, and an impedance component is placed in the via. The impedance component is coupled to both of the planes. The impedance component provides an impedance between the planes without the use of traces or hand soldering of components.

Abstract: A capacitor with conductive layers arranged in parallel relationship. The conductive layers have nickel alloyed with a refractory metal in an amount sufficient to raise the melting temperature of said conductive layer at least 1° C. above the melting temperature of nickel. A dielectric layers is between the conductive layers. Alternating layers of said conductive layers are in electrical contact with external terminations of opposing polarity.

Abstract: A multilayered structure array has narrow pitches by making thinner coatings for insulating internal electrode layers from side electrodes and the productivity of the multilayered structure array is improved. The multilayered structure includes: a first internal electrode layer; a piezoelectric layer formed on the first internal electrode layer; a second internal electrode layer formed on the piezoelectric layer; a first coating formed on an end surface of the first internal electrode layer in a first side surface region of the multilayered structure and containing one of metal oxide, metal nitride, metal fluoride and metal sulfide in at least one part thereof; and a second coating formed on an end surface of the second internal electrode layer in a second side surface region of the multilayered structure and containing one of metal oxide, metal nitride, metal fluoride and metal sulfide in at least one part thereof.

Abstract: A multilayer capacitor includes: a dielectric element; a pair of first internal conductors with same polarity disposed in the dielectric element to be adjacent to each other while being separated from each other by the dielectric layer; first leadout portions led out from the pair of first internal conductors respectively, one being provided for each of the first internal conductors; a pair of second internal conductors with same polarity disposed in the dielectric element to be adjacent to each other while being separated from each other by the dielectric layer; and second leadout portions led out from the pair of second internal conductors respectively, one being provided for each of the second internal conductors, wherein the first leadout portion and the second leadout portion led out respectively from the first internal conductor and the second internal conductor disposed adjacent to each other are led out to substantially the same positions in side faces facing each other of the dielectric element, resp

Abstract: Internal electrodes A1 to D1 and A2 to D2 are laid in layers at spaces in the direction of thickness of a ceramic body 1. Lead electrodes a1 to d1 and a2 to d2 are led out to a side face to form lead portions. Dummy electrodes 51 to 58 have one-side ends led out to a side face to form lead portions in layers provided with the internal electrodes A1 to D1 and A2 to D2. The lead portion of a lead electrode a1 to d1 or a2 to d2 of each layer is superposed over the lead portion of a dummy electrode 51 to 58 belonging to another layer in the direction of thickness.

Abstract: A laminated ceramic capacitor includes a ceramic block formed by laminating a plurality of ceramic sheets, a plurality of external electrodes formed on outer surfaces of the ceramic block facing each other, and set as a positive terminal and a negative terminal, respectively, one or more first and second internal electrodes alternately arranged within the ceramic block such that electric currents flow in opposite directions in the internal electrodes, and a plurality of withdrawing patterns for connecting the first and second internal electrodes to the external electrodes, respectively.

Abstract: The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.

Abstract: An electro-magnetic interference filter terminal assembly for active implantable medical devices includes a structural pad in the form of a substrate or attached wire bond pad, for convenient attachment of wires from the circuitry inside the implantable medical device to the capacitor structure via thermal or ultrasonic bonding, soldering or the like while shielding the capacitor from forces applied to the assembly during attachment of the wires.

Abstract: The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise.

Abstract: A structure and method for manufacturing multi-electrode capacitor within a PCB is used to form a multi-electrode capacitor with a plurality of metal laminates coupled each other and employing the characteristics of the edge-coupled effect therein. the present invention can provide efficient capacitance from the capacitor with the smallest area. The present invention is applied to promote the capability of noise-restraint of the capacitive substrate in a high-frequency/speed system, and further achieves the purpose of regular circuit design with the smallest area in the future development.

Abstract: In this laminated ceramic capacitor, a heat radiation conductor is provided on a top face of a rectangular parallelepiped laminated chip where a plurality of first conductor layers and a plurality of second conductor layers are arranged alternatively through each ceramic layer with facing each other. In addition, the heat radiation conductor is connected to the upper edge of each second conductor layer. Therefore, when heat is generated in each first conductor layer and each second conductor layer which play the role of internal electrodes, the heat of each second conductor layer is directly transferred from each second conductor layer to the heat radiation conductor, and is radiated outside from the heat radiation conductor.