Abstract: A multilayer capacitor has a capacitor element, inner electrodes arranged within the capacitor element, and first terminal electrodes and second terminal electrodes arranged on the capacitor element. The capacitor element has an element part held between the inner electrodes. The first terminal electrodes and second terminal electrodes have electrode parts. When seen in a second direction, the electrode parts are arranged on first and second side faces in any of a plurality of areas holding the element part therebetween in a third direction and not overlapping the element part.

Abstract: A multilayer capacitor has a laminate body in which a first internal electrode and a second internal electrode are alternately laminated with a dielectric layer in between, a first terminal electrode provided on one end side of the laminate body, and a second terminal electrode provided on the other end side of the laminate body. The first internal electrode has a first lead portion connected to the first terminal electrode. The second internal electrode has a second lead portion connected to the second terminal electrode. The first internal electrode consists of plural types of first internal electrodes and the plural types of first internal electrodes have their respective first lead portions at different positions. Distances between the first lead portions of the respective types of the first internal electrodes and the second lead portion are different from each other.

Abstract: A low-inductance multilayer parallel plate capacitor in the form of a rectangular parallelepiped includes at least one pair of consecutive composite layers stacked parallel to each other in the vertical direction, each having a dielectric substrate and a conductor plate. Each conductor plate includes one or more lead portions to enable connection to terminations, and plates on consecutive composite layers are connected to terminations of opposite polarity. Each conductor plate advantageously includes one or more non-conductive regions that provide directionality to the currents flowing through the plates, resulting in a capacitor structure with greatly reduced inductance.

Abstract: Methodologies are disclosed for producing multilayer electronic devices using a single screen printing mask. Plural layer devices are constructed by placing a common mask in alternating positions among alternating layers of support material such that, upon stacking of the plural layers, complimentary electrode structure is produced in alternating layers. Support material may be varied to produce different devices, including capacitors, resistors, and varistors. Multilayer electronic devices include multiple layers providing adjacent printed complimentary electrode layers having an upper surface, a lower surface, a front edge, and a back edge, and with lateral end portions of combined first and second layers trimmed so as to expose selected conductive patterns. Termination material is applied to at least such trimmed lateral end portions.

Abstract: A multilayer chip capacitor including: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer there between in the capacitor body and having one lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, and the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction.

Abstract: A high-frequency composite component for selectively switching a GSM-system signal path and a DCS-system signal path for a signal transmitted to or received from an antenna terminal by a diplexer. Transmission-side input terminals and reception-side balanced output terminals to be switched by high-frequency switches are included in the GSM and the DCS systems. Matching elements include inductors and capacitors that are inserted between the reception-side balanced output terminals and the output side of surface acoustic wave filters.

Abstract: A chip-type electronic component includes a ceramic chip body, an external electrode formed on the chip body, a conductive elastic resin film made of a mixture of metal powder and elastic resin and formed to cover the external electrode, and a metal plating film. The metal powder is exposed at an obverse surface of the conductive elastic resin film. The metal plating film is formed on the obverse surface of the conductive elastic resin film at which the metal powder is exposed.

Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.

Abstract: A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.

Abstract: A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electro

Abstract: The present invention is intended to provide a laminated electronic component having a configuration in which the number of extraction electrodes is reduced to realize a high ESR, the adhesion of a terminal electrode with respect to an ECA is increased and a short-circuit defect between an internal electrode and a dummy electrode can be prevented. An electrode layer in the ECA includes the internal electrode, the extraction electrode and the dummy electrode. One end of the extraction electrode is connected with the internal electrode in the same layer, and the other end of the same is led onto a side surface of the ECA 1 to be connected with the terminal electrode. This is also applied to other extraction electrodes.

Abstract: A multilayer capacitor 10 of the present invention including: a dielectric body 12 formed by stacking a plurality of dielectric layers 12a; an internal layer portion 17 in which a first and second internal conductor layers 21 and 22 are stacked alternately in the dielectric body 12 via the dielectric layer 12a; external layer portions 19a and 19b in which a first and second external conductor layers 23 and 25 are stacked via the dielectric layer 12a; a first terminal electrode 31 connected with the first internal conductor layer 21 and the first external conductor layer 23, formed at least on a first side face 12A of the dielectric body 12; and a second terminal electrode 32 connected with the second internal conductor layer 22 and the second external conductor layer 25, formed at least on a second side face 12 B opposed to the first side face 12A.

Abstract: In the capacitor, an insulating structural member 28 is arranged on an earth metal fitting 27. In the earth metal fitting 27, two sets of cylindrical-shaped portions 26 are separately arranged in an interval, and a floating portion 27a is formed. The insulating structural member 28 is arranged opposite to the floating portion 27a of this earth metal fitting 27 in such a manner that both a concave portion 28a and a convex portion 28b are formed on the insulating structural member 28 to be fitted to the cylindrical-shaped portion 26. Since a feedthrough conductor 29 penetrates a through hole 30 of the insulating structural member 28, the earth metal fitting 27, the insulating structural member 28, and the feedthrough conductor 29 are positioned with each other. Then, one opening portion 31a of an insulating case 31 is fitted into the floating portion 27a of the earth metal fitting 27.

Abstract: A decoupling module for decoupling high-frequency signals from a voltage supply line, the module including a plurality of parallel-connected capacitors (K1, K2, . . . ), which each have a capacitance (C1, C2, . . . ), and are characterized in that at least one of the capacitors (K1) has an inductance (L1) which is selected dependent on the capacitance (C1) of the capacitor (K1) and the voltage supply line inductance (L12), so that a resonance is generated which compensates the self-resonance of the system from at least a further capacitor (K2, . . . ) and the entire voltage supply line (S). L12 is the inductance of the voltage supply line running between the parallel-connected capacitors.

Abstract: A multilayer capacitor comprises a capacitor body; first and second inner electrodes alternately arranged in the capacitor body; and a first outer connecting conductor and first and second terminal electrodes arranged on an outer surface of the capacitor body. Each first inner electrode has a first main electrode portion and a first lead electrode portion for connecting the first main electrode portion to the first outer connecting conductor. Each second inner electrode has a second main electrode portion and a second lead electrode portion for connecting the second main electrode portion to at least one second terminal electrode. The capacitor body includes a first inner connecting conductor arranged outside of at least one set of first and second inner electrodes in the opposing direction of the first and second inner electrodes and connected to at least one first terminal electrode and the first outer connecting conductor.

Abstract: A multilayer capacitor has a multilayer body in which multiple dielectric layers and multiple inner electrodes are alternately laminated, and multiple terminal electrodes formed on the multilayer body. The multiple inner electrodes include multiple first inner electrodes and multiple second inner electrodes alternately arranged. The multiple terminal electrodes include first and second terminal electrodes electrically insulated from each other. The multiple first inner electrodes are electrically connected to each other by way of a through-hole conductor. The multiple second inner electrodes are electrically connected to each other by way of a through-hole conductor.

Abstract: At least four terminal electrodes are provided on a surface of multi-layer substrate main body. An electric functional layer is selectively provided at an internal area of said multi-layer substrate placed at a downward position of all terminal electrodes in a substrate thickness direction. A semiconductor device is flip-chip-bonded to the terminal electrodes. Thus, the semiconductor device is electrically connected to the electric functional layer at a short distance. As a result, a reduction in parasitic inductance and an improvement in high frequency characteristic can be accomplished. Generation of height variations between the terminal electrodes can be prevented, and the semiconductor device is stably flip-chip-bonded to the multi-layer substrate.

Abstract: A laminate is prepared in which adjacent internal electrodes are electrically insulated from each other at an end surface at which the internal electrodes are exposed, a space between the adjacent internal electrodes, which is measured in the thickness direction of insulating layers, is about 10 ?m or less, and a withdrawn distance of the adjacent internal electrodes from the end surface is about 1 ?m or less. In an electroplating step, electroplating deposits deposited on the ends of the adjacent internal electrodes are grown so as to be connected to each other.

Abstract: A laminated body is prepared, in which at an end surface at which internal electrodes are exposed, the internal electrodes disposed adjacently are electrically isolated from each other, and a distance between the internal electrodes disposed adjacently is about 20 ?m or less when measured along the thickness direction of an insulator layer, and a withdrawn-depth of the internal electrodes is about 1 ?m or less when measured from the end surface. In a step of electroless plating, plating deposits formed at the end portions of the plurality of internal electrodes are increased in size so as to be connected to each other.

Abstract: The monolithic ceramic electronic component includes a first external electrode 5, a second external electrode 6, and a ceramic sintered compact 4 including internal electrodes 2 and 3, the first and second external electrodes 5 and 6 being disposed on both end faces 4a and 4b of the ceramic sintered compact 4. The first and second external electrodes 5 and 6 have a multilayer structure in which sintered electrode layers 5a and 6a, intermediate electroplated layers 5b and 6b, and plated layers 5c and 6c are arranged in that order. Exposed surface regions 7a of insulating oxides 7 are exposed from the outer faces of the sintered electrode layers 5a and 6a, the oxides 7 being derived from a glass frit contained in the sintered electrode layers. Metals 8 are deposited on the exposed surface regions 7a and the intermediate electroplated layers 5b and 6b are then formed by electroplating.

Abstract: A variable IC capacitor includes a semiconductor layer doped to contain mobile charge carriers. Capacitor electrodes C1 and C2 are disposed adjacent to each other on the layer's surface, gate electrodes G1 and G2 are disposed on opposite sides of C1 and C2, and source and sink electrodes are disposed on opposite sides of G1 and G2. Potentials are applied to the electrodes as needed to inject and then confine a finite charge into the region under C1 and C2. A drive voltage V applied between C1 and C2 causes the charge packet to move back and forth beneath them, such that the effective capacitance C seen by drive voltage V is given by C=Q/V, where Q is the magnitude of the charge packet.

Abstract: A ceramic capacitor comprises a ceramic sintered body, and first and second terminal electrodes formed on outer surfaces of the ceramic sintered body. The first terminal electrode is electrically connected to a land formed on a substrate through a first metal terminal. The first metal terminal has a first capacitor connecting portion mechanically connected to the first terminal electrode, a first terminal portion mechanically connected to the land, and a first intermediate portion electrically connecting the first capacitor connecting portion and the first terminal portion to each other. The first capacitor connecting portion of the first metal terminal is parallel to the substrate.

Abstract: A chip-type electronic component includes a ceramic chip body incorporating an element, an external electrode formed on a side surface of the chip body, a conductive elastic resin film which is larger in width than the external electrode and formed to cover the external electrode and extend onto part of a mount surface of the chip body, and a metal plating film for soldering formed on the conductive elastic resin film.

Abstract: A multilayer electronic component including a multilayer ceramic capacitor is disclosed, which includes a laminate of dielectric layers and internal electrodes disposed on the dielectric layers; at least one via-conductor penetrating the dielectric layers and connecting to the internal electrodes; and at least one external terminal formed on an outer surface of the laminate and connecting to an end of the via-conductor, wherein the external terminal includes a lower bump formed on the outer surface of the laminate and an upper bump formed on the lower bump, and a diameter of the upper bump is smaller than that of the lower bump.

Abstract: An electrical function unit includes a carrier having dielectric layers, electrically conductive layers, and a first contact on a surface of the carrier, where the dielectric layers and electrically conductive layers are stacked such that electrically conductive layers are between dielectric layers. The dielectric layers and electrically conductive layers form a multilayer capacitor in the carrier. The multilayer capacitor includes a first stack of first electrically conductive layers that are electrically interconnected and a second stack of second electrically conductive layers that are electrically interconnected. The first stack is capacitively coupled to the first contact, and the first contact has substantially no galvanic connection to the first stack or to the second stack.

Abstract: A green sheet coating material including ceramic powder, a binder resin including a butyral based resin as the main component, and a solvent. The solvent includes a first solvent medium having a relatively low boiling point, wherein said binder resin is easy to be dissolved, and a second solvent medium having a relatively high boiling point. The boiling point of the second solvent medium is in a range of 130 to 230° C. The second solvent medium is included by 5 to 70 wt %, and more preferably 8 to 52 wt % with respect to 100 wt % of the entire solvent.

Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Abstract: A capacitor has stacking capacitor elements, each of which contains a conductor plate, a first band being an insulator and disposed around the plate, a second band being an insulator and disposed around the plate so as to be substantially parallel to the first band, an insulating coating covering a region sandwiched between the first and second bands, a cathode layer formed on the insulating coating, and an anode containing the plate and formed on an outer side of at least one of the first and second bands. The cathode layers are elctrically connected to each other through paths each connecting in series the facing two cathode layers of the adjacent two elements and path(s) connecting in parallel the cathode layers to each other, and the anodes are electrically connected to each other through path(s) connecting in parallel the anodes to each other.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Abstract: A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.

Abstract: A multilayer capacitor comprising a dielectric body 12 having an approximately rectangular parallelepiped shape formed by stacking a plurality of dielectric layers 12a; a first internal conductor layer 21 led out straddling a first longitudinal direction side face 12A and two lateral direction side faces 12C and 12D of said dielectric body 12; a second internal conductor layer 22, stacked in the dielectric body 12 via dielectric layers 12a to the first internal conductor layer 21, led out straddling a second longitudinal direction side face 12B and two lateral direction side faces 12C and 12D; a first terminal electrode 31 formed on an outer face of said dielectric body 12, straddling the first longitudinal direction side face 12A and two lateral side faces 12C and 12D; and a second terminal electrode 32 formed on the outer face of said dielectric body 12, straddling the second longitudinal direction side face 12B and two lateral side faces 12C and 12D.

Abstract: A first ceramic substrate includes a substrate (2) and a glaze layer (3), wherein the glaze layer has a surface having an Ra of 0.02 ?m or less and a Ry of 0.25 ?m or less. A second ceramic substrate is formed by subjecting a glass layer (24) formed on a surface of a substrate (2) to heating-and-pressurizing treatment, thereby forming a glaze layer (3) on the substrate (2), and planarization-polishing the surface of the glaze layer. A third ceramic substrate includes a substrate (2), a glaze layer (3) containing substantially no pores formed on the substrate (2) and the surface thereof being planarization-polished, and a wiring pattern (21), wherein at least one first end of the wiring pattern is exposed to the glaze layer (3) surface of the substrate (1), and at least one second end is exposed to another surface of the substrate (1).

Abstract: The present invention provides the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.

Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphery of the electronic component in one or more aligned columns. Each exposed portion is within a predetermined distance from other exposed portions in a given column such that bridged terminations may be formed by depositing one or more plated termination materials over selected of the respectively aligned columns. Internal anchor tabs may be provided and exposed in prearranged relationships with other exposed conductive portions to help nucleate metallized plating material along the periphery of a device. External anchor tabs or lands may be provided to form terminations that extend to top and/or bottom surfaces of the device.

Abstract: A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.

Abstract: An on-chip capacitor having a plurality of capacitor layers. Each capacitor layer includes a pair of frames. A first frame of the pair is electrically connected to first frames on each other capacitor layer and a second frame of the pair is electrically connected to second frames on each other capacitor layer. A plurality of tines project from each frame within the respective capacitor layer. The tines from each frame mesh so as to form an array of sequentially alternating tines from each frame to provide a layer capacitance within the capacitor layer. The multi-layer capacitor further includes a plurality of projections from the tines. The projections extend between frames of adjacent capacitor layers so as to provide an interstitial capacitance between the capacitor layers. The total capacitance of the on-chip capacitor is the sum of each layer capacitance and each interstitial capacitance.

Abstract: A reduction resistant lead-free and cadmium-free glass composition that is particularly suitable for use in conductive ink applications is disclosed. The invention includes a capacitor, which includes a conductive copper termination. The copper termination is made by firing an ink including a glass component, which may include ZnO, provided the amount does not exceed about 65 mole %; B2O3, provided the amount does not exceed about 61 mole %; and, SiO2, provided the amount does not exceed about 63 mole %. The molar ratio of B2O3 to SiO2 is from about 0.05 to about 3.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: An electronic component having an element body, and a terminal electrode disposed on the element body. The terminal electrode has a first electrode layer, a second electrode layer, and a third electrode layer. The first electrode layer is formed on an external surface of the element body and formed by baking of a conductive paste. The second electrode layer is formed by Ni plating on the first electrode layer. The third electrode layer is formed by Sn plating or Sn alloy plating on the second electrode layer. A thickness of the second electrode layer is set in a range of not less than 5 ?m, and less than 8 ?m.

Abstract: A stacked electronic component includes multiple energy storage units and a fastening device. Each energy storage unit has a first electrode and a second electrode. The fastening device includes first and second fastening member disposed on opposite sides of the energy storage units. Each of the first and second fastening members includes a body plate, at least a clamping structure extending from two edges of the body plate and at least a connecting part electrically connected to the body plate and the circuit board. The energy storage units are clamped by the clamping structures of the first and second fastening members and the first and second electrodes are electrically connected to the body plates of the first and second fastening members, so that the first and second electrodes are electrically connected to the circuit board through the body plates and the connecting parts of the first and second fastening members.

Abstract: A multilayer capacitor 1 has a laminated body 20 configured by laminating a plurality of dielectric substrates 2 each having a plurality of internal electrodes 3 and 5 formed on its main surface and a capacitance component is generated between the facing internal electrodes 3 and 5. The dielectric constant of the dielectric substrate located at a central portion of a lamination direction of the laminated body 20 is lower than that of the dielectric substrate 2 located at the edge of the lamination direction.

Abstract: A capacitor having improved surface breakdown voltage performance and a method for applying laser marking to capacitors which does not reduce capacitor surface breakdown voltage, can be applied using existing laser marking technologies and apparatus, and which results in a mark that is legible and clear, is disclosed. In a first exemplary embodiment a capacitor includes a laser mark which is located near one of the capacitor terminals. The exact location is not critical as long as the mark does not make physical contact with the terminal. Conventional laser marking technologies and apparatus may be used to fix the mark in the new location. In a second embodiment the laser mark is oriented so that a flat portion of the mark is is oriented closest to the adjacent terminal.

Abstract: An assembly includes a semiconductor device having surface-connecting terminals, a substrate having surface-connecting pads, and a capacitor having an approximately plate-shaped capacitor main body having a first surface on which the semiconductor device is mounted and a second surface at which the capacitor main body is mounted on the substrate and a plurality of electrically conductive vias penetrating the capacitor main body between the first and second surfaces and connected to the surface-connecting terminals and the surface-connecting pads.

Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set includes a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.

Abstract: A laminated ceramic capacitor includes a body having an inner layer portion and an outer layer portion and a plurality of terminal electrodes spaced apart from each other in a length direction of the body. The inner layer portion has a plurality of internal electrodes stacked in a height direction of the body. The internal electrodes have led-out portions led out to a side face of the body. The outer layer portion is disposed on one of opposite faces of the inner layer portion in the height direction. The terminal electrodes are each provided with a connecting portion and a spreading portion. The connecting portion extends along the height direction to cover corresponding one of the led-out portions. The spreading portion has a width gradually increasing from one of opposite ends of the connecting portion in the height direction toward an edge of the side face.

Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: A multilayer electronic component is composed of a ceramic body obtained by laminating a plurality of ceramic layers via a conductor layer. The conductor layer is a plated film and extracted to one end face of the ceramic body, thereby contributing to the formation of capacity. A peripheral edge portion of the conductor layer composed of the plated film is thicker than its inner region. This avoids stripping on the peripheral edge portion of the conductor layer and avoids internal defects such as delamination. A dummy conductor layer may be formed at a distance on the end opposite the end face for extraction.

Abstract: A multilayer ceramic capacitor (10) having reduced inductance which is separated into a first layer body (11) and a second layer body (12). The first layer body (11) and the second layer body (12) are formed by alternately layering inner electrodes (inner electrode 13a, inner electrode 13b) so as to face each other and sandwich ceramic layers (14). The ceramic layers (14) of the second layer body (12) are thicker than the ceramic layers (14) of the first layer body (11), so as to compensate for electrode height difference. Moreover, in the second layer body (12), the inner electrodes (13b) are electrically connected by via electrode (15b) so that the part of the via electrode (15b) extending without connection to an inner electrode (13b) is shortened.

Abstract: A multilayer capacitor array comprises a multilayer body, and first to fourth terminal conductors and first and second outer connecting conductors formed on the multilayer body. The multilayer body includes a first electrode group having a plurality of first and second inner electrodes, and a second electrode group having a plurality of third and fourth inner electrodes. The first to fourth inner electrodes are connected to the first to fourth terminal conductors, respectively. In the plurality of first inner electrodes, at least one first inner electrode whose number is smaller than the total number of the first inner electrodes by at least one is connected to the first terminal conductor. In the plurality of second inner electrodes, at least one second inner electrode whose number is smaller than the total number of the second inner electrodes by at least one is connected to the second terminal conductor.

Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.