Abstract: Disclosed are energy conditioner structures, method of making and using them wherein the structure comprises a sequence of conductive layers including a first A layer, a G layer, and a first B layer; wherein said first A layer, said G layer, and said first B layer are each conductive, and are conductively isolated from one another in said energy conditioner structure; wherein said first A layer includes a first A layer main body and a first A layer tab, said first B layer includes a first B layer main body and a first B layer tab, and said G layer includes a G layer main body and a G layer first tab; wherein said G layer is in a plane between a plane containing said first A layer and a plane containing said first B layer; where the main body of at least one of said first A layer and said first B layer opposes a portion of said G layer main body; wherein two of said first A layer tab, said first B layer tab, and said G layer first tab are on a first side of said energy conditioner, and the remaining one of sai

Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.

Abstract: A multilayer capacitor has a capacitor element body, first and second terminal electrodes, and a connection conductor. The capacitor element body has a plurality of insulator layers laminated, and a plurality of first internal electrodes and second internal electrodes arranged as opposed with at least one of the insulator layers in between. The first and second terminal electrodes are disposed on one external surface extending in a direction parallel to a laminating direction of the insulator layers, among external surfaces of the capacitor element body. The connection conductor is disposed on an exterior surface extending in the direction parallel to the laminating direction of the insulator layers, among the external surfaces of the capacitor element body. The first internal electrodes include two types of internal electrodes, a type of internal electrode connected to the first terminal electrode and the connection conductor and a type of internal electrode connected to the connection conductor only.

Abstract: A first signal internal electrode is connected to a first signal terminal electrode and a signal connection conductor. A second signal internal electrode is connected to a second signal terminal electrode and the signal connection conductor. A first ground internal electrode is connected to a first ground terminal electrode and a ground connection conductor. A second ground internal electrode is connected to a second ground terminal electrode and the ground connection conductor. The first signal internal electrode and the first ground internal electrode have their respective regions opposed to each other. The second signal internal electrode and the second ground internal electrode have their respective regions opposed to each other. The first signal internal electrode and the second ground internal electrode are not opposed to each other. The second signal internal electrode and the first ground internal electrode are not opposed to each other.

Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.

Abstract: A method and class of circuit configurations for coupling low-frequency signals from one stage of an electronic apparatus to another stage, from the outside world to such a stage, or from such a stage to the outside world, through the use of a plurality of symmetrical double-layer capacitors combined with other electronic components are disclosed. The capacitors are used for signal transmission while blocking direct current, rather than for energy storage. Use of double-layer capacitors in place of more conventional capacitors permits the transmission of a much wider range of signals with far less distortion. The technology is particularly well-adapted to use in medical devices, including bioelectronic stimulators, where redundant devices are required for safety in case of single component failure while unacceptable levels of distortion may occur when conventional components are used.

Abstract: A multi-segment parallel wire capacitor includes substantially identical multiple capacitor segments fabricated on a semiconductor substrate. Each segment comprises at least first and second interleaved metal finger formed in a first metal layer above the substrate and third and fourth interleaved metal fingers formed in a second metal layer. The first and fourth sets are connected together to form one plate of the capacitor and the second and third sets are connected to form a second plate. The multiple capacitor segments are arranged in a matrix having M rows and N columns. The multiple capacitor segments are inter-connected in such a manner that the capacitor segments in each column of the matrix are connected in parallel. First and second metal lines selectively connect the plates of the different capacitor segments in the first and last rows and serve as the two opposite terminals of the multi-segment parallel wire capacitor.

Abstract: A multilayer electronic component has: a first capacitive electrode layer of a rectangular shape on which four capacitive electrode portions are formed at four comers; and a ground electrode layer which is laid on the first capacitive electrode layer and on which a ground electrode is formed so as to be arranged as superposed over the four capacitive electrode portions. The four capacitive electrode portions are equidistant from a first facing edge pair of the first capacitive electrode layer and equidistant from a second facing edge pair different from the first edge pair. This configuration equalizes distributions of electric fields established between the respective capacitive electrode portions and the ground electrode, which realizes uniformization of the capacitances in the four respective capacitive electrode portions.

Abstract: Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

Abstract: Disclosed are apparatus and methodology for providing controlled equivalent series resistance (ESR) decoupling capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Controlled equivalent series resistance (ESR) is provided by providing extended length tab connections to active electrode layers within the device.

Abstract: In a monolithic ceramic capacitor, the size of end surfaces of a capacitor body in a two-dimensional surface in which ceramic layers extend is greater than the size of side surfaces in the two-dimensional surface in which the ceramic layers extend. External terminal electrodes include a resistive component. In each of first to fourth internal electrodes, a width-direction size of a lead-out portion is less than a width-direction size of a capacitance portion. The lead-out portions of the first and third internal electrodes and the lead-out portions of the second and fourth internal electrodes are arranged so as to partially overlap each other or not to overlap each other.

Abstract: In a multilayer capacitor including a capacitor body, first capacitor portions and a second capacitor portion are arranged in the direction of lamination. While a resonant frequency of the first capacitor portions is set to be greater than a resonant frequency of the second capacitor portion so that the first capacitor portions contribute to low impedance, an ESR per layer of the second capacitor portion is set to be greater than an ESR per layer of the first capacitor portions so that the second capacitor portion contributes to high ESR. Further, a combined ESR of the first capacitor portions is set to be substantially equal to a combined ESR of the second capacitor portion.

Abstract: Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of first and second polarity electrode layers. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups and thin-film plated deposition is formed thereon by electroless and/or electrolytic plating techniques. A solder dam layer is provided over a given component surface and formed to expose predetermined areas where solder barrier and flash materials may be deposited before attaching solder preforms. Some embodiments include plated terminations substantially covering selected component surfaces to facilitate with heat dissipation and signal isolation for the electronic components.

Abstract: A multilayer electronic component having a ceramic substrate and a resin layer mounted on a mounting substrate. Recess portions are formed at an outside-facing major surface side of the resin layer. In the resin layer, columnar conductors are disposed so that axis line directions thereof are aligned in a thickness direction of the resin layer. End portions of the columnar conductors are located inside the recess portions further from opening faces thereof and have end surfaces exposed in the recess portions. When a multilayer electronic component is mounted on a mounting substrate, solder is provided on the end surfaces of the columnar conductors in the recess portions. The thickness of solder used in the above mounting does not interfere with a reduction in size and height of an electronic device that includes the above multilayer electronic component.

Abstract: A first terminal electrode has a first electrode portion disposed on a first face and connected to a first internal electrode, and a second electrode portion disposed on a third face and connected to the first electrode portion. A second terminal electrode has a first electrode portion disposed on a second face and connected to a second internal electrode, and a second electrode portion disposed on the third face and connected to the first electrode portion. Each of the second electrode portions of the first and second terminal electrodes, when viewed along a second direction perpendicular to the third face, is arranged with a gap in a third direction perpendicular to the second directions so as to sandwich at least a portion of an end in the first direction of an element body region sandwiched between the first internal electrode and the second internal electrode, at an end in the first direction of the second electrode portion.

Abstract: A first terminal electrode has a first electrode portion disposed on a first face and connected to a first internal electrode, and a second electrode portion disposed on a third face and connected to the first electrode portion. A second terminal electrode has a first electrode portion disposed on a second face and connected to a second internal electrode, and a second electrode portion disposed on the third face and connected to the first electrode portion. Each of the second electrode portions of the first and second terminal electrodes, when viewed along a third direction perpendicular to the third face, is arranged with a gap in the second direction so as to sandwich at least a portion of an end in the first direction of an element body region sandwiched between the first internal electrode and the second internal electrode, at an end in the first direction of the second electrode portion.

Abstract: One inventive aspect relates to a laminated capacitor capable of satisfying higher electrostatic capacitance and lower ESL at the same time. A dielectric chip constituting the laminated capacitor has an integral structure formed by alternately laminating a pair of first inner conductor layer and second inner conductor layer which are positioned on the same plane and are held in a non-contact relation, and a pair of third inner conductor layer and fourth inner conductor layer which are positioned on the same plane and are held in a non-contact relation, while a dielectric layer is interposed between the pair of first and second inner conductor layers and the pair of third and fourth inner conductor layers. Voltage of one polarity is applied to the first and fourth inner conductor layers from a first outer electrode through lead-out portions, and voltage of the other polarity is applied to the second and third inner conductor layers from a second outer electrode through lead-out portions.

Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.

Abstract: A multilayer capacitor has a capacitor element, inner electrodes arranged within the capacitor element, and first terminal electrodes and second terminal electrodes arranged on the capacitor element. The capacitor element has an element part held between the inner electrodes. The first terminal electrodes and second terminal electrodes have electrode parts. When seen in a second direction, the electrode parts are arranged on first and second side faces in any of a plurality of areas holding the element part therebetween in a third direction and not overlapping the element part.

Abstract: A film capacitor suited to car-mount application, excellent in heat cycle tolerance and humidity resistance, and high in productivity, while maintaining low heat generation and low inductance characteristic is provided. The film capacitor comprises a film capacitor element, a bus bar as metal terminal connected to electrode of this film capacitor element, and a case for containing them, in which the film capacitor element and bus bar are packed within the case by plural layers of epoxy resin compositions, and the plural layers of epoxy resin compositions are composed so that the coefficient of linear expansion is smallest in the composition disposed in the uppermost layer.

Abstract: A feedthrough capacitor array has first and second terminal electrodes, first and second ground terminal electrodes, first and second signal internal electrodes, and first and second ground internal electrodes. The first signal internal electrode and the first ground internal electrode are arranged so as to be opposed to each other through a part of a dielectric element body. The second signal internal electrode and the second ground internal electrode are arranged to be opposed to each other through a part of the dielectric element body, in an opposed direction of the first signal internal electrode and the first ground internal electrode. The first signal internal electrode and the second ground internal electrode are arranged so as not to overlap each other in the opposed direction of the first signal internal electrode and the first ground internal electrode.

Abstract: A monolithic or essentially monolithic single layer capacitor with high structural strength and capacitance, a printed circuit board having the capacitor mounted thereon, and a method of making. Sheets of green-state ceramic dielectric material and glass/metal composite material are laminated together, diced into individual chips, and fired to sinter the glass and the ceramic together. The composite material contains an amount of metal sufficient to render the composite conductive whereby the composite may be used for one or both electrodes and for mounting the capacitor to the printed circuit board. Vertically-oriented surface mountable capacitors and hybrid capacitors are provided.

Abstract: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

Abstract: A laminated ceramic substrate includes a side electrode in which a side edge electrode layer formed on a side edge portion of a ceramic layer overlaps with and connects to a side edge electrode layer formed on a side edge portion of another ceramic layer directly above and/or directly below the former ceramic layer. The side edge electrode layer includes a parallel wall unexposed and approximately parallel to a side surface of the laminated ceramic substrate and a perpendicular wall approximately perpendicular to the side surface of the laminated ceramic substrate. A length La of the parallel wall and a depth Lb of the parallel wall from the side surface of the laminated ceramic substrate have a relationship of La>Lb.

Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).

Abstract: The heat resistance of a joint between a terminal electrode and a metal terminal as well as the bonding strength of the joint are increased in a ceramic electronic component. The surface of the metal terminal in contact with a binder is formed of a coating layer which is a Ag-based metal plated film. The binder contains a metal powder composed of a Cu-based metal and having an average particle diameter of 2.0 ?m or less and a glass component. The step of joining the metal terminal to a terminal electrode via the binder includes bringing the terminal electrode into intimate contact with the metal terminal via the binder and heat-treating them at a temperature in the range of 550° C. to 750° C. to form a Ag—Cu alloy layer between the metal terminal and a metal bonding layer, thus joining the terminal electrode to the metal terminal by Ag—Cu alloy bonding.

Abstract: A laminated ceramic capacitor has a high breakdown voltage and excellent withstand-voltage performance, and prevents cracks generated during firing even when the number of lamination layers constituted by ceramic layers and inner electrode layers is increased. The laminated ceramic capacitor includes capacitance forming layers in which ceramic dielectric layers and capacitance-forming inner electrode layers are laminated, and a stress relieving layer. The stress relieving layer is disposed between the capacitance forming layers. In the stress relieving layer, ceramic dielectric layers, dummy inner electrode layers (split electrodes) that do not contribute to the formation of electrostatic capacitance, and capacitance-formation-preventing inner electrode layers that prevent capacitance from being formed between the capacitance-forming inner electrode layers and the dummy inner electrode layers are laminated. The thickness of the stress relieving layer is in the range of about 100 ?m to about 300 ?m inclusive.

Abstract: A multilayer capacitor has a multilayer body in which dielectric layers and internal electrode layers are alternately laminated, and terminal electrodes formed on each of two mutually opposed side faces of the multilayer body. Each internal electrode layer includes a plurality of internal electrodes arranged in an array direction along a direction perpendicular to a laminating direction of the multilayer body and parallel to the side faces. A plurality of internal electrodes included in one internal electrode layer are electrically connected to the terminal electrodes respectively. A distance between a plurality of internal electrodes included in one internal electrode layer is not less than 20 ?m nor more than 200 ?m.

Abstract: A manufacturing method of conductive paste comprising arranging process (S20 to S23) of ceramics particles, arranging process (S10 to S14) of wetted metal particles, forming process (S30) of slurry wherein metal particles and ceramics particles are mixed and dispersion treatment process (S32) by applying collision to the slurry. The arranging process of wetted metal particles comprises, a process (S12) of adding solvent, compatible with organic component in conductive paste and incompatible with water, to undried water washed metal particles, a process (S18) of adding surfactant, a process (S14) of separating water from the metal particles and a process (S15) of adding acetone or the other second solvent.

Abstract: A capacitor body of a multilayer feedthrough capacitor is arranged with grounding inner electrodes and signal inner electrodes. The grounding inner electrodes include first and second grounding main electrode portions, grounding connection electrode portions having no areas opposing the signal inner electrodes, and first and second grounding lead electrode portions. The signal inner electrodes include first and second signal main electrode portions, signal connection electrode portions having no areas opposing the grounding inner electrodes, and first and second signal lead electrode portions.

Abstract: A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.

Abstract: A method for manufacturing a laminated ceramic capacitor includes a step of preparing a laminate which has a first principal surface, a second principal surface, a first end surface, a second end surface, a first side surface, and a second side surface and which includes insulating layers and internal electrodes having end portions exposed at the first or second end surface; a step of forming external electrodes on the first and second end surfaces such that plating deposits are formed on the exposed end portions of the internal electrodes so as to be connected to each other; and a step of forming thick end electrodes electrically connected to the external electrodes such that a conductive paste is applied onto edge portions of the first and second principal surfaces and first and second side surfaces of the laminate and then baked.

Abstract: A multilayer capacitor array comprises a capacitor body having rectangular first and second main faces opposing each other. In the capacitor body having a dielectric characteristic, a first electrode group including first and second inner electrodes and a second electrode group including third and fourth inner electrodes are arranged in a row. The first and third inner electrodes are arranged in contact with a reference plane parallel to the opposing direction of the first and second main faces between the first electrode group and second electrode group. The second and fourth inner electrodes are arranged such as to be separated from the reference plane by a predetermined distance.

Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.

Abstract: Electrode layers 121 to 128 are superimposed in a ceramic porcelain 1 with ceramic layers therebetween. The electrode layers 121 to 128 respectively include internal electrodes A1 to A8 and extraction electrodes B1 to B8. Giving a description on the electrode layer 121, one end of the extraction electrode B1 is connected with the internal electrode A1 in the same layer, and the other end of the same is led onto a side surface of the ceramic porcelain 1. Further, the extraction electrode B1 is formed to be thicker than the internal electrode A1 in the same layer.

Abstract: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.

Abstract: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in a signal absorption ring implemented around a non-absorptive area of one or more conductive layers of an integrated circuit structure to dampen laterally flowing Electro-Magnetic (EM) waves between electrically adjacent conductive layers of the device are also presented.

Abstract: A layered capacitor includes a capacitor body that is divided into two first capacitor sections and a second capacitor section. The first capacitor sections are disposed at ends in a layer-stacking direction such that the second capacitor section is interposed between the first capacitor sections in the layer-stacking direction. The resonant frequency of the first capacitor sections is greater than that of the second capacitor section. The total number of third internal electrodes and fourth internal electrodes provided per dielectric layer included in the second capacitor section is less than the total number of first via conductors and second via conductors per dielectric layer included in the first capacitor sections. The ESR per dielectric layer included in the second capacitor section is greater than that per dielectric layer included in the first capacitor sections.

Abstract: A multilayer electronic device includes a laminate and an external electrode that is formed on an end surface of the laminate after a plurality of conductive particles having a particle diameter of about 1 ?m or more is adhered to the end surface of the laminate, for example, by a sandblast method or a brush polishing method. The external electrode is defined by a plating film that is formed by electroplating or electroless plating.

Abstract: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted.

Abstract: A multilayer capacitor comprises a capacitor body, a first connecting conductor arranged on a first side face of the capacitor body, first and second terminal electrodes, and a first insulator arranged between the first connecting conductor and first terminal electrode. The capacitor body has a plurality of laminated insulator layers and a plurality of first and second inner electrodes. The second terminal electrode is connected to the second inner electrode. Each of the first inner electrodes has a first lead portion exposing an end to the first side face. At least one of the first inner electrodes also has a second lead portion whose end is exposed to the first side face. The first connecting conductor continuously covers all the ends of the first lead portions of the first inner electrodes and mechanically connects with the ends of the first lead portions.

Abstract: A multi-terminal multilayer capacitor reducing an equivalent series inductance (ESL), whose design flexibility is high, in which cost of electrode material is low, and in which a structural defect hardly occurs includes lead portions of first and second internal electrodes and lead portions of third and fourth internal electrodes that are disposed along the length of each of two side surfaces so as to be alternately exposed. Preferably, the first and third internal electrodes, and the second and fourth internal electrodes are disposed so as to be arranged along the length of each side surface in a coplanar manner, with a predetermined distance provided between two internal electrodes.

Abstract: An integrated multilayer chip capacitor module including: plurality of multilayer chip capacitors arranged close to one another and co-planar with one another; and a capacitor support accommodating the multilayer chip capacitors, wherein each of the multilayer chip capacitors includes a rectangular parallelepiped capacitor body and a plurality of first and second external electrodes formed on at least two sides of the capacitor body, and the external electrodes on adjacent sides of adjacent ones of the multilayer chip capacitor in the capacitor support are electrically connected to each other by a conductive adhesive material.

Abstract: A multilayer capacitor array comprises a multilayer body, and first to fourth terminal conductors and first and second outer connecting conductors formed on the multilayer body. The multilayer body includes a first electrode group having a plurality of first and second inner electrodes, and a second electrode group having a plurality of third and fourth inner electrodes. The first to fourth inner electrodes are connected to the first to fourth terminal conductors, respectively. In the plurality of first inner electrodes, at least one first inner electrode whose number is smaller than the total number of the first inner electrodes by at least one is connected to the first terminal conductor. In the plurality of second inner electrodes, at least one second inner electrode whose number is smaller than the total number of the second inner electrodes by at least one is connected to the second terminal conductor.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.

Abstract: A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.

Abstract: A package structure with an embedded capacitor, a fabricating process thereof and applications of the same are provided, wherein the package structure includes a dielectric layer, a first conductive layer, a second conductive layer, a first embedded plate and a second embedded plate. The dielectric layer has a thickness. The first conductive layer with a first potential is located on one side of the dielectric layer. The second conductive layer with a second potential is located on the dielectric layer at the other side thereof opposite to the first conductive layer. The first embedded plate and the second embedded plate that are embedded in the dielectric layer are separated at a distance, wherein the first embedded plate is electrically connected with the first conductive layer, and the second embedded plate is electrically connected with the second conductive layer.

Abstract: In one aspect of the invention, a thin layer capacitor element has a capacitor with a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, and a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.