Abstract: A laminated capacitor includes: a dielectric body; first terminal electrodes arranged at intervals on one surface of the dielectric body; second terminal electrodes arranged at intervals on the surface of the dielectric body; first internal electrodes arranged in layers within the dielectric body; second internal electrodes arranged in layers within the dielectric body to alternate with the first internal electrodes; first outer through-hole conductors each connecting each first terminal electrode to one first internal electrode which is located closest to the surface of the dielectric body among the first internal electrodes; second outer through-hole conductors each connecting each second terminal electrode to one second internal electrode which is located closest to the surface of the dielectric body among the second internal electrodes; a first inner through-hole conductor connecting the first internal electrodes to one another; and a second inner through-hole conductor connecting the second internal elec

Abstract: A laminated ceramic capacitor includes a body having an inner layer portion and an outer layer portion and a plurality of terminal electrodes spaced apart from each other in a length direction of the body. The inner layer portion has a plurality of internal electrodes stacked in a height direction of the body. The internal electrodes have led-out portions led out to a side face of the body. The outer layer portion is disposed on one of opposite faces of the inner layer portion in the height direction. Each terminal electrode extends along the height direction to cover corresponding one of the led-out portions and is provided with an intermediate portion and an end portion. The intermediate portion has a larger electrode width than the led-out portion. The end portion has a smaller electrode width at an edge of the side face than the intermediate portion.

Abstract: A monolithic capacitor includes a main capacitor unit having first capacitor portions and a second capacitor portion arranged in a direction of lamination, with the first capacitor portion located towards at least one end in the direction of lamination, so that the first capacitor portion is located closer to a mounting surface than the second capacitor portion. The number of pairs of third and fourth lead-out portions for third and fourth internal electrodes in the second capacitor portion is less than the number of pairs of first and second lead-out portions for first and second internal electrodes in the first capacitor portion, so that the first capacitor portion contributes to decreasing ESL while the second capacitor portion contributes to increasing ESR.

Abstract: A multilayer capacitor comprises a ceramic sintered body, an internal electrode disposed in the ceramic sintered body, and an external electrode disposed on an external surface of the ceramic sintered body. The external electrode has a first electrode layer formed on the external surface of the ceramic sintered body, a second electrode layer formed on the first electrode layer, and a conductive resin layer formed on the second electrode layer. The internal electrode and the first electrode layer consist primarily of a base metal. The second electrode layer consists primarily of a noble metal or a noble metal alloy. The conductive resin layer contains a noble metal or a noble metal alloy as a conductive material.

Abstract: A laminated ceramic capacitor including a capacitor body where internal electrodes and a dielectric layer are alternately laminated, and external electrodes are provided on the end faces thereof. In this capacitor body, high resistance layers are provided between the internal electrodes and dielectric layer. These high resistance layers contain a ceramic material, an element including at least one selected from Mn, Cr, Co, Fe, Cu, Ni, Mo and V, and/or a rare earth element.

Abstract: A multilayer capacitor includes a multilayer body in which dielectric layers and inner electrodes are alternately laminated, and terminal electrodes formed on the multilayer body. The inner electrodes include first inner electrodes and second inner electrodes alternately arranged. The terminal electrodes include at least three terminal electrodes. The first inner electrodes are electrically connected to each other via a through-hole conductor. The second inner electrodes are electrically connected to each other via a through-hole conductor. At least two first inner electrodes in the first inner electrodes are electrically connected via a lead conductor to at least two respective terminal electrodes whose number is smaller than the total number of the terminal electrodes by at least 1 in the at least three terminal electrodes.

Abstract: Internal electrode layers are superimposed in a dielectric substrate 1 at intervals. Step absorption layers are respectively provided on lateral sides of the internal electrode layers. A side portion of the internal electrode layer forms an inclined surface, and the step absorption layer is superimposed so as to partially overlap the inclined surface of the internal electrode layer. This is also applied to the other internal electrode layers and step absorption layers.

Abstract: A multilayer ceramic electronic component includes a skittered laminated body including internal electrodes that have a strength that is greater than that of ceramic layers provided therein. End portions of the internal electrodes protrude from end surfaces of the laminated body and are deformed so as to extend along the end surfaces by a barrel polishing process using balls. When external electrodes are formed on the end surfaces of the laminated body, a large contact area with the internal electrodes can be obtained. Therefore, a reliability of the electrical connection between the electrodes is definitely secured.

Abstract: A multi-layer chip capacitor includes a capacitor body; first and second internal electrodes alternately arranged therein and separated by dielectric layers, each of the internal electrodes having at least one opening formed at one or more sides thereof; first and second conductive vias passing through the openings and electrically connected to the first and second internal electrodes, respectively; first and second terminal electrodes of opposite polarities formed on one or more side faces of the capacitor body; and first and second lowermost electrode patterns being coplanar, each pattern including a via contact portion and a lead portion extending therefrom. The first and second lowermost electrode patterns are connected to the first and second terminal electrodes, respectively, through the respective lead portions of the lowermost patterns.

Abstract: A low inductance multi-layer capacitor. The capacitor includes interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate includes two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are alternately laminated, and a plurality of outer conductors (first and second terminal conductors, and first and second outer connecting conductors) formed on the multilayer body. Each of the outer conductors is formed on one of two side faces of the multilayer body opposing each other. Each of the first and second inner electrodes is electrically connected to the corresponding outer connecting conductor. At least one inner connecting conductor layer including a first and a second inner connecting conductors is laminated in the multilayer body. Each of the inner connecting conductors is electrically connected to the corresponding terminal and outer connecting conductors. The equivalent series resistance of the multilayer capacitor is set to a desirable value by adjusting the number or position of inner connecting conductor layer.

Abstract: A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.

Abstract: A metal alloy powder containing at least two alloying elements selected from the group of Ni, Cu, Cr, Sn, Mn, Co and W containing 1 to 99% by weight Ni, 1 to 99% by weight Cu, 6 to 60% by weight Cr, 6 to 15% by weight Sn, 6 to 15% by weight Mn, 6 to 15% by weight Co, and/or 6 to 15% by weight W for use in laminated ceramic capacitors with an internal electrode wherein said electrode comprises a sintered body of said alloy powder. A metal alloy powder containing at least two alloying elements selected from the group of Ni, Cu, Cr, Sn, Mn, Co and W wherein the onset of oxidation of the alloy powder occurs above about 250° C.

Abstract: An objective is to provide a multilayer filter capable of preventing an electric current rapidly flowing by virtue of varistor effect, from passing as noise, upon application of noise of a high voltage over a varistor voltage to its input. A multilayer filter has an inductor part 10 and a varistor part 20 in a laminate 2, and the inductor part 10 has the DC resistance of 4 ?-100 ?. This prevents an electric current rapidly flowing by virtue of the varistor effect, from passing as noise, upon application of noise of a high voltage over the varistor voltage to the input.

Abstract: A capacitor and a method for manufacturing the same provide a branched capacitor with a large capacitance and a super-slim structure. The method includes sintering a ceramic substrate; forming a plurality of troughs in the sintered ceramic substrate, the plurality of troughs including first and second sets of troughs corresponding to opposing electrodes; and filling the troughs with metal to form a plurality of metal lines arranged alternately in the plurality of troughs.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: A method for adjusting the equivalent series resistance (ESR) of a multi-layer component includes providing at least first and second layers separated by an insulating layer, providing a resistive layer between the inslulating layer and one of the first or second electrode layers, and adjusting the ESR of the component by varying the effective resistance of the resistive layer. The effective resistance may be varied by adjusting the composition or thickness of the resistive layer. Alternatively, the effective resistance may be varied by forming a plurality of through-holes perforating one of the electrode layers and by then adjusting the respective diameters of selected of the through-holes to vary the extent of coverage on the resistive layer. An additionally disclosed feature of the present subject matter is to incorporate dielectric layers of varied thicknesses to broaden the resonancy curve associated with a particular mutli-layer component configuration.

Abstract: The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: The capacitor 10 (laminated ceramic capacitor) of the invention comprises a capacitor body 11 wherein internal electrodes 12 (electrodes) and a dielectric layer 14 are alternately laminated, and external electrodes 15 are provided on the end faces thereof. The dielectric layer 14 has a site containing particles of a dielectric material which is formed of only one of these particles in its thickness direction. Regions 24 comprising at least one element selected from a group comprising Si, Li and B are scattered between the internal electrodes 12 and dielectric layer 14.

Abstract: A ceramic capacitor comprises a ceramic sintered body, and first and second terminal electrodes formed on outer surfaces of the ceramic sintered body. The first terminal electrode is electrically connected to a land formed on a substrate through a first metal terminal. The first metal terminal has a first capacitor connecting portion mechanically connected to the first terminal electrode, a first terminal portion mechanically connected to the land, and a first intermediate portion electrically connecting the first capacitor connecting portion and the first terminal portion to each other. The first capacitor connecting portion of the first metal terminal is parallel to the substrate.

Abstract: A multilayer capacitor includes a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated, and a plurality of terminal electrodes formed on side faces of the multilayer body. The multilayer body has a first capacitor portion and a second capacitor portion. The first capacitor portion includes first and second internal electrodes as the internal electrodes. The second capacitor portion includes third and fourth internal electrodes as the internal electrodes. Each of the first to fourth internal electrodes is electrically connected through a lead conductor or through lead conductors to one or more corresponding terminal electrodes among the first to fourth terminal electrodes. The first and second capacitor portions have their respective capacitances different from each other.

Abstract: A novel multi-capacitor divider network in which two capacitors are fabricated in a single package, using a common dielectric material, is disclosed. In a preferred embodiment of the present invention, the multi-capacitor network comprises a high-voltage capacitor and a low-voltage capacitor fabricated in a single monolithic package, both fabricated from a class one dielectric material having a combined tolerance of plus or minus five percent. The use of the same class one dielectric material for both capacitors assures that the temperature coefficents are similar for both capacitors and, more importantly, that the tolerance of the ratio between the high-voltage capacitor and low-voltage capacitor is within a predetermined range.

Abstract: A low inductance multi-layer capacitor. The capacitor comprises interleaved parallel internal electrode plates with dielectric there between. Each internal electrode plate comprises two lead-out tabs and is generally T shaped. A first external electrode terminal is electrically connected to the lead-out tabs of the even internal electrode plates, and a second external electrode terminal is electrically connected to the lead-out tabs of the odd internal electrode plates. The external electrode terminals are on a common first exterior surface and a common opposing second exterior surface of the capacitor.

Abstract: A multilayer capacitor has a multilayer body, and first and second terminal electrodes. In the multilayer body first and second internal electrode are laminated with a dielectric layer in between. The first internal electrode includes first and second electrode portions with a dielectric region between them along the laminating direction of the multilayer body, and a connection portion for electrically connecting the first and second electrode portions. The second internal electrode includes first and second electrode portions with a dielectric region between them along the laminating direction of the multilayer body, and a connection portion for electrically connecting the first and second electrode portions. The first internal electrode is electrically connected to the first terminal electrode, and the second internal electrode to the second terminal electrode.

Abstract: A method of forming a ceramic structure includes disposing substrate-forming ceramic green sheets having conductors, internal conductors, and via conductors so as to sandwich connecting member-forming ceramic green sheets having via conductors, followed by lamination and bonding thereof by pressure application, with the conductors being formed using a conductive paste primarily composed of a powdered metal, so that a ceramic laminate composed of ceramic molded bodies laminated to each other is formed. The ceramic laminate is fired at a temperature at which the substrate-forming ceramic green sheets are sintered and the connecting member-forming ceramic green sheets are not sintered and at a temperature not more than the melting point of the metal, and subsequently, the connecting member-forming ceramic green sheets are removed from the fired composite laminate, thereby forming a ceramic structure.

Abstract: A capacitor charging semiconductor apparatus including a plurality of serially connected capacitors to be charged. A direct current source is applied to the plurality of capacitors. A plurality of bypass transistors is provided to bypass charge current supplied to the plurality of capacitors when a voltage of a capacitor exceeds a prescribed reference level. A plurality of parallel monitor circuits is provided to control the plurality of bypass transistors to equally charge the plurality of capacitors. A plurality of capacitor connection terminals is connected to both ends and intersections of the plurality of capacitors. A plurality of transistor connection terminals is connected to the plurality of control terminals of the bypass transistor. A prescribed number of capacitors is optionally charged by increasingly shorting a number of capacitor connection terminals from the highest and lower voltage side capacitor connection terminals.

Abstract: A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.

Abstract: A multilayered chip capacitor (MLCC) includes internal electrodes and external electrodes formed to be perpendicular to the internal electrodes, whereby parasitic capacitance is reduced, resulting in no parallel resonance frequency effects. In addition, the MLCC has a capacitor structure, which provides a first surface and a second surface formed in a stacking direction of the dielectric layers in the capacitor body as a top surface and a bottom surface. Hence, in the thin capacitors having the same size, the number of internal electrode layers is increased, thereby reducing the equivalent series resistant (ESR) and equivalent series inductance (ESL). Further, the printed circuit board (PCB) having an embedded MLCC is easily manufactured.

Abstract: A multilayer capacitor having a low parasitic inductance includes a first electrode, a second electrode, a dielectric, a first contact, and a second contact. The first electrode is substantially rectangular and it includes a first contact finger. The dielectric has a first surface and a second surface, wherein the first and second surfaces are situated opposite with each other. The first surface of the dielectric is coupled with the first electrode. The second electrode is substantially rectangular and it includes a first contact finger. The second electrode is coupled to the second surface of the dielectric. The first contact is coupled to the first contact finger of the first electrode. The second contact is coupled to the first contact finger of the second electrode. The second contact is situated at a minimal space from the first contact to reduce the parasitic inductance.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Abstract: A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

Abstract: A capacitor with reduced equivalent series resistance and reduces equivalent series inductance is provided. Capacitors are provided with multiple plate assemblies that couple to a common single first polarity terminal. Capacitors are also provided with multiple plate assemblies that each couple to a respective second polarity terminal. Fan-like plate assemblies are arranged to provide increased capacitance with reduced equivalent series resistance and reduces equivalent series inductance. Capacitors are provided that mount using surface mounting technology. Capacitors are provided that conform to existing capacitor form factors.

Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.

Abstract: A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.

Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.

Abstract: A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

Abstract: This invention is directed to reduce degradation, loss, and reflection of high frequency signals of a coupling circuit for an alternating current. The coupling circuit, for connecting a first circuit element to a second circuit element, comprises a die capacitor and a chip capacitor connected in parallel to each other. The die capacitor has a first electrode that faces to and is in contact with the first circuit element, and a second electrode that is wire-bonded to the second circuit element. The chip capacitor also has a first electrode that is in contact with the first circuit element and a second electrode that is in contact with the second electrode of the die capacitor. The coupling circuit may show both advantages of superior performance at high frequencies attributed to the die-capacitor and relative large capacitance attributed to the chip-capacitor.

Abstract: A capacitor capable of being incorporated into a packaging substrate, which capacitor includes a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract: A method and apparatus for storing large quantities of electric energy in a small mass and volume at a high dc electric potential. Dispersed conductive particles 16 in a dispersing medium 15 contained in an insulator casing 21 between an insulating divider 11 and either a positive conductive plate 12 or a negative conductive plate 13 accumulate and store electric charges. A procedure of particle-to-particle charge pumping is employed to convey electric charges to and from the positive conductive plate 12 and the negative conductive plate 13 to the surfaces of each of a great multitude of dispersed conductive particles 16. Energizing results in oppositely charged dispersed conductive particles 16 becoming electrically bound to the surfaces of the insulating divider 11 with a large quantity of electric charges also residing on the outside surfaces of the repelling dispersed conductive particles 16, whereby the total effective capacitor plate surface area is greatly increased.

Abstract: A capacitor is provided having a structure in which an insulation film is interposed between a first electrode and a second electrode. The insulation film includes SrTiO3 as a main component, and at least one of Si and Ge added thereto.

Abstract: A dielectric body 12 has internal conductor layers 14 arranged in it. At the far sides of the internal conductor layers 14 separated by ceramic layers 12A, internal conductor layers 16 are arranged. A length W of a side of the dielectric body 12 running along a stacking direction Y of the ceramic layers is made longer than the lengths L and T of any other two sides running along directions (X- and Y-directions) intersecting the side running along the stacking direction (Y-direction). The internal conductor layers 14 and 16 are formed with cut parts 18a and 18b, the internal conductor layers 14 are divided into channel parts 20A and 20B across the cut part 18a, and the internal conductor layers 16 are divided into channel parts 22A and 22B across the cut part 18b. These channel parts are connected through uncut ends 19, whereby the current flows in reverse directions.

Abstract: A wiring board has a substrate, a bank disposed above the substrate and providing a plurality of regions, and a conductive layer and first and second interconnecting lines which are parallel to each other and formed between the bank and the substrate. The first interconnecting line is formed in a position closer to the substrate than the second interconnecting line. The vertical centerline of the first interconnecting line is not coincide with the vertical centerline of the second interconnecting lines. The conductive layer is formed in a position closer to the substrate than the second interconnecting line. The vertical centerline of the conductive layer is not coincide with the vertical centerline of the second interconnecting line. The conductive layer and first interconnecting line have portions which are not located under the second interconnecting line and extend in opposite width directions.

Abstract: A chip-type electronic component comprises a chip element body including an inner circuit element, and a pair of terminal electrodes electrically connected to the inner circuit element. The pair of terminal electrodes are positioned at respective end portions of the chip element body. The chip element body has one side face acting as a mounting surface opposing a circuit substrate. The pair of terminal electrodes include an electrode portion formed on the mounting surface. Here, it is assumed that a first direction is a direction orthogonal to the mounting surface, a second direction is a direction along which the pair of terminal electrodes oppose each other on the mounting surface, and a third direction is a direction orthogonal to the first and second directions.

Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphery of the electronic component in one or more aligned columns. Each exposed portion is within a predetermined distance from other exposed portions in a given column such that bridged terminations may be formed by depositing one or more plated termination materials over selected of the respectively aligned columns. Internal anchor tabs may be provided and exposed in prearranged relationships with other exposed conductive portions to help nucleate metallized plating material along the periphery of a device. External anchor tabs or lands may be provided to form terminations that extend to top and/or bottom surfaces of the device.

Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.

Abstract: A window via capacitor comprises a stacked multilayer configuration of at least one bottom layer, a plurality of first and second layers, a transition layer and a cover layer. An alternative window via capacitor comprises a stacked configuration of a bottom window layer, a bottom transition layer, a plurality of first and second layers, followed by a top window layer and a top cover layer. Each first and second layer is preferably characterized by a sheet of dielectric material with a respective first or second electrode plate provided thereon. Adjacent first and second electrode plates form opposing active capacitor plates in the multilayer configuration. Portions of each first and second electrode plate extend to and are exposed on selected side portions of the periphery of the window via capacitor.