Abstract: A semiconductor structure and a method for forming the same. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.

Abstract: A multilayer capacitor array achieves a high ESR because terminal conductors to which internal electrodes in capacitance sections are connected in parallel are connected in series through internal electrodes in ESR control sections to external electrodes. Since in the multilayer capacitor array the internal electrodes extend as far as a boundary between capacitor element portions, electrostriction occurs in an entire laminate including a region near the boundary between the capacitor element portions, with application of a voltage from the outside. Therefore, concentration of stress due to electrostriction is avoided, so as to suppress occurrence of cracking or the like.

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract: A method of forming a window via capacitor comprises a first step of providing a plurality of interleaved dielectric layers and paired electrode layers to create a multilayered arrangement characterized by top and bottom surfaces and a plurality pf side surfaces. First and second transition layer electrode portions are provided on a top surface of the multilayered arrangement on top of which a cover layer formed to define openings, or windows, therein is provided. The cover layer may be provided before device firing or may be printed on after firing using polymer or glass. Peripheral terminations are subsequently formed on the device periphery to connect selected electrode layers to respective transition layer electrode portions. Via terminations are formed in the cover layer openings, on top of which solder balls may be applied. Some of the terminations may be formed in accordance with various plating techniques as disclosed.

Abstract: In a ceramic electronic component, an electrically conductive resin layer is arranged to cover a thick film layer and to extend beyond the end of the thick film layer by at least about 100 ?m and a plating layer is arranged to cover the electrically conductive resin layer except a region having a dimension of at least about 50 ?m and extending along the end of the electrically conductive resin layer. Consequently, the concentration of the stress is reduced.

Abstract: A monolithic ceramic electronic component includes a ceramic laminate which includes a plurality of stacked ceramic layers and which has a first principal surface, a second principal surface opposed to the first principal surface, a first side surface, and a second side surface opposed to the first side surface, first external terminal electrodes arranged on the first side surface, second external terminal electrodes arranged on the second side surface, first internal electrodes arranged in the ceramic laminate, and second internal electrodes arranged in the ceramic laminate. The first internal electrodes include first opposed portions, first lead portions, and first projecting portions. The second internal electrodes include second opposed portions, second lead portions, and second projecting portions.

Abstract: There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units; and first to fourth outer electrodes, wherein the first capacitor unit includes at least one pair of first and second inner electrodes, the second capacitor unit includes at least one pair of third and fourth inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: Among a plurality of first inner electrodes, at least one first inner and a second inner electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth inner electrodes are arranged as opposed with at least one of the dielectric layers in between. The first inner electrodes are electrically connected to a first external connection conductor via lead conductors. The second inner electrode is electrically connected to a second terminal conductor via a lead conductor. The third inner electrode is electrically connected to a third terminal conductor via a lead conductor. The fourth inner electrode is electrically connected to a fourth terminal conductor via a lead conductor. Among all the first inner electrodes, one to multiple first inner electrodes that are less than the total first inner electrodes are electrically connected to the first terminal conductors via lead conductors.

Abstract: A through-type multilayer capacitor array comprises a capacitor body, and two first signal terminal electrodes, two second signal terminal electrodes, two grounding terminal electrodes, a first outer connecting conductor, and a second outer connecting conductor. The capacitor body includes a grounding inner electrode, and first to fourth signal inner electrodes. The grounding inner electrode is arranged to oppose the first or second signal inner electrode with an insulator layer in between and oppose the third or fourth signal inner electrode with an insulator layer in between while being connected to the grounding terminal electrodes. The first signal inner electrode is connected to the first signal terminal electrodes and first outer connecting conductor. The third signal inner electrode is connected to the second signal terminal electrodes and the second outer connecting conductor. The second and fourth signal inner electrodes are respectively connected to the first and second outer connecting conductor.

Abstract: A multilayer capacitor array comprises a capacitor body, and two first signal terminal electrodes, two second signal terminal electrodes, two grounding terminal electrodes, one first outer connecting conductor, and one second outer connecting conductor. The capacitor body includes first and, second signal inner electrodes, and first to third grounding inner electrodes. The first signal inner electrode is arranged to oppose the first or third grounding inner electrode with at least one insulator layer therebetween, while the second signal inner electrode is arranged to oppose the second or third grounding inner electrode with at least one insulator layer therebetween. The first and second signal inner electrodes, and first and second grounding inner electrodes are connected to the first and second signal terminal electrodes, and first and second outer connecting conductors, respectively.

Abstract: An electrode plate for an electricity storage and discharge device, which includes a plurality of I/O convergence terminals evenly distributed along a periphery of the electrode plate, and a plurality of conductive structures, each conductive structure for one of the I/O convergence terminals, wherein each conductive structure is of a radial pattern that centers on the one of the I/O convergence terminals, and radiates towards the interior of the electrode plate.

Abstract: Among a plurality of first inner electrodes, at least one first inner and a second inner electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth inner electrodes are arranged as opposed with at least one of the dielectric layers in between. The first inner electrodes are electrically connected to a first external connection conductor via lead conductors. The second inner electrode is electrically connected to a second terminal conductor via a lead conductor. The third inner electrode is electrically connected to a third terminal conductor via a lead conductor. The fourth inner electrode is electrically connected to a fourth terminal conductor via a lead conductor. Among all the first inner electrodes, one to multiple first inner electrodes that are less than the total first inner electrodes are electrically connected to the first terminal conductors via lead conductors.

Abstract: A multilayer capacitor having a dielectric body, an internal layer portion, external layer portions a first terminal electrode connected with a first internal conductor layer and a first external conductor layer, formed at least on a first side face of side faces of the dielectric body, and a second terminal electrode connected with a second internal conductor layer and a second external conductor layer, formed on a second side face opposed to the first side face of the dielectric body. The dielectric layer positioned at the external layer portions includes a plurality of pin hole conducting portions connecting a pair of first external conductor layers or a pair of second external conductor layers to each other adjacent to the dielectric layer, in an area of overlapping a pair of the first external conductor layers or a pair of the second external conductor layers adjacent to the dielectric layer.

Abstract: At least one of a plurality of first internal electrodes and a second internal electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth internal electrodes are arranged as opposed with at least one of the dielectric layers in between. The first internal electrodes are electrically connected to a first external connecting conductor through lead conductors. The second, third, and fourth internal electrodes are electrically connected to second, third, and fourth terminal conductors, respectively, through lead conductors. At last one but not all of the first internal electrodes are electrically connected to the first terminal conductor through a lead conductor.

Abstract: Methodologies and structures are disclosed for providing multilayer electronic devices having low inductance and high ratings, such as for capacitor devices for uses involving faster pulsing and higher currents. Plural layer devices are constructed for relatively lowered inductance by relatively altering typical orientation of capacitors such that their electrodes are placed into a vertical position relative to an associated circuit board. Optionally, individual leads may be formed so that the resulting structure can be used as an array. Internal electrodes may be arranged for reducing current loops for associated circuits on a circuit board, to correspondingly reduce the associated inductance of the circuit board mounted device. Leads associated with such devices may have added tab-like structures which serve to more precisely place the lead, to improve the lead to capacitor strength, and to promote lower resistance and inductance.

Abstract: A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.

Abstract: A multi-layer ceramic capacitor including: a ceramic sintered body having cover layers provided on upper and lower surfaces thereof as outermost layers and a plurality of ceramic layers disposed between the cover layers; first and second internal electrodes formed on the ceramic layers, the first and second internal electrodes stacked to interpose one of the ceramic layers; first and second external electrodes formed on opposing sides of the ceramic sintered body to connect to the first and second internal electrodes, respectively; and anti-oxidant electrode layers formed between the cover layers and adjacent ones of the ceramic layers, respectively, the anti-oxidant electrode layers arranged not to affect capacitance.

Abstract: A capacitor array with a multiplicity of capacitors with terminations of alternating polarity wherein the terminations are arranged in M columns and N rows. A circuit is provided with terminations in a grid of L columns and K rows wherein the terminations are of alternating polarity with the proviso that a first terminal with L={acute over (?)}M has the same polarity as a second terminal with L={acute over (?)}M+1 wherein {acute over (?)} is an integer.

Abstract: A capacitor block includes a first capacitor electrode connected to a first terminal, a first common capacitor electrode, a third capacitor electrode connected to a third terminal, a second common capacitor electrode, and a second capacitor electrode connected to a second terminal. One surface of the first capacitor electrode faces one surface of the first common capacitor electrode with a dielectric material therebetween. The other surface of the first common capacitor electrode faces one surface of the third capacitor electrode with a dielectric material therebetween. The other surface of the third capacitor electrode faces one surface of the second common capacitor electrode with a dielectric material therebetween. The other surface of the second common capacitor electrode faces one surface of the second capacitor electrode with a dielectric material therebetween. The first common capacitor electrode is electrically connected to the second common capacitor electrode.

Abstract: A capacitor is provided. The capacitor includes a dielectric polymer film comprising a cyanoresin and at least one electrode coupled to the dielectric polymer film. The capacitor has an energy density of at least about 5 J/cc. A method of making a capacitor is provided. The method includes dissolving a cyanoresin in a solvent to form a solution and coating the solution on a substrate to form a dielectric polymer film. The dielectric polymer film has a breakdown strength of at least about 300 kV/mm.

Abstract: A multilayer capacitor has a first inner electrode connected to a first terminal electrode, a second inner electrode connected to a second terminal electrode, and third and fourth inner electrodes connected to third and fourth terminal electrodes. The first and second inner electrodes have no overlapping area therebetween when seen in the opposing direction of the first and second main faces and are arranged at respective positions different from each other in the opposing direction of the first and second main faces and in the opposing direction of the first and second side faces. The third and fourth inner electrodes have no overlapping area therebetween when seen in the opposing direction of the first and second main faces and are arranged at respective positions different from each other in the opposing direction of the first and second main faces and in the opposing direction of the first and second side faces.

Abstract: A first signal internal electrode is connected to a first signal terminal electrode and a second signal internal electrode is connected to a second signal terminal electrode. A first ground internal electrode is connected to a first ground terminal electrode and a second ground internal electrode is connected to a second ground terminal electrode. The first signal internal electrode and the first ground internal electrode have their respective opposed regions. The second signal internal electrode and the second ground internal electrode have their respective opposed regions. The first signal internal electrode and the second ground internal electrode are not opposed to each other. The second signal internal electrode and the first ground internal electrode are not opposed to each other. The first signal internal electrode and the second signal internal electrode are connected through a signal throughhole conductor.

Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

Abstract: An apparatus and method includes an integrated circuit disposed in a ball grid array (“BGA”) package having interconnects on at least one corner without signal assignments.

Abstract: An electrical multiple-layer component is described herein. The component includes a base body having dielectric layers and internal electrodes. The internal electrodes are of connected to each other electrically between the dielectric layers via at least one external electrode on side surfaces of the base body. The component also includes an electrical connection between the external electrode and a contact surface on a surface of the base body and insulated relative to an outer side of the component.

Abstract: A composite electronic component has: a first multilayer section including an electrode layer; and a second multilayer section laid on the first multilayer section and including at least one ground electrode layer on which a ground electrode is formed, and at least one hot electrode layer on which a hot electrode is formed. In the second multilayer section, the hot electrode layer is interposed between the ground electrode layer nearest to the first multilayer section, and the first multilayer section and in the ground electrode on the ground electrode layer nearest to the first multilayer section, at least a part of an exposed portion exposed from the hot electrode to the first multilayer section side is a narrow portion narrower than a width of an unexposed portion not exposed therefrom.

Abstract: An interdigitated Metal-Insulator-Metal (MIM) capacitor provides self-shielding and accurate capacitance ratios with small capacitance values. The MIM capacitor includes two terminals that extend to a plurality of interdigitated fingers separated by an insulator. Metal plates occupy layers above and below the fingers and connect to fingers of one terminal. As a result, the MIM capacitor provides self-shielding to one terminal. Additional shielding may be employed by a series of additional shielding layers that are isolated from the capacitor. The self-shielding and additional shielding may also be implemented at an array of MIM capacitors.

Abstract: An element body has first and second inner electrodes which are alternately laminated. The first inner electrode has a first main electrode, a first coupling conductor extending to a first side face of the element body while being connected to an edge part of the first main electrode, and a first lead conductor extending to a third side face while being connected to the first coupling conductor. The second inner electrode has a second main electrode, a second coupling conductor extending to the first side face of the element body while being connected to an edge part of the second main electrode, and a second lead conductor extending to a fourth side face while being connected to the second coupling conductor. The first and second lead conductors are separated from the first and second main electrodes by gaps, respectively.

Abstract: A wiring board includes a plurality of via pads disposed on a ceramic sub-core accommodated in a core board. A Cu-plated layer is formed on the surface of a conductor pad and serves as a processed face, i.e., a face to which Cu surface chemical processing is applied in order to improve the adhesion between the surface of the Cu-plated layer and that of an adjacent polymer material. The lowermost dielectric layer of a laminated wiring portion, and a via conductor formed in the dielectric layer, are in electrical contact with the processed face.

Abstract: Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.

Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: A technique for enhancing circuit density and performance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for enhancing circuit density and performance of a microelectronic module. The method may comprise forming a discrete package, wherein the discrete package comprises one or more passive devices that are desirable for the performance of the microelectronic module. The method may also comprise coupling the discrete package to the microelectronic module.

Abstract: There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.

Abstract: There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.

Abstract: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Abstract: In a multilayer capacitor including a capacitor body, first capacitor portions and a second capacitor portion are arranged in the direction of lamination. While a resonant frequency of the first capacitor portions is set to be greater than a resonant frequency of the second capacitor portion so that the first capacitor portions contribute to low ESL, an ESR per layer of the second capacitor portion is set to be greater than an ESR per layer of the first capacitor portions so that the second capacitor portion contributes to high ESR. Furthermore, a combined ESR of the first capacitor portions is set to be less than or greater than a combined ESR of the second capacitor portion.

Abstract: A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Abstract: A multi-terminal capacitor includes a first capacitor plate, a second capacitor plate in parallel with the first capacitor plate, and a third capacitor plate in parallel with the first and second capacitor plates. The first, second and third capacitor plates are separated from each other by dielectric material, such that the first, second and third capacitor plates function as a first, second and third terminals, respectively, for capacitors formed therebetween.

Abstract: A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract: A multilayer capacitor comprises a capacitor body having rectangular first and second main faces opposing each other, first and second end faces extending in a shorter side direction of the first and second main faces so as to connect the first and second main faces to each other, and first and second side faces extending in a longer side direction of the first and second main faces so as to connect the first and second main faces to each other. First and second terminal electrodes are arranged on the first and second side faces of the capacitor body, respectively. A first inner electrode connected to the first terminal electrode, a second inner electrode connected to the second terminal electrode, and first and second intermediate electrodes connected to none of the first and second terminal electrodes are arranged within the capacitor body.

Abstract: A multilayer electronic component includes a base body, internal electrodes disposed inside the base body and extending to exterior surfaces thereof, and terminal electrodes provided on the exterior surfaces of the base body and connected to the internal electrodes. The terminal electrodes include first electrode layers defined by plating layers, and preferably electroplating layer, and second electrode layers made of a conductive resin and provided on the first electrode layers.

Abstract: A multilayer capacitor has a capacitor element, inner electrodes arranged within the capacitor element, and first to fourth terminal electrodes. Electrode parts of the first to fourth terminal electrodes cover ridges formed between first and third side faces, first and fourth side faces, second and third side faces, and second and fourth side faces. The capacitor element has an element part. The element part is formed such as to overlap the electrode parts when seen in a second and a third directions and keep away from respective areas about the electrode parts when seen in a first direction.

Abstract: A polymeric dielectric composition is disclosed, having a paraelectric filler with a dielectric constant between 50 and 150. Such compositions are well suited for electronic circuitry, such as, multilayer printed circuits, flexible circuits, semiconductor packaging and buried film capacitors.

Abstract: A multilayer capacitor has a capacitor element body of a nearly rectangular parallelepiped shape in which a signal electrode layer and a GND electrode layer are laminated with a dielectric layer in between, and signal terminal electrodes and GND terminal electrodes each set of which is provided on either of two side faces along the longitudinal direction of the capacitor element body. A signal electrode is led to each of the two side faces along the longitudinal direction of the capacitor element body and connected to the signal terminal electrodes. First GND electrode and second GND electrode are arranged alongside as spaced in a direction perpendicular to the longitudinal direction of the capacitor element body. The first GND electrode is led to one side along the longitudinal direction of the capacitor element body and connected to the GND terminal electrode.

Abstract: Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.

Abstract: Disclosed are energy conditioner structures, method of making and using them wherein the structure comprises a sequence of conductive layers including a first A layer, a G layer, and a first B layer; wherein said first A layer, said G layer, and said first B layer are each conductive, and are conductively isolated from one another in said energy conditioner structure; wherein said first A layer includes a first A layer main body and a first A layer tab, said first B layer includes a first B layer main body and a first B layer tab, and said G layer includes a G layer main body and a G layer first tab; wherein said G layer is in a plane between a plane containing said first A layer and a plane containing said first B layer; where the main body of at least one of said first A layer and said first B layer opposes a portion of said G layer main body; wherein two of said first A layer tab, said first B layer tab, and said G layer first tab are on a first side of said energy conditioner, and the remaining one of sai

Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.

Abstract: A multilayer capacitor has a capacitor element body, first and second terminal electrodes, and a connection conductor. The capacitor element body has a plurality of insulator layers laminated, and a plurality of first internal electrodes and second internal electrodes arranged as opposed with at least one of the insulator layers in between. The first and second terminal electrodes are disposed on one external surface extending in a direction parallel to a laminating direction of the insulator layers, among external surfaces of the capacitor element body. The connection conductor is disposed on an exterior surface extending in the direction parallel to the laminating direction of the insulator layers, among the external surfaces of the capacitor element body. The first internal electrodes include two types of internal electrodes, a type of internal electrode connected to the first terminal electrode and the connection conductor and a type of internal electrode connected to the connection conductor only.