Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: A method for manufacturing a multilayer ceramic electronic component significantly reduces and prevents swelling or distortion when a conductive paste is applied to a green ceramic element body. A ceramic green sheet used in the method satisfies 180.56?A/B wherein A is a polymerization degree of an organic binder contained in the ceramic green sheet, and B is a volume content of a plasticizer contained in the ceramic green sheet.

Abstract: A ceramic electronic component includes a substantially rectangular ceramic element assembly, a first external electrode, and a second external electrode. The first external electrode includes at least one plating film including a first plating film disposed directly on the ceramic element assembly from outside. Likewise, the second external electrode includes at least one plating film including a second plating film disposed directly on the ceramic element assembly from outside. The first and second plating films each have a surface area per unit area equal to or larger than about 1.02 in plan view.

Abstract: A multilayered ceramic electronic component includes: a ceramic element having a plurality of dielectric layers laminated therein; first inner electrodes formed on the dielectric layers disposed in upper and lower portions in the ceramic element, the width of a portion of each of the first inner electrodes exposed from one end face of the ceramic element being less than that of a portion thereof disposed within the ceramic element; and second inner electrodes formed on the dielectric layers disposed in the middle portion in the ceramic element, the width of a portion of each of the second inner electrodes exposed from one end face of the ceramic element being equal to that of a portion thereof disposed within the ceramic element.

Abstract: There is provided a multi-layered ceramic capacitor including: a ceramic body formed by multi-layering a plurality of dielectric layers; a plurality of first and second internal electrodes including at least one side exposed through edges of the dielectric layer; upper and lower cover layers formed at upper and lower portions of the ceramic body, respectively; first and second external electrodes formed to be spaced apart from each other at a lower surface of the lower cover layer; first and second connecting electrodes contacting outer peripheral surfaces of a plurality of second and first margin to connect exposed portions of the plurality of first and second internal electrodes, respectively; and an insulating side part formed so as to cover lateral surfaces at which the first and second internal electrodes are exposed.

Abstract: Provided is a package type multi-layer thin film capacitor for large capacitance, including: a ceramic sintered body formed with slots on one side and another side thereof, respectively; a plurality of first internal electrode layers formed within the ceramic sintered body; a plurality of second internal electrode layers formed within the ceramic sintered body to be positioned between the plurality of first internal electrode layers; a pair of first main connection electrode members inserted into the slots to be connected to the first internal electrode layers or the second internal electrode layers, respectively; a pair of first main lead members inserted into the slots and to be connected to the first main connection electrode members, respectively; and a sealing member sealing the ceramic sintered body to partially expose each of the pair of first main lead members.

Abstract: An element array and a footprint layout for an element array are disclosed. The element array can have a rectangular configuration defining two side surfaces and two end surfaces. The element array can include a plurality of stacked dielectric-electrode layers. One dielectric-electrode layer can include a plurality of element electrodes, such as eight element electrodes. Each of the plurality of element electrodes forms a part of an individual element for the element array. The element array device can further include a common electrode. The common electrode is used as part of each of the individual elements for the element array. The common electrode can include a lead for termination to one of the two end surfaces of the element array or, in a particular embodiment, to one of the two side surfaces of the element array.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: A laminated ceramic electronic component includes curved surface portions provided in an outer surface of a ceramic element assembly, and internal conductors provided within the ceramic element assembly that are exposed in the curved surface portions and principal surfaces to define starting points for plating deposition. A base layer, in an external conductor, which is defined by a plating film is arranged so as to directly cover the exposed portions of the internal conductors.

Abstract: A chip-type electronic component with high reliability, which is able to suppress and prevent fatal damage to a ceramic body due to cracking even if a substrate with the chip-type electronic component mounted thereon undergoes a deflection. The chip-type electronic component includes a ceramic body having internal electrodes; resin electrode layers formed in a region including at least end surfaces of the ceramic body, and connected to the internal electrodes directly or indirectly and connected with the ceramic body; and plating metal layers covering the resin electrode layers, wherein the adhesion strength between the ceramic body and the resin electrode layer is higher than the adhesion strength between the resin electrode layer and the plating metal layer.

Abstract: An electrical circuit arrangement provides a substrate and at least two conductive surfaces. The substrate comprises at least one layer disposed between the conductive surfaces. The conductive surfaces form a capacitor and overlap in part and form an overlapping area. In the event of a displacement of the conductive surfaces relative to one another, the resulting overlapping area is largely constant up to a threshold value of the displacement.

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

Abstract: An electronic component comprises: a laminate having a plurality of rectangular insulator layers and a mounting surface formed by a series of sides of the insulator layers. A plurality of first lead-out conductors are exposed between the insulator layers at the mounting surface. A first external electrode covers the first lead-out conductors at the mounting surface. The first external electrode is located at a first formation area at the mounting surface. The first formation area, when viewed in a plan view in an extending direction in which the sides of the insulator layers that constitute the mounting surface extend, is curved so as to bulge at a center of the formation area relative to opposite ends thereof.

Abstract: Disclosed herein are a stacked chip device including: a stacked body in which a plurality of sheets having an internal electrode made of a conductive material are stacked; external electrodes provided at both sides of the stacked body; and connection electrodes extending from the internal electrode and electrically connecting the internal electrode with the external electrodes, wherein the connection electrodes include: a plating solution permeation preventing section extending from the internal electrode, however, extending with a thickness smaller than the thickness of the internal electrode; and a contact reinforcement section extending from the plating solution permeation preventing section, however, extending in the form in which the thickness thereof is gradually extended toward the external electrode, and a manufacturing method thereof.

Abstract: A feedthrough capacitor includes an inner electrode that extends coaxially within a grounded outer electrode. A non-conductive, epoxy-based potting material insulates and adhesively joins opposing roughened portions of the inner and outer electrodes. A capacitor assembly extends between the inner and outer electrode and serves to bypass relatively high frequency signals carried by the inner electrode to the grounded outer electrode. The capacitor assembly includes a plurality of monolithic multilayer ceramic capacitors, each capacitor having first and second terminals that are respectively surface mounted onto inner and outer concentric conductive rings. A plurality of deflectable tines project radially inward from the inner ring and resiliently circumferentially contact the exterior of the inner electrode. Similarly, a plurality of deflectable tines project radially outward from the outer ring and resiliently circumferentially contact the interior of the outer electrode.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A multilayer capacitor is provided with improved reliability and reduced ESL. In a width direction, a second principal-surface electrode portion is greater than a first principal-surface electrode portion, and a fifth principal-surface electrode portion is greater than a fourth principal-surface electrode portion. When viewed from a lamination direction, an outer edge of the second principal-surface electrode portion at the other end side is arranged near the other end side more than outer edge of the fifth principal-surface electrode portion at one end side. First lead portions are connected to the second principal-surface electrode portion, and second lead portions are connected to the fifth principal-surface electrode portion.

Abstract: A multilayer capacitor comprises a capacitor element body, a first terminal electrode connected to a first inner electrode, a second terminal electrode connected to a second inner electrode, a third terminal electrode connected to a third inner electrode, and a fourth terminal electrode connected to a fourth inner electrode. The capacitor element body includes therewithin a first capacitor unit having first and second inner electrodes stacked adjacent to each other through a dielectric layer and a second capacitor unit having third and fourth inner electrodes stacked adjacent to each other through a dielectric layer. The first and second terminal electrodes have high resistance layers exhibiting electrical resistances higher than those of the third and fourth terminal electrodes.

Abstract: A modular EMI filtered terminal assembly for an active implantable medical device (AIMD) includes a hermetic terminal subassembly having at least one conductor extending through an insulator in non-conductive relation with the AIMD housing, and a feedthrough capacitor subassembly disposed generally adjacent to the hermetic terminal assembly. The feedthrough capacitor subassembly includes a conductive modular cup conductively coupled to the AIMD housing, and a feedthrough capacitor disposed within the modular cup. A first electrode plate or set of electrode plates is conductively coupled to the conductor, and a second electrode plate or set of electrode plates is conductively coupled to the modular cup.

Abstract: A first inner electrode is integrally provided with a first terminal connection part connected to a first terminal electrode and a first linking connection part connected to a first linking electrode. A second inner electrode is integrally provided with a second terminal connection part connected to a second terminal electrode and a second linking connection part connected to a second linking electrode. A third inner electrode is integrally provided with a third linking connection part connected to the first linking electrode. A fourth inner electrode is integrally provided with a fourth linking connection part connected to the second linking electrode. The third inner electrode is adjacent to the first and fourth inner electrodes in a laminating direction of the plurality of dielectric layers. The first and fourth inner electrodes overlap the third inner electrode as seen in the laminating direction of the plurality of dielectric layers.

Abstract: In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2?d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.

Abstract: An integrated capacitive device includes an electrically conducting comb, at least some of whose teeth form first electrodes of capacitors, and electrically conducting fingers extending between the teeth of the comb so as to form second electrodes of the capacitors. The device includes a first finger-teeth set having a single reference finger forming a reference capacitor having a reference capacitive value, at least one second finger-teeth set including several fingers, the reference finger and the number of fingers of the second finger-teeth set or sets forming a geometric series with ratio two. At least one additional set includes a single additional finger forming, with at least one tooth of the comb, an additional capacitor having an additional capacitive value substantially equal to half the reference capacitive value.

Abstract: An electronic component includes a ceramic body including first to fourth side surfaces, a first external electrode provided on one side surface of the ceramic body, a second external electrode, and a plurality of reinforcing electrodes. Each of the first and second external electrodes includes a thick-film electrode layer including sintered metal, a plated layer arranged so as to cover the thick-film electrode layer, an external electrode main body portion covering the side surface of the ceramic body, and turnback portions extending to the top surface and the bottom surface of the ceramic body. An end portion of at least one reinforcing electrode of the plurality of reinforcing electrodes is exposed on the top surface or the bottom surface of the ceramic body on the center portion of the ceramic body in relation to the thick-film electrode layer in the turnback portion.

Abstract: The present invention relates to a capacitor arrangement having a capacitor and a first terminal plate and a second terminal plate. The capacitor has a first contact face and a second contact face arranged opposite one another. The terminal plates are each connected to one of the contact faces and have protrusions on one end suitable for engaging in recesses in a power rail.

Abstract: In a capacitor body of a multilayer capacitor, one second capacitor portion is sandwiched between two first capacitor portions. An ESR is controlled by setting a width of lead portions of third and fourth internal electrodes disposed in the second capacitor portion to be less than that of lead portions of first and second internal electrodes disposed in the first capacitor portions and by changing ratios between the first and second capacitor portions in the width of the lead portions and in the number of stacked internal electrodes. In the first capacitor portions, current paths from the internal electrodes to an external terminal electrode are widely distributed so that the first capacitor portions have a relatively low ESL, and accordingly, the ESL of the entire multilayer capacitor is reduced.

Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same, the multilayer ceramic electronic including: a ceramic body; and a plurality of internal electrodes laminated within the ceramic body, wherein, when T1 is the greatest distance between an upper outermost internal electrode and a lower outermost internal electrode among the plurality of internal electrodes and T2 is the distance between the highest point and the lowest point in each of the upper outermost internal electrode and the lower outermost internal electrode in a thickness direction of the ceramic body, T2/T1<0.05 is satisfied, and thus, defects in alignment of internal electrodes of the multilayer ceramic electronic component may be suppressed.

Abstract: A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; first and second internal electrodes provided within the ceramic body and including respective lead-out portions exposed to a first surface of the ceramic body and a third or fourth surface thereof connected to the first surface and having an overlapping area, the overlapping area being exposed to the first surface of the ceramic body; first and second external electrodes extended from the first surface of the ceramic body to the third or fourth surface thereof connected to the first surface and connected to the respective lead-out portions; and an insulation layer formed on the first surface of the ceramic body and the third and fourth surfaces thereof connected to the first surface.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including dielectric layers and internal electrodes stacked between the dielectric layers; and a pair of external electrodes each fixed to first and second surfaces of the ceramic body, facing each other, and connected to the internal electrodes, wherein the ceramic body has a third surface facing a printed circuit board and each of the pair of external electrodes includes mounting parts extended onto the third surface and having a preset length by which they are mounted on the printed circuit board and wherein connection parts between the pair of external electrodes and the mounting parts have a convexly curved shape having a size equal to or smaller than a preset corner radius.

Abstract: To provide a thin-film capacitor capable of improving the stability of electric connection between an internal electrode layer and a connection electrode. The thin-film capacitor comprises: two or more dielectric layers deposited above a base electrode; an internal electrode layer being deposited between the dielectric layers and having a projecting portion which projects from the dielectric layer when seen from a laminating direction; and a connection electrode electrically connected to the internal electrode layer via at least a part of a surface and an end face of the internal electrode layer included in the projecting portion, wherein a ratio L/t between a projection amount L of the projecting portion of the internal electrode layer with respect to the dielectric layer and a thickness t of the internal electrode layer is 0.5 to 120.

Abstract: In a monolithic ceramic electronic component, where a distance in the height direction between one of outer-layer dummy conductors in an outer layer portion, which is arranged closest to an inner layer portion, and one of inner electrodes in the inner layer portion, which is arranged closest to the outer layer portion, is b, and an opposing distance between an adjacent pair of first inner electrodes and second inner electrodes in the height direction is t, 2t?b is satisfied, such that the outer-layer dummy conductors can be spaced a sufficient distance away from the inner electrodes, and such that the distance between the inner electrodes can be prevented from being reduced when the inner electrodes arranged in overlapping relation to the outer-layer dummy conductors are pressed in a pressing step before firing, and a reduction of BDV can be prevented.

Abstract: There is provided a multilayer ceramic electronic part, including: a ceramic element having a plurality of dielectric layers laminated therein; a plurality of first and second internal electrodes each formed on at least one surface of each of the plurality of dielectric layers within the ceramic element, the first and second internal electrodes respectively including first and second lead parts extended therefrom to be exposed through one surface of the ceramic element; and first and second external electrodes formed on one surface of the ceramic element, and electrically connected to the first and second internal electrodes through exposed portions of the first and second lead parts, respectively, wherein a ratio of a width of the first or second lead part to a width of the first or second external electrode is 10 to 85%.

Abstract: An electrical multilayer component has a monolithic main body that includes a number of alternating ceramic layers disposed one above the other and at least one electrode layer. The main body has two end faces opposite each other and two lateral faces opposite each other. The component also includes a number of outer electrodes and at least three inner electrodes. Each of the inner electrodes is associated with one outer electrode. A first inner electrode protruding from an end face and a second inner electrode protruding from an opposite end face have a first distance to each other. A third inner electrode protrudes from a side face.

Abstract: A conductive structure, including an adhesion layer and a conductor in contact with the adhesion layer and having a thickness of less than six hundred Angstroms. The present invention may be used to form a capacitor, including an adhesion layer, a first conductor in contact with the adhesion layer and having a thickness of less than six hundred Angstroms, a second conductor, and a dielectric between the first and second conductors. The present invention is also directed towards structures wherein iridium or rhodium may be used in place of the combination of the adhesion layer and conductor.

Abstract: The disclosure provides a method for producing an electronic component in which the oxidation of Cu constituting an internal conductor part of the component is inhibited or prevented in a firing step, and even when a magnetic body part containing NiO, ZnO, Fe2O3, etc. is reduced in the firing step, the magnetic body part is subsequently oxidized to ensure the original characteristics. In producing the electronic component, an unfired laminated body including parts to serve as the magnetic body part and the internal conductor part after firing is subjected to firing in an atmosphere with an oxygen concentration equal to or lower than the equilibrium oxygen partial pressure of Cu—Cu2O, and the fired laminated body is then subjected to an oxygenic-atmosphere heat treatment in an atmosphere with an oxygen concentration of 0.01% or more in a step of decreasing the temperature.

Abstract: Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.

Abstract: A ceramic electronic component includes a ceramic element assembly and external electrodes. The external electrodes are disposed on the ceramic element assembly. The external electrodes include an underlying electrode layer and a first Cu plating film. The underlying electrode layer is disposed on the ceramic element assembly. The first Cu plating film is disposed on the underlying electrode layer. The underlying electrode layer includes a metal that is diffusible in Cu and a ceramic bonding material. The metal that is diffusible in Cu is diffused in at least a surface layer in the underlying electrode layer side of the first Cu plating film.

Abstract: In a laminate type ceramic electronic component, when an external electrode for a laminated ceramic capacitor is formed directly by plating onto a surface of a component main body, the film that is directly plated may have a low fixing strength with respect to the component main body. As the external electrode, a first plating layer composed of a Ni—P plating film with a P content rate of about 9 weight % or more is first formed such that a plating deposition deposited with the exposed ends of respective internal electrodes as starting points is grown on at least an end surface of a component main body. Then, a second plating layer composed of a Ni plating film containing substantially no P is formed on the first plating layer. Preferably, the first plating layer is formed by electroless plating, whereas the second plating layer is formed by electrolytic plating.

Abstract: Disclosed herein are a multilayer ceramic electronic component and a method for manufacturing the same. The multilayer ceramic electronic component includes a multilayer body in which dielectric layers and internal electrode layers are alternately stacked and external electrodes, wherein a portion in the internal electrode layers positioned in a marginal portion in which vertically neighboring internal electrode layers in the multilayer body is not overlapped with each other has a thickness thicker than that of a portion of the internal electrode layer positioned in an overlapped portion in which the vertically neighboring internal electrode layers are overlapped with each other, such that an accumulated stepped height difference in the marginal portion is reduced.

Abstract: Provided is a multilayer capacitor that can be manufactured with high yields and whose warpage is suppressed. The multilayer capacitor includes two or more laminated bodies which are bonded together, the two or more laminated bodies each including resin layers and metal layers which are alternately laminated a plurality of times in a thickness direction and each being warped and having front and rear surfaces covered with surface layers containing a resin material, one of the front and rear surfaces being formed of a first surface as a smooth surface having no recess portion, another of the front and rear surfaces being formed of a second surface having a recess portion, in which at least two adjacent laminated bodies are bonded together at the first surfaces or the second surfaces. Also provided are a manufacturing method for the multilayer capacitor, and a circuit board and an electronic device which use the multilayer capacitor.

Abstract: A method for manufacturing a laminated electronic component includes the steps of preparing a laminated component main body, the component main body including internal electrodes formed therein, and each of the internal electrodes being partially exposed on an external surface of the component main body, and forming an external terminal electrode on the external surface of the component main body such that the external terminal electrode is electrically connected to the internal electrodes. The step of forming the external terminal electrode includes the steps of forming a metal layer on exposed surfaces of the internal electrodes, applying a water repellant on a surface of the metal layer and a section of the external surface of the component main body at which an end edge of the metal layer is located, and then forming a conductive resin layer on the metal layer having the water repellant applied thereon.

Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.

Abstract: A multilayered body includes capacitor conductors and an internal conductor, which together define a capacitor. A first external electrode is connected to one of the capacitor conductors via a set of lead electrodes. A second external electrode is connected to the other capacitor conductor via another set of lead electrodes. The internal conductor faces the capacitor conductors.

Abstract: There is provided a multilayered ceramic electronic component including: a ceramic main body having a dielectric layer, the ceramic main body having a length of 1.79 mm or less and a width of 1.09 mm or less; first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic main body; and a first external electrode electrically connected to the first internal electrode and a second external electrode electrically connected to the second internal electrode, wherein, when it is defined that the shortest length of at least one of the first and second external electrodes, formed in the lengthwise direction from both end portions of the ceramic main body is A, and the longest length thereof is BW, a relational expression of 0.5?A/BW<1.0 may be satisfied.

Abstract: There is provided multilayered ceramic electronic component having a 0603 size or less, the multilayered ceramic electronic component including: a ceramic body including a plurality of internal electrodes and dielectric layers disposed between the internal electrodes; and external electrodes disposed on outer surfaces of the ceramic body and electrically connected to the internal electrodes, wherein when a region in which the internal electrodes are overlapped is defined as an active region in a cross section of a central portion in a length direction of the ceramic body, taken in width and thickness directions thereof, the entire area of the cross section taken in the width and thickness directions is defined as At, and an area of the active region is defined as Aa, the following equation is satisfied: 65%?Aa/At?90%.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A ceramic electronic component includes two electronic-component main bodies and two metal terminals. Each of the metal terminals includes a base, ribs on left and right sides of the base, and a mounting portion below the base. The base includes two bonding portions to be bonded to respective external electrodes of the two electronic-component main bodies and cut-out portions each having a closed shape and being disposed below the respective bonding portions. The ribs are bent from the left and right sides of the base in the width direction toward the electronic-component main body. The ribs extend from the top of the base in the height direction to the vicinity of the mounting-side major surface of the mounting-side electronic-component main body and do not reach the mounting portion. The mounting portion is bent from the bottom of the base toward the electronic-component main body.

Abstract: A ceramic electronic component includes a ceramic element assembly and external electrodes. The external electrodes are disposed on the ceramic element assembly. The external electrodes include an underlying electrode layer and a first Cu plating film. The underlying electrode layer is disposed on the ceramic element assembly. The first Cu plating film is disposed on the underlying electrode layer. The underlying electrode layer includes a metal that is diffusible in Cu and a ceramic bonding material. The metal that is diffusible in Cu is diffused in at least a surface layer in the underlying electrode layer side of the first Cu plating film.

Abstract: A ceramic electronic component 100 includes a ceramic body 1 in which internal electrodes containing a metal component is buried, and a pair of terminal electrodes 3 provided to cover both end surfaces 11 of the ceramic body to which the internal electrodes are exposed. Each of the terminal electrodes 3 has a first electrode layer and a second electrode layer formed by baking a conductive green sheet from a side close to the ceramic body 1. The second electrode layer contains the metal component diffused from the internal electrodes.

Abstract: In a method for manufacturing a laminated ceramic electronic component, after a plating layer for an external terminal electrode is formed by applying copper plating to an end surface of a component main body at which respective ends of a plurality of internal electrodes primarily including nickel are exposed, when a heat treatment at a temperature of about 800° C. or more is applied in order to improve adhesion strength and resistance to moisture of the external terminal electrode, voids may occur in the plating layer. The step of applying a heat treatment at a temperature of about 800° C. or more to a component main body with plating layers formed thereon includes not only a step of maintaining a top temperature of about 1000° C. or more but also a step of maintaining a temperature of about 600° C. to 900° C. at least once before the step of maintaining the top temperature.