Abstract: A multilayer capacitor includes an active portion including a dielectric layer and first and second internal electrodes stacked with the dielectric layer interposed therebetween in a first direction, a first external electrode covering the active portion and connected to the first internal electrode, a connection electrode covering the active portion and connected to the second internal electrode, a side margin portion covering the connection electrodes on the active portion, and a second external electrode covering the side margin portions and connected to the connection electrode.

Abstract: A multilayer electronic component includes a body including a dielectric layer and a first internal electrode and a second internal electrode having first to sixth surfaces, a first external electrode including a first connection portion on the third surface, a first band portion on a portion of the first surface, and a third band portion on a portion of the second surface, a second external electrode including a second connection portion on the fourth surface, a second band portion on a portion of the first surface, and a fourth band portion on a portion of the second surface, an insulating layer disposed on the first and second connection portions and covering the second surface and the third and fourth band portions, a first plating layer disposed on the first band portion, and a second plating layer disposed on the second band portion. The insulating layer includes an oxide containing Ba.

Abstract: A coil component is capable of reducing specific resistance of a coil and reliably mitigating stress. A coil component includes a base body and a coil disposed in the base body. The base body includes a plurality of magnetic layers laminated in a first direction. The coil includes a plurality of coil wires laminated in the first direction. The coil wires extend along a plane orthogonal to the first direction. Each of the coil wires includes a first coil conductor layer and a second coil conductor layer laminated in the first direction. Specific resistance of the first coil conductor layer is smaller than specific resistance of the second coil conductor layer.

Abstract: A multilayer capacitor includes: a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately laminated in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes spaced apart from each other and respectively disposed on first and second surfaces of the body, the first and second surfaces opposing each other. The body further includes a first via electrode, connecting the at least one first internal electrode and the first external electrode to each other in the first direction, and a second via electrode connecting the at least one second internal electrode and the second external electrode to each other in the first direction.

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

Abstract: A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.

Abstract: A multilayer ceramic capacitor includes a multilayer body including ceramic layers and internal electrode layers laminated therein, a pair of external electrodes electrically connected to the internal electrode layers and provided on two end surfaces of the multilayer body. The pair of external electrodes each include a base electrode layer including a metal component, an electrically conductive resin layer on the base electrode layer and including a thermosetting resin and a metal component, and a Ni-plated layer on the electrically conductive layer. A stress of about ?150 MPa or more and about 50 MPa or less is applied to the Ni-plated layer, and an end portion of the Ni-plated layer being in contact with the multilayer body.

Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and including first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces. A plurality of internal electrodes is disposed inside the ceramic body, connected to the first and second surfaces, and have one ends connected to the third and fourth surfaces. First and second side margin parts are disposed on end portions of the internal electrodes connected to the first and second surfaces. The ceramic body includes an active portion forming capacitance by including the plurality of internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween. An average Sn content in a region adjacent to the side margin part of the active portion is greater than an average Sn content in a central region of the active portion.

Abstract: Provided is an improved multilayered ceramic capacitor and an electronic device comprising the multilayered ceramic capacitor. The multilayer ceramic capacitor comprises first conductive plates electrically connected to first external terminations and second conductive plates electrically connected to second external terminations. The first conductive plates and second conductive plates form a capacitive couple. A ceramic portion is between the first conductive plates and said second conductive plates wherein the ceramic portion comprises paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC VPP wherein the rated AC VPP is higher than the rated DC voltage.

Abstract: An inductor component in which degradation of the insulation property, the inductance acquisition efficiency, and mechanical strength is suppressed. An inductor component includes a flat plate-shaped main body containing magnetic powder and a resin piece containing the magnetic powder; an inductor wire arranged in the main body; and an external terminal electrically connected to the inductor wire and exposed from a main surface of the main body. An average particle size X of the magnetic powder, a thickness T orthogonal to the main surface of the main body, and a first arithmetic mean roughness Ra1 of a part of a straight line on the main surface passing through the external terminal and excluding a part overlapping with the external terminal satisfying Formula (1): X/10?Ra1?T/10 . . . Formula (1).

Abstract: According to an aspect of the present disclosure, a capacitor component includes a body including a dielectric layer and an internal electrode layer; and an external electrode disposed on the body and connected to the internal electrode layer, wherein the body further includes a withstand voltage layer disposed in a region spaced apart by more than 0 to 30 nm or less in a direction from a boundary of the internal electrode layer toward the dielectric layer, and having ionic mobility, lower than ionic mobility of the dielectric layer.

Abstract: A varistor array can include a monolithic body including a plurality of dielectric layers. A first varistor can be formed in the monolithic body. The first varistor can include a first external terminal on a first end of the monolithic body, a first plurality of electrodes connected with the first external terminal, a second external terminal on a second end of the monolithic body, and a second plurality of electrodes connected with the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes at an overlapping area that is insensitive to a relative misalignment between the first plurality of electrodes and the second plurality of electrodes when the misalignment is less than a threshold. A second varistor can be formed in the monolithic body that is distinct from the first varistor.

Abstract: A multilayer electronic component includes a plurality of dielectric layers and a plurality of electrode layers that are alternately stacked. A skewness of a distribution of thicknesses of the plurality of dielectric layers at a plurality of arbitrary locations of the plurality of dielectric layers is 0.2 or more.

Abstract: A multilayer capacitor includes a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately laminated in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes spaced apart from each other and disposed on the body to be connected to the at least one first internal electrode and the at least one second internal electrode, respectively, wherein the body further includes a buffer layer disposed in the capacitance region and having a Young's modulus of greater than 0 time and (50/135) times or less of a Young's modulus of the at least one dielectric layer.

Abstract: A ceramic electronic device includes a multilayer structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked. Each of the plurality of dielectric layers includes ceramic grains of a main component thereof expressed by (Ba1-x-yCaxSry)(Ti1-zZrz)O3 (0<x?0.2, 0?y?0.1, 0?z?0.1). D3<D1<D2 is satisfied when an average grain diameter of the ceramic grains of the main component of the plurality of dielectric layers in a section in which each two internal electrode layers is D1, an average grain diameter of the ceramic grains of the main component of first dielectric layers which are located at different height positions from the internal electrode layers is D2, an average grain diameter of the ceramic grains of the main component of second dielectric layers which are located at same height positions of the internal electrode layers is D3.

Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween and including a capacitance forming portion, by which capacitance of the multilayer electronic component is defined, having the first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, cover portions disposed on two opposing surfaces of the capacitance forming portion in a first direction, and margin portions disposed on two opposing surfaces of the capacitance forming portion in a second or third direction, in which ?3.0<{1?(Hc/H1)}×100?0.4, where an average hardness of the cover portions is Hc and an average hardness of the first margin portions is H1.

Abstract: A multilayer electronic component includes a body including a dielectric layer and internal electrodes disposed alternately with the dielectric layer therebetween and including first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, and external electrodes disposed on the body. One end of each internal electrode is connected to the third or fourth surface. The external electrodes include a first electrode layer disposed on the third and fourth surfaces and including a conductive metal and a second electrode layer disposed on the first electrode layer, including silver (Ag) and glass, and further including one or more of palladium (Pd), platinum (Pt), and gold (Au), and the first electrode layer is disposed to cover all of one end of each internal electrode connected to the third and fourth surfaces and does not extend to the other surfaces.

Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode, an external electrode disposed outside the body, and an insulating layer disposed on the external electrode. The external electrode is disposed to cover an exposed surface of an outermost surface of the electrode layer, and is formed to have a thickness, equal to or less than a thickness of the body, and the insulating layer is disposed to cover an end of the external electrode, to improve moisture resistance reliability.

Abstract: A multilayer capacitor includes a body including dielectric layers and internal electrodes and external electrodes disposed on an external surface of the body and connected to the internal electrodes. The body includes a first surface and a second surface to which the internal electrodes are exposed, the first surface and the second surface opposing each other in a first direction, a third surface and a fourth surface opposing each other in a second direction which is a direction in which the dielectric layers are stacked, and a fifth surface and a sixth surface opposing each other in a third direction. At least one of the internal electrodes include a first bottleneck structure having a first directional length of a third-directional outer region smaller than an inner region thereof and a second bottleneck structure having a third directional length of a first directional outer region smaller than an inner region thereof.

Abstract: There is provided a card or token for use in financial transactions. The financial transaction token or card has an onboard energy storage device that enables onboard electronics to operate when the card is not in the proximity of a merchant Point-Of-Service (POS) terminal. In one implementation, the onboard energy storage device includes a capacitor such as a thin-film capacitor that stores sufficient energy to power onboard electronics without the need for an onboard battery. The card may be incorporated within various conventional apparatus such as a see-through and/or protective substrate, an item of clothing, an item of jewelry, a cell phone, a Personal Digital Assistant (PDA), a credit card, an identification card, a money holder, a wallet, a personal organizer, a keychain payment tag, and like personality.

Abstract: A multilayer electronic component includes a body including a plurality of first dielectric layers, an active portion in which internal electrodes are alternately disposed, and a cover portion disposed the active portion in a first direction of the body, a direction in which the plurality of first dielectric layers are laminated, and including a second dielectric layer; and an external electrode disposed externally on the body and connected to one of the internal electrodes. The body includes a margin portion covering a side surface of the one of the internal electrodes other than a side surface connected to the external electrode and including a dielectric pattern having a porosity higher than that of one of the plurality of first dielectric layers.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes stacked in a first direction and having first and second surfaces opposing each other in the first direction, third and fourth surfaces opposing each other in a second direction, and fifth and sixth surfaces opposing each other in a third direction, and first and second external electrodes disposed on the third and fourth surfaces of the body, respectively, and connected to the first and second internal electrodes, respectively. The first and second external electrodes each include a central portion disposed in a center of each of the third and fourth surfaces and an outer portion disposed outside the central portion. T1>T2>T3, in which T1 and T3 are maximum value and minimum value of a thickness of the central portion, respectively, and T2 is a maximum value of a thickness of the outer portion.

Abstract: An electronic component includes an element body, an external electrode, and a resin film having electrical insulation properties. The element body includes a principal surface and a side surface adjacent to the principal surface. The external electrode includes a first electrode portion disposed on the principal surface and a second electrode portion disposed on the side surface. The resin film is disposed on the principal surface and is in contact with the principal surface. Each of the first electrode portion and the second electrode portion includes a conductive resin layer disposed on the element body. A conductive resin layer included in the first electrode portion is disposed on the resin film and is in contact with the resin film.

Abstract: A multilayer ceramic electronic component includes a multilayer body including layered ceramic layers and layered inner electrode layers and having a rectangular parallelepiped shape, and outer electrodes covering both end surfaces of the multilayer body and extending from both end surfaces to cover at least a portion of a first main surface of the multilayer body. The multilayer ceramic capacitor includes an insulating layer continuously extending from a ceramic layer at the first main surface of the multilayer body so as to cover end edge portions of both the outer electrodes located on the first main surface of the multilayer body, and t2>t1 is satisfied.

Abstract: A method of manufacturing a multilayer ceramic capacitor includes preparing a ceramic green sheet in which a plurality of internal electrode patterns are formed with a predetermined distance therebetween, forming a ceramic laminate by laminating a plurality of the ceramic green sheets in a first direction, cutting the ceramic laminate to have a side surface from which an end of the internal electrode pattern is exposed in a second direction perpendicular to the first direction, forming a margin portion on the side surface from which the end of the internal electrode pattern is exposed, and forming a ceramic body including a dielectric layer and an internal electrode by firing the cut-out ceramic laminate. The forming a margin portion includes flowing a ceramic paste from an upper portion to a lower portion of the cut-out ceramic laminate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: A manufacturing method of a laminated sheet having a printed layer includes, given that a table that associates density data of a specific area included in image data with a burnup degree of the printed layer corresponding to the specific area at printing based on the image data is an image-burnup degree conversion table, identifying the image-burnup degree conversion table that satisfies a printing condition for the laminated sheet, acquiring printed image data that is image data for forming the printed layer of the laminated sheet, and calculating the burnup degree of the printed layer based on the image-burnup degree conversion table and the printed image data. Also disclosed is a laminated sheet having a printed layer, a system for manufacturing the laminated sheet, and a program for manufacturing the laminated sheet.

Abstract: To provide a multilayer electronic component of which a reliability is not compromised and also a crack is suppressed from forming even when the multilayer electronic component is made thinner. A multilayer electronic component including an element body in which at least one dielectric layer and at least one internal electrode layer are stacked in an alternating manner, wherein a thickness variation of the at least one internal electrode layer is larger than a thickness variation of the at least one dielectric layer.

Abstract: The present invention is directed to a multilayer ceramic capacitor. The multilayer ceramic capacitor has a first end and a second end that is spaced apart from the first end in a longitudinal direction that is perpendicular to a lateral direction wherein the lateral direction and longitudinal direction are each perpendicular to a Z-direction. The multilayer ceramic capacitor comprises a monolithic body comprising a plurality of dielectric layers and a plurality of electrode layers parallel with the lateral direction.

Abstract: A multilayer ceramic capacitor package accommodating multilayer ceramic capacitors includes a carrier tape that is elongated and includes recess pockets at equal or substantially equal intervals in a longitudinal direction, a cover tape that is elongated and attached to the carrier tape to cover an opening of each of the pockets, and the multilayer ceramic capacitors respectively accommodated in the pockets. In the multilayer ceramic capacitor package, in adjacent multilayer ceramic capacitors, a difference in densities of surfaces on an opening side of the pockets is about 0% or more and about 4% or less.

Abstract: A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. A ceramic protection section includes a cover layer and a side margin. A main component ceramic of the ceramic protection section is a ceramic material having a perovskite structure expressed as a general formula ABO3. An A site of the perovskite structure includes at least Ba. A B site of the perovskite structure includes at least Ti and Zr. A Zr/Ti ratio which is a molar ratio of Zr and Ti is 0.010 or more and 0.25 or less. An A/B ratio which is a molar ratio of the A site and the B site is 0.990 or less.

Abstract: A capacitor component includes a body including internal electrode layers and a dielectric layer disposed between the internal electrode layers adjacent to each other and an external electrode disposed on one surface of the body, wherein the internal electrode layer and the dielectric layer separately include molybdenum (Mo), the dielectric layer has a central portion in a thickness direction and an outer portion disposed between the central portion and the internal electrode layer, and the content of molybdenum contained in the central portion of the dielectric layer is less than the content of molybdenum (Mo) contained in the outer portion of the dielectric layer.

Abstract: A multilayer electronic component includes: a body including dielectric layers; side margin portions disposed on side surfaces of the body, respectively; and external electrodes disposed on end surfaces of the body, respectively. The body includes a capacitance forming portion including internal electrodes disposed alternately with the dielectric layers and cover portions disposed on upper and lower surfaces of the capacitance forming portion, respectively. Ga2/Ga1 is 0.8 or more and less than 1.0 and Ga2/Gc1 is 0.8 or more and less than 1.0. a1 is a central portion of the capacitance forming portion, a2 is a boundary portion between the capacitance forming portion and the cover portion in the capacitance forming portion, and c1 is a boundary portion between the capacitance forming portion and the cover portion in the cover portion. Ga1, Ga2, and Gc1 are average sizes of dielectric grains at a1, a2, and c1, respectively.

Abstract: A multilayer ceramic capacitor includes a multilayer body and external electrodes. The multilayer body includes an inner layer portion including dielectric layers and internal electrode layers alternately stacked, and first and second outer layer portions on opposite sides of the inner layer portion in a stacking direction, side gap portions on opposite sides in a width direction, main surfaces on opposite sides in the stacking direction, side surfaces on opposite sides in the width direction, and end surfaces on opposite sides in a length direction. Each external electrode is provided at one end surfaces of the multilayer body, and extends from the end surface to a portion of the main surface. A difference in location between ends at the side surface of two adjacent internal electrode layers is about 0.5 ?m or less. The second outer layer portion is thicker than the first outer layer portion.

Abstract: A ceramic electronic component includes a body including dielectric layers and a plurality of internal electrodes and an external electrode including a connection portion and a band portion. The external electrode includes an electrode layer, a conductive resin layer, a nickel plating layer, and a tin plating layer. When an electrode layer thickness, a conductive resin layer thickness, a nickel plating layer thickness, a tin plating layer thickness of the band portion are defined as t3, t4, and t5, respectively, t5 is greater than or equal to 0.5 micrometer and less than 7 micrometer, and t5/(t3+t4) satisfies 1?t5/(t3+t4)*100<17.5 in the case in which t3+t4 is less than or equal to 100 micrometers and satisfies 0.3?t5/(t3+t4)*100<4.38 in the case in which t3+t4 is more than 100 micrometers.

Abstract: Provided is a multilayer ceramic capacitor having dielectric layers and internal electrode layers laminated alternately on one another. Each internal electrode layer comprises a common ceramic material containing 3 to 25% by weight of rare earth elements, and through the rare earth elements, high dielectric layers are formed on the interfaces between the dielectric layers and the internal electrode layers.

Abstract: A multilayer capacitor includes a capacitor body including first to sixth surfaces and including a plurality of dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween, and first and second external electrodes disposed on the third and fourth surfaces of the capacitor body and connected to the first and second internal electrodes, respectively, wherein the capacitor body includes an active region in which the first and second internal electrodes overlap in a first direction, and at least a portion of a margin portion excluding the active region in the capacitor body has a ratio of Ba to Ti less than 1 (Ba/Ti<1) and has a twin boundary structure.

Abstract: Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.

Abstract: Provided is a high-density multi-component package comprising a first module interconnect pad and a second module interconnect pad. At least two electronic components are mounted to and between the first module interconnect pad and the second module interconnect pad wherein a first electronic component is vertically oriented relative to the first module interconnect pad. A second electronic component is vertically oriented relative to the second module interconnect pad.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer including a grain and first and second internal electrodes stacked in a third direction with the dielectric layer interposed therebetween, and including a first surface and a second surface opposing each other in a third direction, a third surface and a fourth surface opposing each other in a second direction, and a fifth surface and a sixth surface opposing each other in a first direction; and first and second external electrodes disposed on the fifth surface and the sixth surface of the ceramic body, respectively, and a ratio, G/I, of a particle size, G, of a grain of the dielectric layer to a thickness, I, of each of the first and second internal electrodes is 0.3 or more and 0.5 or less.

Abstract: A multilayer ceramic electronic component includes a ceramic body includes: a ceramic body including a capacitance formation portion including a dielectric layer and first and second internal electrodes disposed to be stacked in a third direction with the dielectric layer interposed therebetween, a margin portion disposed on both surfaces of the capacitance formation portion in a second direction, and a cover portion disposed on both surfaces of the capacitance formation portion in the third direction, and; and an auxiliary electrode spaced apart from the capacitance formation portion, and disposed to be in contact with one of the first and second external electrodes. The auxiliary electrode is spaced apart from first surface and the second surface of the ceramic body in a first direction.

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, and external electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers, the external electrode layers each further including a base electrode layer including a first region, a second region, and a third region divided therein, in order from the multilayer body. The first region includes a metal included in the internal electrode layers in a higher amount than the second region and the third region, the second region includes glass in a higher amount than the first region and the third region, and the third region includes copper in a higher amount than the first region and the second region.

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 ?m or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

Abstract: A multilayer electronic component includes: a body including dielectric layers and internal electrodes alternately disposed with the dielectric layers; and external electrodes disposed on the body. One of the internal electrodes includes interfacial portions disposed at interfaces thereof with two of the dielectric layers, between which the one of the internal electrodes is disposed, and a central portion disposed between the interfacial portions, and one of the interfacial portions has a Mn content higher than an average Mn content of the central portion and an average Mn content of one of the dielectric layers which is in contact with the one of the interfacial portions.

Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.

Abstract: A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are stacked, the plurality of internal electrode layers being exposed to at least one of a first end face and a second end face of the multilayer structure, the first end face being opposite to the second end face, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and a fluorine compound that is adhered to at least a part of a region including a surface of the multilayer chip where neither the first external electrode nor the second external electrode is formed and surfaces of the first external electrode and the second external electrode, fluorine compound being released at a temperature of 380 degrees C. or more.

Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes laminated in a first direction, and external electrodes. The body includes an active portion, in which the plurality of internal electrodes are disposed to form capacitance, corresponding to a region between internal electrodes disposed on an outermost side in the first direction, among the plurality of internal electrodes, a cover portion covering the active portion in the first direction, and a side margin portion covering the active portion in a second direction, perpendicular to the first direction, and 1.49<A1/A2<2.50 where A1 is an average grain size of the dielectric layer in a central region of the active portion, and A2 is an average grain size of the dielectric layer in an active-cover boundary portion, adjacent to the cover portion, of the active portion.

Abstract: A dielectric ceramic composition comprising a main component comprising an oxide represented by: UaXbYcZd((Ca1-x-ySrxMy)m(Zr1-u-vTiuHfv)O3)1-a-b-c-d wherein the elements defined by U, X, Y, Z and M and subscripts a, b, c, d, x, y, m, u and v are defined.

Abstract: Provided is an improved multilayered ceramic capacitor and an electronic device comprising the multilayered ceramic capacitor. The multilayer ceramic capacitor comprises first conductive plates electrically connected to first external terminations and second conductive plates electrically connected to second external terminations. The first conductive plates and second conductive plates form a capacitive couple. A ceramic portion is between the first conductive plates and said second conductive plates wherein the ceramic portion comprises paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC VPP wherein the rated AC VPP is higher than the rated DC voltage.

Abstract: There are provided a multilayer ceramic electronic component to be embedded in a board and a manufacturing method thereof, and particularly, a multilayer ceramic electronic component to be embedded in a board, in which a thickness of a ceramic body in an entire chip is increased by not allowing for an increase in a thickness of an external electrode while forming a band surface of the external electrode to have a predetermined length or greater for connecting the external electrode to an external wiring through a via hole, such that chip strength may be improved and the occurrence of damage such as breakage, or the like may be prevented, and a manufacturing method thereof, may be provided.