Abstract: A dielectric ceramic composition includes BaTiO3 as a main component; as subcomponents, with respect to 100 moles of BaTiO3, 0.9 to 2.0 moles of an oxide of RA in terms of RA2O3, where RA is at least one selected from Dy, Gd and Tb; 0.3 to 2.0 moles of an oxide of RB in terms of RB2O3, where RB is at least one selected from Ho and Y; 0.75 to 2.5 moles of an oxide of Yb in terms of Yb2O3; and 0.5 to 2.0 moles of an oxide of Mg in terms of Mg. when contents of oxide of RA, oxide of RB and oxide of Yb with respect to 100 moles of BaTiO3 are defined as “?”, “?” and “?”, respectively, “?”, “?” and “?” satisfy relations of 0.66?(?/?)?3.0 and 0.85?(?+?)/??2.4. According to the present invention, a dielectric ceramic composition having good properties can be provided.

Abstract: A laminated ceramic capacitor is provided which is excellent in reliability even when its dielectric ceramic layers thinned. For a dielectric ceramic in a laminated ceramic capacitor, a ceramic is used which includes a main component containing a barium titanate based composite oxide represented by the general formula: (Ba1-h-m-xCahSrmRex)k(Ti1-n-yZrnMy)O3, where Re is La or the like, M is Mg or the like, and the respective relationships of 0.05?x?0.50, 0.02?y?0.3, 0.85?k?1.05, 0?h?0.25, 0?m?0.50, and 0?n?0.40 are satisfied; and an accessory component as a sintering aid, wherein the average grain diameter of crystal grains in a sintered body is 0.6 ?m or less.

Abstract: It is harder to realize structural defects when the thickness of an internal electrode is reduced in a laminated ceramic electronic component, such as a laminated ceramic capacitor, when the internal electrodes contain a base metal as their conductive constituent, and the dielectric ceramic layers are formed from a dielectric barium titanate ceramic, and as an accessory constituent, at least one alkali metal element selected from Li, K, and Na, each of the internal electrodes has a thickness of 0.5 ?m or less, and the content of the alkali metal element in the dielectric ceramic is 0.2 parts by mol or more with respect to 100 parts by mol of the main constituent.

Abstract: A multilayer capacitor operable to allow adjustment of its equivalent series resistance substantially independent of its equivalent series inductance is disclosed. The multilayer capacitor can be used in decoupling circuits such as power supply decoupling circuits. The equivalent series resistance of the multilayer capacitor can be increased while suppressing an increase in the equivalent series inductance resulting in improved noise grounding.

Abstract: There are provided a conductive paste composition for an internal electrode and a multilayer ceramic electronic component including the same. The conductive paste composition includes: 100 moles of a metal powder; 0.5 to 4.0 moles of a ceramic powder; and 0.03 to 0.1 mole of a silica (SiO2) powder. The conductive paste composition can raise the sintering shrinkage temperature of the internal electrodes and improve the connectivity of the internal electrodes, and can improve the degree of densification of the dielectric layer, thereby improving withstand voltage characteristics, reliability, and dielectric characteristics.

Abstract: There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 ?m or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 ?m or less.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

Abstract: There is provided a multilayered ceramic electronic component capable of securing capacitance by controlling electrode connectivity. The multilayered ceramic electronic component includes: a ceramic main body; and internal electrodes formed in the interior of the ceramic main body and having a central portion and a tapered portion becoming thinner from the central portion toward edges thereof, respectively, wherein the ratio of the area of the tapered portion to the overall area of the internal electrodes is 35% or less. A desired capacitance can be obtained by controlling an electrode connectivity even in the small high capacitance multilayered ceramic capacitor.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

Abstract: A laminated ceramic electronic component having excellent mechanical characteristics and internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, and low defective rate includes a laminate having a plurality of laminated ceramic layers and a plurality of Al/Cu alloy-containing internal electrodes at specific interfaces between ceramic layers; where the Al/Cu ratio of the Al/Cu alloy is 80/20 or more.

Abstract: Provided is a laminated ceramic electronic component having excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes: a laminate which has a plurality of laminated ceramic layers and internal electrodes at a plurality of specific interfaces between the ceramic layers and having an Al/Ni alloy as a component; and an external electrode formed on the outer surface of the laminate, wherein the Al/Ni ratio of the Al/Ni alloy is 85/15 or more.

Abstract: Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes a laminate which has a plurality of laminated ceramic layers and internal electrodes formed along at a plurality of specific interface between the ceramic layers and having an Al/Ti alloy as a component; and an external electrode formed on the outer surface of the laminate. The Al/Ti ratio of the Al/Ti alloy is 91/9 or more.

Abstract: Disclosed herein are a stacked chip device including: a stacked body in which a plurality of sheets having an internal electrode made of a conductive material are stacked; external electrodes provided at both sides of the stacked body; and connection electrodes extending from the internal electrode and electrically connecting the internal electrode with the external electrodes, wherein the connection electrodes include: a plating solution permeation preventing section extending from the internal electrode, however, extending with a thickness smaller than the thickness of the internal electrode; and a contact reinforcement section extending from the plating solution permeation preventing section, however, extending in the form in which the thickness thereof is gradually extended toward the external electrode, and a manufacturing method thereof.

Abstract: A laminated ceramic electronic component includes curved surface portions provided in an outer surface of a ceramic element assembly, and internal conductors provided within the ceramic element assembly that are exposed in the curved surface portions and principal surfaces to define starting points for plating deposition. A base layer, in an external conductor, which is defined by a plating film is arranged so as to directly cover the exposed portions of the internal conductors.

Abstract: A dielectric ceramic composition includes, as a main component, a compound having perovskite type crystal structure shown by a general formula ABO3, as subcomponents, in terms of respective element with respect to 100 moles of the compound, and 0.6 to 2.0 moles of an oxide of Mg, 0.010 to 0.6 mole of oxide of Mn and/or Cr, 0.010 to 0.2 mole of an oxide of at least one selected from V, Mo and W, 0.10 to 1.0 mole of an oxide of R1 (R1 is at least one selected from Y, Yb, Er and Ho), 0.10 to 1.0 mole of an oxide of R2 (R2 is at least one selected from Dy, Gd and Tb) and 0.2 to 1.5 moles of a component consisting of an oxide of Ba and/or oxide of Ca and an oxide of Si. According to the present invention, even when a dielectric layer is made thinner, a dielectric ceramic composition having good characteristics can be provided.

Abstract: A multilayer ceramic capacitor and a method of manufacturing the same are provided. The multilayer ceramic capacitor includes a capacitive part, a passivation layer, and first and second outer electrodes. In the capacitive part, a plurality of dielectric layers and a plurality of first and second inner electrodes are alternately laminated, and ends of the first and second inner electrodes are alternately and respectively exposed in a direction of lamination of the dielectric layers. The passivation layer is provided at either or both of the top and bottom surfaces of the capacitive part. The first and second outer electrodes are electrically connected to the first and second inner electrodes exposed in a direction of lamination of the dielectric layers. One or more inner electrodes disposed at both ends in a direction of lamination among the plurality of inner electrodes include oxide represented by Ni—Mg—O.

Abstract: A multi-layered ceramic capacitor with at least one chip and with first base metal plates in a parallel spaced apart relationship and second base metal plates in a parallel spaced apart relationship wherein the first plates and second plates are interleaved. A dielectric is between the first base metal plates and said second base metal plates and the dielectric has a first coefficient of thermal expansion. A first termination is in electrical contact with the first plates and a second termination is in electrical contact with the second plates. Lead frames are attached to, and in electrical contact with, the terminations wherein the lead frames have a second coefficient of thermal expansion and the second coefficient of thermal expansion is higher than said first coefficient of thermal expansion. The lead frame is a non-ferrous material.

Abstract: There is provided a multilayer ceramic electronic component including: a lamination main body including a dielectric layer; and a plurality of inner electrode layers formed within the lamination main body and having ends exposed from one or more faces of the laminated main body, wherein when a distance between central portions of adjacent inner electrodes among the plurality of inner electrodes is T1 and a distance between non-exposed edges of the adjacent inner electrodes is T2, the ratio (T2/T1) of T2 to T1 is 0.80 to 0.95.

Abstract: There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

Abstract: A plurality of ceramic green sheets having printed strip inner electrodes patterns, each including a thick portion at a width-direction center and thin portions at respective width-direction sides of the thick portion, are laminated so that the thin portions overlap and the thick portions do not overlap to form an unfired mother laminated body. This unfired mother laminated body is cut along predetermined cut lines that are vertical to each other to obtain a plurality of unfired ceramic element assemblies. By applying ceramic paste to cover exposed portions of inner electrode patterns exposed to lateral surfaces, side gap areas are formed between a first inner electrode pattern and first and second lateral surfaces of the unfired ceramic element assembly and between a second inner electrode pattern and the first and second lateral surfaces.

Abstract: A multilayer capacitor which can prevent chattering noises from occurring and improve the packaging density and packaging yield, and a method of manufacturing a multilayer capacitor are provided. Even when an electrostrictive vibration is generated in this multilayer capacitor upon voltage application, a joint surface of a metal terminal can flex, so as to mitigate the electrostrictive vibration, thereby preventing chattering noises from occurring. The joint surface is formed with a cutout and thus can fully secure its flexibility. In this multilayer capacitor, a step formed by a terminal connecting surface, a substrate connecting surface, and the joint surface is positioned within an area overlapping a capacitor element body as seen in the laminating direction of dielectric layers. Therefore, solder fillets do not protrude out of the capacitor element body, whereby the packaging density on a mounting substrate K can be improved.

Abstract: A multilayer chip capacitor includes a capacitor body including a first capacitor part and a second capacitor part, first and second external electrodes respectively formed on first and second longer side faces of the capacitor body, and third and fourth external electrodes respectively formed on first and second shorter side faces of the capacitor body. The first capacitor part includes first and second internal electrodes of opposite polarity, and the second capacitor part includes third and fourth internal electrodes of opposite polarity. The first to fourth internal electrodes each have one lead. The first to fourth external electrodes are respectively connected to the leads of the first to fourth internal electrodes. A series resonance frequency of the first capacitor part is different from that of the second capacitor part. Equivalent series resistance (ESR1) of the first capacitor part and the equivalent series resistance (ESR2) of the second capacitor part satisfy ERS1?20 m? and 0.7(ESR1)?ESR2?1.

Abstract: A multilayer capacitor includes a dielectric body formed by a plurality of dielectric layers, a first conductor layer, a second conductor layer, a first terminal electrode, and a second terminal electrode formed on a first side face of side faces of the dielectric body in parallel to a stacking direction Z. The first and second conductor layers respectively include first and second lead portions connected to the first and second terminal electrodes. A relation (a+c)/(b×n)?0.035 is formed between a length “a” between the first and second lead portions in a vertical direction to the stacking direction Z, a length “b” between conductor layers positioned at both ends of the dielectric body in the stacking direction, a space length “c” between the first side face and the first conductor layer, a total number “n” of the conductor layers.

Abstract: A multi-terminal monolithic ceramic capacitor arranged to reduce an equivalent series inductance and having an array structure is provided. A first same-polarity-connection conductor and a second same-polarity-connection conductor are provided inside a capacitor body so as to extend over at least two capacitors. The first same-polarity-connection conductor is electrically connected to a plurality of first external terminal electrodes, and the second same-polarity-connection conductor is connected to a plurality of second external terminal electrodes. In the monolithic ceramic capacitor which is mounted on a wiring substrate, the overall capacitance can be maintained even if an accident, such as cracking of a solder joint, occurs in one of the external terminal electrodes.

Abstract: A first inner electrode has a first main electrode, a first lead conductor, a first coupling conductor, and a second lead conductor. A second inner electrode has a second main electrode, a third lead conductor, and a second coupling conductor. A third inner electrode has a third main electrode, and a fourth lead conductor. The third inner electrode is connected to only a first connection conductor. In the extending direction of the first and third lead conductors, the first and second coupling conductors have a length shorter than the lengths of the first and third lead conductors and of the first and second main electrodes, respectively. The second inner electrode is adjacent to at least one of the first and third inner electrodes so as to sandwich the insulating layer.

Abstract: A multilayer ceramic electronic component includes external terminal electrodes that are formed by direct plating on the first and second side surfaces of a ceramic body including stacked ceramic layers and inner conductors. The external terminal electrodes include base plating films formed so as to cover the exposed portions of inner conductors. Voids are provided that are open to the side surfaces of the ceramic body so as to be adjacent to the ends in the width direction of the exposed portions of the inner conductors. A plating metal defining the base plating films enters the voids and is electrically connected to the inner conductors in the ceramic body.

Abstract: A method of manufacturing a capacitor-embedded printed circuit board that includes fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

Abstract: Disclosed is a dielectric ceramic having crystal grains mainly composed of barium titanate and an intergranular phase formed among the crystal grains. The dielectric ceramic contains certain amounts of manganese and at least one rare earth element (RE) selected from magnesium, gadolinium, terbium, dysprosium, holmium and erbium, in terms of oxides, per 1 mole of barium constituting the barium titanate. The dielectric ceramic also contains a certain amount of yttrium in terms of oxides, per 100 parts by mass of the barium titanate. The crystal grains have an average grain size of 0.05-0.2 ?m. By using the dielectric ceramic as a dielectric layer, there can be obtained a capacitor having high capacity and stable capacitance temperature characteristics.

Abstract: There are provided a ceramic sheet product for a ceramic electronic component, a multilayer ceramic electronic component using the same, and a method of manufacturing the multilayer ceramic electronic component. The ceramic sheet product for a ceramic electronic component includes a ceramic layer; a metal layer formed on the ceramic layer; and metal nanostructures contacting the metal layer and protruding from the metal layer to an inner portion of the ceramic layer. With the multilayer ceramic electronic component using the ceramic sheet product for a ceramic electronic component, an interval between electrodes is reduced to thereby allow for the increase of capacitance, whereby a multilayer ceramic electronic component having high capacitance may be provided.

Abstract: The laminated ceramic capacitor has a laminate block made of alternately laminated ceramic dielectric layers and internal electrodes, a pair of cover layers, laminated on top and bottom of the laminate block, ceramic bodies formed on both side faces of the laminate block, and a pair of external electrodes that are electrically connected to the internal electrodes, wherein the average grain size of the ceramic dielectric grains constituting the ceramic body is smaller than the average grain size of the ceramic dielectric grains constituting the ceramic dielectric layer in the laminate block.

Abstract: A multilayer ceramic electronic component that is small, that has high electrical strength, and that is resistant to separation between ceramic layers includes a ceramic sintered body having a substantially rectangular parallelepiped shape and a plurality of first and second internal electrodes. The plurality of first and second internal electrodes are alternately arranged so as to face each other. The first and second internal electrodes are parallel or substantially parallel to first and second major surfaces. The first and second internal electrodes are exposed to at least one of the fifth and sixth surfaces and are not exposed to the third or fourth surface. No bends exist in any of the ends of each of the first and second internal electrodes adjacent to the third and fourth surfaces.

Abstract: An electronic component includes a ceramic sintered body, and a plurality of first and second inner electrodes alternately arranged inside the ceramic sintered body to be opposed to each other in a third direction with a ceramic layer interposed between the adjacent first and second inner electrodes. The first and second inner electrodes are each arranged to be exposed to a third or fourth surface without being exposed to fifth and sixth surfaces. Heterogeneous regions, which include solid solutions of metals included in the first and second inner electrodes and the ceramic sintered body, are arranged continuously in opposite end portions of the ceramic sintered body in a first direction to extend from one side end to an opposite side end of a region where the first and second inner electrodes are disposed in a third direction.

Abstract: [Problem to be Solved] To provide a helical capacitor for controlling a high-frequency power which flows in power lines, and a manufacturing method of the helical capacitor. [Solution] A helical capacitor is constituted by helically spiraling a belt shape capacitor line 1001 which includes an internal metal body to be a helically spiraled belt-shape internal electrical conductor, a dielectric film covering the internal electrical conductor, and an electrically conductive layer covering the dielectric film. The capacitor line of belt shape 1001 can be wrapped around the internal support body 1200. Internal metal body lead terminals 1311, 1321 are respectively formed at both ends of the internal metal body, and electrically conductive layer lead terminals 1312, 1322 can be respectively formed at both ends of the electrically conductive layer.

Abstract: The present invention relates to a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a ceramic body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side; a plurality of inner electrodes formed within the ceramic body and having respective one ends exposed to the third side and the fourth side; and outer electrodes formed on the third side and the fourth side and electrically connected to the inner electrodes. A shortest distance from distal edges of an outermost inner electrode among the plurality of inner electrodes to the first side or the second side is smaller than a shortest distance from distal edges of a central inner electrode to the first side or the second side.

Abstract: There are disclosed a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes: a ceramic body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side, a plurality of inner electrodes formed within the ceramic body, and outer electrodes formed on the third side and the fourth side and electrically connected to the inner electrodes. A distance from distal edges of the inner electrodes to the first side or the second side of the ceramic body is 30 ?m or less.

Abstract: There is disclosed a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a multilayer body having a first side and a second side opposite to each other and having a third side and a fourth side connecting the first side to the second side, a plurality of inner electrodes formed in the multilayer body and having distal edges exposed to the first side or the second side, first and second side members formed on the first and second sides to cover the distal edges of the plurality of inner elecrodes, and outer electrodes formed on the third side and the fourth side to be electrically connected to the inner electrodes. An angle between a virtual line connecting the distal edges of the plurality of inner electrodes and the first side member or the second side member is less than 90° (?/2).

Abstract: There are provide a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a multilayer body having a first side and a second side opposed to each other and having a third side and a fourth side connecting the first side to the second side, inner electrodes formed in the multilayer body and formed to be spaced apart from the third side or the fourth side by a predetermined distance, groove portions formed on at least one of top and bottom surfaces of the multilayer body and formed parallel to the third or fourth side by a predetermined distance from the third side or the fourth side, and outer electrodes extended from the third side and the fourth side to the top surface or the bottom surface of the multilayer body to cover the groove portions.

Abstract: A multilayer ceramic capacitor includes: a ceramic element; a plurality of first and second inner electrodes formed at the interior of the ceramic element and including capacity contribution portions facing each other and capacity non-contribution portions extending from the capacity contribution portions and having one end alternately exposed from the side of the ceramic element; first and second outer electrodes formed at the side of the ceramic main body and electrically connected with the first and second inner electrodes, wherein the thickness of the capacity non-contribution portion is greater than that of the capacity contribution portion and connectivity of the capacity non-contribution portion is higher than that of the capacity contribution portion at one or more of the first and second inner electrodes.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic main body having first and second side faces opposed to each other and third and fourth side faces connecting the first and second side faces; a plurality of inner electrodes formed within the ceramic main body and having respective one ends thereof exposed to the third and fourth side faces; external electrodes formed on the third and fourth side faces and electrically connected to the inner electrodes; and dielectric layers alternately stacked with the inner electrodes and made of ceramic powder, wherein a grain size of the ceramic powder is 130 ?m or smaller. Acoustic noise generated from the multilayer ceramic capacitor can be reduced by adjusting the grain size of the ceramic powder, a chip permittivity, and the thickness of the dielectric layer, and thus, noise of an electronic product employing the multilayer ceramic capacitor can be reduced.

Abstract: In a ceramic electronic component having a thin structure, the occurrence of cracks due to stress applied when the ceramic component is being mounted or in a mounted state are prevented. Each of first and second external terminal electrodes has a substantially rectangular region on a principal surface of a ceramic element body, the principal surface being directed to the mounting surface side. An end of the first external terminal electrode, which is arranged in contact with a gap region, and an end of the second external terminal electrode, which is positioned in contact with the gap region, each preferably have a concave-convex shape on the principal surface.

Abstract: There is provided a multilayer ceramic capacitor including: a capacitor main body formed by stacking a dielectric layer having a thickness of td and alternately stacking more than one opposing pair of a first internal electrode having a thickness of te and a second internal electrode having the same thickness as the first internal electrode, and having the dielectric layer therebetween; and a protective layer formed by stacking a second dielectric layer on at least one of an upper surface and a lower surface of the capacitor main body so that a dielectric material layer has a thickness of tc, wherein when a thickness from an end of a region where the first internal electrode and the second internal electrode oppose each other to side and end surfaces of the capacitor main body is a, it satisfies the following Equation 1 and a method of fabricating a multilayer ceramic capacitor are provided.

Abstract: There are provided a ceramic electronic component and a method for producing the ceramic electronic component, where a ground electrode layer can be directly coated with lead-free solder without lowering reliabilities. Terminal electrode 3 is provided with a ground electrode layer 21 of Cu having been formed by firing, a solder layer 22 formed of a lead-free solder based on five elements of Sn—Ag—Cu—Ni—Ge, and a diffusion layer 23 having been formed by the diffusion of Ni between the ground electrode layer 21 and the solder layer 22. Because the diffusion layer 23 of Ni is formed between the ground electrode layer 21 and the solder layer 22, the diffusion layer 23, which functions as a barrier layer, suppresses the solder leach of Cu from the ground electrode layer 21. The diffusion layer 23 of Ni can also suppress the growth of fragile intermetallic compounds of Sn—Cu. Therefore, a decrease in the bonding strength between the ground electrode layer 21 and the solder layer 22 can be prevented.

Abstract: In a laminated ceramic electronic component in which, by directly carrying out a plating process on an outer surface of a component main body, an external electrode is formed thereon, an attempt is made to improve the adhesion strength between a plated film forming the external electrode and the component main body. A brazing material containing Ti is applied to at least one portion of a surface on which external electrodes of a component main body is formed, and by baking this brazing material, a metal layer containing Ti is formed. Moreover, the external electrodes are formed by a plating process so as to coat at least the metal layer, and a heating process is then carried out so as to cause counter diffusion between the metal layer and the plated film that is to form the external electrodes.

Abstract: A dielectric ceramic for use in dielectric ceramic layers has a main component represented by a composition formula of (Sr1-x-ySnxBay)TiO3, wherein x is 0.005?x?0.24, y is 0?y?0.25 in the composition formula. Preferably, the dielectric ceramic includes 0.01 mol to 5 mol of M (M is at least one of Mn and V) calculated as MO and/or 0.2 mol to 5 mol of Si calculated as SiO2, with respect to 100 mols of the main component, and more preferably, further includes 0.1 mol to 25 mol of Ca calculated as CaO with respect to 100 mols of the main component. The dielectric ceramic has an increased dielectric constant permitting size reduction when used in a laminated ceramic capacitor.

Abstract: A multilayer ceramic capacitor is provided. In the multilayer ceramic capacitor, a plurality of first and second inner electrodes are formed inside a ceramic sintered body. Ends of the first and second inner electrodes are alternately exposed to both ends of the ceramic sintered body. First and second outer electrodes are formed on both ends of the ceramic sintered body and connected to the first and second inner electrodes. The first and second outer electrodes include a first region having a porosity in the range of 1% to 10%, and a second region having a porosity less than that of the first region.

Abstract: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

Abstract: In a method of forming an external electrode by growing plated depositions on exposed ends of a plurality of internal electrodes in a component main body, the component main body is polished to increase exposure of the internal electrodes. To prevent decreased external electrode fixing strength, a radius of curvature is reduced to about 0.01 mm or less for an R chamfered section formed in a ridge section of the component main body during polishing by ion milling, and exposed ends of the internal electrodes are recessed from end surfaces of the component main body with a recess length of about 1 ?m or less. Plating films to serve as external electrodes are formed to extend from the end surfaces of the component main body across the R chamfered section, and include end edges located on at least one of the principal surfaces and the side surfaces.

Abstract: A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.

Abstract: A multilayer capacitor array 1 comprises a capacitor element body 2 having first, second, third, and fourth inner electrodes 13 to 16, and first to fourth terminal electrodes 3 to 6 disposed on the outer surface of the capacitor element body 2 and respectively connected to the inner electrodes 13 to 16. The first and second inner electrodes 13, 14 form a first capacitor section C1, while the third and fourth inner electrodes 15, 16 form a second capacitor section C2. The multilayer capacitor array 1 is mounted to a circuit board such that the first and third terminal electrodes 3, 5 are connected to first leads 22, 23, while the second and fourth terminal electrodes 4, 6 are connected to a second lead 24.

Abstract: A method for manufacturing a ceramic electronic component includes the steps of preparing a ceramic body including a plurality of first internal electrodes and a plurality of second internal electrodes, processing the ceramic body to an internal electrode exposure rate of about 102% to about 153%, and plating the processed ceramic body to form a plated layer thereon.