Having Particular Material Patents (Class 361/771)
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Patent number: 7019403Abstract: A self supported underfill film adhesively bonds surface mount integrated circuit packages to a printed circuit board. The printed circuit board has conductive traces and exposed conductive pads on the surface. Solder paste is printed on the conductive pads, and one or more additional solder paste deposits are printed in an area outside the conductive pads to serve as tack pads for a film adhesive. The film adhesive is strategically positioned on the printed circuit board over the tack pads and near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.Type: GrantFiled: August 29, 2003Date of Patent: March 28, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Katherine M. Devanie, Lane V. Brown, Michael L. Johnson
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Patent number: 6992397Abstract: A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability.Type: GrantFiled: February 9, 2004Date of Patent: January 31, 2006Assignee: Altera CorporationInventor: My Nguyen
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Patent number: 6992376Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.Type: GrantFiled: July 17, 2003Date of Patent: January 31, 2006Assignee: Intel CorporationInventor: Edward W. Jaeck
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Patent number: 6900529Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.Type: GrantFiled: May 6, 2002Date of Patent: May 31, 2005Assignee: Legacy Electronics, Inc.Inventors: Kenneth J. Kledzik, Jason C. Engle
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Patent number: 6882545Abstract: A noncontact ID card composed by laminating an antenna circuit board where an antenna is formed and an interposer board formed by connecting an enlarged electrode to an electrode of a mounted IC chip and bonding between an antenna electrode of the antenna circuit board and the enlarged electrode of the interposer board with electroconductive adhesive material, wherein a substrate of the antenna circuit board and a substrate of the interposer board are bonded. In addition, in another composition, at least one local deformation is applied to a boding face of the electrodes each other in a direction crossing the bonding face.Type: GrantFiled: March 13, 2003Date of Patent: April 19, 2005Assignee: Toray Engineering Company, LimitedInventors: Masanori Akita, Yoshiki Sawaki
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Patent number: 6879492Abstract: A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N ?2) and N metal planes formed in the following sequence: dielectric layer 1 on a metallic plane that exists on a surface of the substrate, metal plane 1 on dielectric layer 1, dielectric layer 2 on dielectric layer 1 and metal plane 1, metal plane 2 on the dielectric layer 2, . . . , dielectric layer N on dielectric layer N-1 and metal plane N-1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.Type: GrantFiled: March 28, 2001Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventors: David J. Alcoe, Kim J. Blackwell
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Patent number: 6829149Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.Type: GrantFiled: August 18, 1997Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Chi Shih Chang, William T. Chen, Ajit Trivedi
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Patent number: 6809407Abstract: A semiconductor device includes an electrically insulating board; conductive interconnections formed on a first face of the board and on a second face opposite to the first face; a semiconductor chip fixed to the board through at least the interconnections on the first face, said semiconductor chip having a semiconductor element electrically connected to the interconnections; a conductive bump formed on the second face of the board and electrically connected to the interconnections on the second face; and a first through-hole passing through the board to ventilate at least a part of the region between the board and the semiconductor chip.Type: GrantFiled: October 31, 2002Date of Patent: October 26, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Shinya Shimizu
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Publication number: 20040179343Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and pads on a second side; (b) a rigid substrate having vias aligned with the pads on the second side of the flexible substrate; (c) an adhesive layer comprised of a compliant adhesive material having vias aligned with the pads on the second side of the flexible substrate; the adhesive layer being affixed to the flexible substrate and the rigid substrate; (d) a card; (e) electrical connectors that are retained in the vias of the rigid substrate and the adhesive layer, which electrical connectors have first and second retractable ends, wherein the first retractable ends contact pads on the substrate, and the second retractable ends contact pads on the card; and (f) a clamp that is adapted to fit over the substrate and the adhesive layer, the clamp having an opening to provide access to the contactors, wherein the clamp is connected to the card.Type: ApplicationFiled: April 16, 2003Publication date: September 16, 2004Applicant: Nexcleon, Inc.Inventors: Konstantine N. Karavakis, Tom T. Nguyen
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Patent number: 6791035Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces. In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.Type: GrantFiled: February 21, 2002Date of Patent: September 14, 2004Assignee: Intel CorporationInventors: Thomas E. Pearson, George L. Arrigotti, Raiyomand F. Aspandiar, Christopher D. Combs
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Patent number: 6785144Abstract: A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.Type: GrantFiled: August 24, 2000Date of Patent: August 31, 2004Assignee: Micron Technology, Inc.Inventor: Salman Akram
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Patent number: 6740823Abstract: A solder bonding method comprises the step of solder bonding a first electrode 30 to a second electrode 16 having a solder bump 18 of mainly Sn formed on the upper surface thereof. The first electrode 30 and/or the second electrode 16 includes metal layers 14, 26 formed of an alloy layer containing Ni and P, an alloy layer containing Ni and B, or an alloy layer containing N, W and P. The metal layer of the alloy layer containing impurities, such as P, etc. can prevent the Ni of the metal layer from combining with the Sn in the solder bump. Accordingly, good bonded states can be obtained.Type: GrantFiled: August 13, 2002Date of Patent: May 25, 2004Assignee: Fujitsu LimitedInventor: Kozo Shimizu
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Patent number: 6734540Abstract: A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 26 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A stress inhibiting intermediate mounting substrate is connected to the chip carrier through a first array of solder connections. The stress inhibiting intermediate mounting substrate has a second coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the chip carrier and smaller than or equal to the coefficient of thermal expansion of the printed circuit board. Alternate preferred inventive embodiments allow for the cleaning and removal of residual flux and other debris in packaging.Type: GrantFiled: October 10, 2001Date of Patent: May 11, 2004Assignee: Altera CorporationInventor: Donald S. Fritz
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Publication number: 20040057221Abstract: The present invention relates to a method and apparatus that prevents/minimizes cracking in the ceramic body of processors. The ability to prevent/minimize cracking can ensure successful operation and substantially increase processor lifetime. The present invention discloses a device for maintaining a microprocessor in a desired relationship with a printed wiring board while limiting the transmission of shock and vibrational motion to and from the processor includes a printed wiring board, a processor, and a dynamic isolating mount compressed between the printed wiring board and the processor, wherein the processor maintains the dynamic isolating mount in a compressed state such that the dynamic isolating mount bears on the printed wiring board.Type: ApplicationFiled: September 26, 2003Publication date: March 25, 2004Inventors: Daniel L. Callahan, Raymond J. Iannuzzelli
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Publication number: 20040012936Abstract: The invention provides a device and method for enclosure of electronic circuits. An encapsulated electronic circuit device has a circuit board further comprising, electronic conductive paths, at least one electronic component, and an energy source, and an enclosure encapsulating the circuit board, substantially covering the front and back-side of the circuit board. The enclosure is composed of a polyurethane material. The circuit device preferably has a design imprinted on the front of the circuit board. The printing process is optionally a silk screening method.Type: ApplicationFiled: July 18, 2002Publication date: January 22, 2004Inventor: Pascal A. Gravelin
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Patent number: 6675474Abstract: An electronic component mounted member includes a circuit board, an electronic component connected to the circuit board and an electrically conductive adhesive interposed between the electronic component and the circuit board. In a joining interface of the electrically conductive adhesive and an electrode of the circuit board, an intermediate layer that is formed of a thermoplastic insulating adhesive with a softening temperature of 100° C. to 300° C. is interposed between the electrically conductive adhesive and the electrode. An electrically conductive filler contained in the electrically conductive adhesive is present partially in the intermediate layer, thus allowing an electrical conduction between the electrically conductive adhesive and the electrode of the circuit board.Type: GrantFiled: December 3, 2002Date of Patent: January 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tsutomu Mitani, Hiroaki Takezawa, Yukihiro Ishimaru, Takashi Kitae, Yasuhiro Suzuki
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Patent number: 6674016Abstract: An electronic component is described, which contains a printed circuit board having electrodes for connection and a semiconductor chip having electrodes for connection which is mounted on said circuit board with their electrodes facing those of the circuit board, the gap between the circuit board and the semiconductor chip being filled with a sealing resin layer, wherein the sealing resin layer is formed of a liquid epoxy resin composition containing (A) a liquid epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) an N,N,N′,N′-tetrasubstituted fluorine-containing aromatic diamine derivative.Type: GrantFiled: September 19, 2002Date of Patent: January 6, 2004Assignees: Nitto Denko Corporation, NEC CorporationInventors: Masahiro Kubo, Ichiro Hazeyama, Sakae Kitajo, Koji Matsui, Kazumasa Igarashi
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Patent number: 6664480Abstract: A circuit board substrate assembly includes a generally planar circuit board substrate material having a longitudinal axis extending along a length of the substrate material between a first end and a second end thereof. The circuit board substrate material further has a first edge and a second edge extending along the length of the circuit board substrate material between the first end and the second end. A plurality of openings are defined in the substrate material. Each opening extends between a first distance from the first edge of the circuit board substrate and a second distance from the second edge of the circuit board substrate. Further, each opening separates adjacent circuit forming regions lying along the longitudinal axis and has first and second opposing end portions.Type: GrantFiled: May 25, 2001Date of Patent: December 16, 2003Assignee: Micron Technology, Inc.Inventors: Zane Drussel, Derek Hinkle
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Patent number: 6660942Abstract: A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elasticity underlayer made of a material having a lower modulus of elasticity than that of a base material of the wiring substrate is disposed between the base material of the wiring substrate and each of the electronic-part mounting pad and the rerouted wiring. A method of manufacturing the wiring substrate and a semiconductor device using the wiring substrate are also disclosed.Type: GrantFiled: April 5, 2001Date of Patent: December 9, 2003Assignee: Shinko Electric Industries Co., Ltd.Inventors: Michio Horiuchi, Takashi Kurihara
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Patent number: 6633489Abstract: The present invention relates to a method and apparatus that prevents/minimizes cracking in the ceramic body of processors. The ability to prevent/minimize cracking can ensure successful operation and substantially increase processor lifetime. The present invention discloses a device for maintaining a microprocessor in a desired relationship with a printed wiring board while limiting the transmission of shock and vibrational motion to and from the processor includes a printed wiring board, a processor, and a dynamic isolating mount compressed between the printed wiring board and the processor, wherein the processor maintains the dynamic isolating mount in a compressed state such that the dynamic isolating mount bears on the printed wiring board.Type: GrantFiled: July 31, 2001Date of Patent: October 14, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Daniel L. Callahan, Raymond J. Iannuzzelli
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Patent number: 6617528Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.Type: GrantFiled: January 17, 2001Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: Gregg J. Armezzani, Matthew A. Heller
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Patent number: 6617681Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.Type: GrantFiled: June 28, 1999Date of Patent: September 9, 2003Assignee: Intel CorporationInventor: Mark T. Bohr
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Publication number: 20030141104Abstract: The aim of the invention is to improve the modular assembly technique used for assembling electronic printed-circuit boards (FBG1, FBG2) for electronic devices in order to incorporate the printed-circuit boards in electronic devices with electronic printed-circuit boards of the type mentioned above more flexibly in terms of the printed-circuit board material, in accordance with the respective field of application, size and weight requirements and manufacturing costs of the devices. To this end, the electronic devices are modularly assembled in terms of the printed-circuit board construction, with at least two printed-circuit boards (FBG1, FBG2) consisting of different materials with different temperature and length-related expansion coefficients.Type: ApplicationFiled: December 3, 2002Publication date: July 31, 2003Inventors: Heinrich Bruckmann, Georg Busch, Ludger Hinken
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Patent number: 6576848Abstract: A wiring structure with crossover capability is disclosed. The wiring utilizes a connection stud in a contact layer, beneath the plane of the otherwise-intersecting lines as a crossover. Thus, a first wire in a first metallization layer passes below a second wire in a second metallization layer by overlapping contact with the connection stud in the contact layer. In manufacturing the wiring structure of the present invention, no intervening insulative or via layers are used between the contact layer, the first metallization layer and the second metallization layer. However, care must be taken in device layout on the substrate to ensure that the connection stud is located above isolation areas rather than active device areas.Type: GrantFiled: November 22, 1996Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventors: John Edward Cronin, John Andrew Hiltebeitel, Carter Welling Kaanta, James Gardner Ryan
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Publication number: 20030081393Abstract: A resin-formed substrate is provided which has a component side for mounting an electronic component thereon, and a solder side for soldering thereto a lead extending from the electronic component, which is the reverse to the component side, the resin-formed substrate comprising a metal frame forming an electronic circuit pattern; and a resin covering the metal frame, the resin having an aperture formed therein, for exposing a portion of the metal frame, wherein the portion of the metal frame exposed through the aperture serves as an electrode portion for mounting of the electronic component, wherein the resin has a rib integrally formed on the component side, thereby suppressing warp of the resin-formed substrate due to a temperature difference made between a component side and a solder side during soldering.Type: ApplicationFiled: October 16, 2002Publication date: May 1, 2003Applicant: Canon Kabushiki KaishaInventor: Yukio Yokoyama
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Patent number: 6535395Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.Type: GrantFiled: December 3, 2001Date of Patent: March 18, 2003Assignee: Intel CorporationInventors: Joe A. Harrison, Edward R. Stanford, Thomas G. Ruttan
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Patent number: 6529026Abstract: An interconnect for making temporary electrical connections with semiconductor components includes a substrate with patterns of elastomeric contacts adapted to electrically engage contact locations (e.g., bond pads, solder bumps) on the semiconductor components. The elastomeric contacts can be formed of conductive elastomer materials, such as anisotropic adhesives and silver filled silicone, having metal particles for penetrating the contact locations. The substrate also includes patterns of metal conductors having non-oxidizing contact pads, which provide low resistance bonding surfaces for the elastomeric contacts. A method for fabricating the interconnect includes the step of depositing bumps in a required size and shape using stenciling, screen printing, or other deposition process. Following deposition, the bumps can be cured and planarized to form the elastomeric contacts. During a test procedure, the elastomeric contacts can be loaded in compression to compliantly engage the contact locations.Type: GrantFiled: October 9, 2001Date of Patent: March 4, 2003Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Salman Akram
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Patent number: 6512183Abstract: An electronic component mounted member includes a circuit board, an electronic component connected to the circuit board and an electrically conductive adhesive interposed between the electronic component and the circuit board. In a joining interface of the electrically conductive adhesive and an electrode of the circuit board, an intermediate layer that is formed of a thermoplastic insulating adhesive with a softening temperature of 100° C. to 300° C. is interposed between the electrically conductive adhesive and the electrode. An electrically conductive filler contained in the electrically conductive adhesive is present partially in the intermediate layer, thus allowing an electrical conduction between the electrically conductive adhesive and the electrode of the circuit board.Type: GrantFiled: June 27, 2001Date of Patent: January 28, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tsutomu Mitani, Hiroaki Takezawa, Yukihiro Ishimaru, Takashi Kitae, Yasuhiro Suzuki
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Patent number: 6507497Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.Type: GrantFiled: May 4, 2001Date of Patent: January 14, 2003Assignee: Shinko Electric Industries, Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 6496382Abstract: A radio frequency identification tag is made with printed antenna coil integrated on a flexible substrate, and an integrated circuit area of the substrate adjacent the antenna coil for carrying circuit elements. The radio frequency identification tag is designed to be sufficiently robust to withstand the rigors of mail efficiency processing measurement applications.Type: GrantFiled: October 25, 2000Date of Patent: December 17, 2002Assignee: Kasten Chase Applied Research LimitedInventors: Donald Harold Ferguson, Mircea Paun
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Patent number: 6489572Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.Type: GrantFiled: January 23, 2001Date of Patent: December 3, 2002Assignee: Kingpak Technology Inc.Inventors: Mon Nan Ho, Chih-Hong Chen, Yen Cheng Huang, Li Huan Chen, Kuo Feng Peng, Jichen Wu, Allis Chen, Wen Chuan Chen
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Patent number: 6462283Abstract: A printed wired board is provided, in which an area for extracting lines for plating of the printed wired board is made small and at the same time the number of the extracting lines for plating within a packaging area is made small, resulting in an improvement of wiring efficiency. The circuit pattern formed on an insulating film has a window portion and is not formed toward the periphery of the insulating film, and a bonding pad is electroplated, where the bonding pads are to be connected with a center-pad of a semiconductor by a bonding wire through the window portion. Accordingly, even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.Type: GrantFiled: September 3, 1999Date of Patent: October 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Sumie Hirai, Jun Ohmori
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Patent number: 6455785Abstract: A bump connection is formed by stacking at least two metallic balls of different kinds of metals on a conductor of an electronic component such as a semiconductor device. The bump connection is obtained by forming the metallic balls using metallic wires. An apparatus for forming the connection includes a support, capillary member for having a wire pass therethrough, a pair of clamps for clamping the wire, and a “torch” (e.g., electrode, gas flame) which heats the tip of the wire, forming the ball. Successive balls can be formed by this apparatus atop the initially formed ball to provide a stacked configuration.Type: GrantFiled: October 5, 1999Date of Patent: September 24, 2002Assignee: International Business Machines CorporationInventors: Hiroyuki Sakurai, Keizo Sakurai
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Patent number: 6452112Abstract: The electronic circuit unit of the present invention is provided with the broad width lands and the thin width lands tied with the broad width lands, which are configured by a solder resist that is formed on the surface of the circuit board. Owing to this configuration, the solders placed on the thin width lands are drawn toward the broad width lands, which increases the quantity of the solder buildup on the broad width lands, and accompanied with this increase, swells the heights of the solder buildup on the broad width lands. Thus, the electronic circuit unit of the present invention ensures the soldering.Type: GrantFiled: October 18, 1999Date of Patent: September 17, 2002Assignee: Alps Electric Co., Ltd.Inventors: Kiminori Terashima, Hiroshi Harada
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Patent number: 6437251Abstract: This invention provides a specially-shaped, double-face flexible printed wiring board having a small pitch at a high production yield. Metal wirings 22 and 32 formed on a base film 21, 31 of two elemental pieces 20 and 30 of a flexible printed wiring board are arranged in such a manner as to face each other while sandwiching a bonding film 16 not containing conductive particles between them, and are heat-pressed to each other. The adhesive resin film 16 so softened is pushed aside from the metal wirings 22 and 32 and the low melting point metal coating films 23 and 33 formed on the surface of the metal wirings 22 and 32 come into direct contact with each other and are fused. In this instance, the softened adhesive resin film 16 is charged between the metal wirings 22 and 32. Therefore, the molten low melting point metal does not scatter. The base films 21 and 31 are bonded by the adhesive resin film 16.Type: GrantFiled: February 17, 2000Date of Patent: August 20, 2002Assignee: Sony Chemicals Corp.Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Yukio Anzai, Mitsuhiro Fukuda
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Patent number: 6434017Abstract: A semiconductor device in a chip size package form having a high durability and reliability and realizing a small size with high density, and an electronic apparatus mounting the same, connected to a motherboard by soldering, comprising a semiconductor chip wherein bumps are formed on pad portions thereof; an interposer supporting the bumps mechanically and having through-holes wherein conductors are formed and connected to the bumps electrically; and a sealing resin buried between the semiconductor chip and the interposer, wherein the interposer is formed from a material having a higher glass transition temperature than a curing temperature of the sealing resin, a coefficient of linear expansion of the interposer is of a value substantially intermediate between that of the motherboard and that of the semiconductor chip, and/or the interposer is formed from a material having a bending strength of 400 MPa or more.Type: GrantFiled: January 25, 1999Date of Patent: August 13, 2002Assignee: Sony CorporationInventor: Kaoru Iwabuchi
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Patent number: 6429382Abstract: For the reliability in insulation and against sulfurization, the mounting structure of the invention includes an electric structure, and an electrically conductive adhesive layer including an electrically conductive filler disposed on the electric structure, and at least a portion of surface of the electrically conductive filler is exposed to an external environment, and an elution preventive film is disposed on at least a portion of the exposed surface. Further, an electrically conductive adhesive of this invention includes the electrically conductive filler, and an elution preventive film is disposed on the entire surface of the electrically conductive filler.Type: GrantFiled: April 11, 2000Date of Patent: August 6, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuyoshi Amami, Hiroaki Takezawa, Tsukasa Shiraishi, Yoshihiro Bessho
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Patent number: 6420658Abstract: A module circuit board for a semiconductor device by a solder reflow process includes a plurality of pads on which the semiconductor device to be mounted, a plurality of terminals formed on a side edge of the board, a resist film covering an area between said pads and said terminal on the board, and a barrier formed between said pads and said terminals.Type: GrantFiled: November 30, 1999Date of Patent: July 16, 2002Assignee: Oki Electric Industry Co., Ltd.Inventor: Norio Takahashi
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Patent number: 6421249Abstract: An electronic device having an enhanced attachment to a surface mount lamp (106) includes a circuit board (100), at least two conductive pads (102), at least two adhesive pads (104), and the surface mount lamp (106). The conductive pads (102) and the adhesive pads (104) are integrally formed within the circuit board (100). Preferably, each section of the circuit board (100) allotted for one surface mount lamp (106) has two conductive pads (102) and two adhesive pads arranged in a grid-like pattern such that similar pads are in opposing corners of the grid. The surface mount lamp (106) has two electrical leads (108), each protruding from opposing corners of a base (110) of the surface mount lamp (106). These electrical leads (108) are soldered to the conductive pads (102) in the circuit board (100). The unobscured opposing corners (112) of the plastic base (110) are partially melted and adhered to the adhesive pads (104) in the circuit board (100).Type: GrantFiled: October 18, 2000Date of Patent: July 16, 2002Assignee: Delphi Technologies, Inc.Inventors: Donald Milton Trombley, Robert Ray Voltenburg, Jr., David Brian Houser, Paul Dennis Scheller
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Patent number: 6411518Abstract: A high-density mounted device, in which a plurality of semiconductor devices such as semiconductor element or module boards, are mounted on a wiring board, includes an adhesive sheet which is interposed between the wiring board and the semiconductor device. The adhesive sheet has a sheet-like base board made of an adhesive member and a plurality of conductive Sections provided at predetermined pitches in the sheet-like base member. The conductive sections are electrically insulated from each other, and extend from one side of the sheet-like base member to the other side thereof, and enable electrical connection between the electrode terminals of the wiring board and the electrode terminals of the semiconductor device. The conductive sections work as heat conductive channels between the wiring board and the semiconductor device.Type: GrantFiled: August 8, 2000Date of Patent: June 25, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masaaki Okada
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Patent number: 6403895Abstract: A semiconductor device includes a wiring substrate which includes a wiring pattern provided per each wiring with a land covering an external terminal mounting perforation for mounting an external terminal, said land being provided on a side of the wiring pattern on which side a semiconductor chip is mounted, wherein a plurality of second pads for electrically connecting the wiring and the semiconductor chip by wire bonding are provided per each wiring, and at least one of the second pads is provided between lands.Type: GrantFiled: February 4, 2000Date of Patent: June 11, 2002Assignee: Sharp Kabushiki KaishaInventor: Yoshiki Sota
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Patent number: 6396706Abstract: Separate heating elements are embedded in a printed circuit board near integrated circuit (IC) packages or other parts mounted on the circuit board. Each heating element supplies heat to the part residing near it in response to an input voltage pulse. The heating elements are used to selectively melt solder or adhesives attaching the parts to the circuit board so that they can be easily removed or to temporarily melt solder or cure adhesive when the parts are mounted on the circuit board. The heating elements are also used to supply heat to IC packages for regulating their operating temperatures.Type: GrantFiled: July 30, 1999Date of Patent: May 28, 2002Assignee: Credence Systems CorporationInventor: Paul D. Wohlfarth
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Patent number: 6396712Abstract: A system for connecting a combination of substrates, including chips, components, printed-circuit-boards and multiple-chip-modules to each other. The system includes a half-conductive layer forming a resistive network sandwiched between the mating substrates. The half-conductive layer has sufficient conductance to allow electrical coupling between mating electrodes on the substrates, and sufficient resistance, to stay below the maximum specified cross-talk level between non-mating electrodes. The connection system can be used to connect light emitting sources with integrated circuits, detectors to integrated circuits and two integrated circuits of the same or possibly different technology to each other. Connection of integrated circuits to printed circuit boards (PCBs) and multi-chip modules (MCMs) is also supported.Type: GrantFiled: February 12, 1998Date of Patent: May 28, 2002Assignee: Rose Research, L.L.C.Inventor: Maarten Kuijk
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Publication number: 20020008967Abstract: The invention relates to a power module with a circuit arrangement provided with active semiconductor components and passive components and with a circuit substrate, whereby at least a portion of the active semiconductor components are soldered onto a DCB substrate and at least a portion of the passive components are printed in thick film technology on at least one ceramic substrate. The upper side of the DCB substrate is structured to form track conductors and connecting surfaces for receiving the active semiconductor components and passive components of the circuit arrangement. On the ceramic substrate, for each passive component, a first print layer is printed in thick film technology and at least one contact surface as additional print layer laterally adjoining the first print layer.Type: ApplicationFiled: August 30, 1999Publication date: January 24, 2002Inventors: HANS-PETER FEUSTEL, FRIEDRICH LOSKARN, REINHARD RUCKERT
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Patent number: 6288905Abstract: A module, such as a contact module for embedding an electronic device into a credit card, smart card, identification tag or other article, comprise a pattern of metal contacts having a first and a second surface and electrically-conductive vias built up on the first surface of the metal contacts. A layer of dielectric adhesive on the first surface of the pattern of metal contacts surrounds the electrically-conductive vias except the ends thereof distal from the metal contacts. An electronic device has electrical contacts connected to the exposed ends of the conductive vias, as by wire bonds or by flip-chip type connections.Type: GrantFiled: October 4, 1999Date of Patent: September 11, 2001Assignee: Amerasia International Technology Inc.Inventor: Kevin Kwong-Tai Chung
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Patent number: 6281445Abstract: A connection device for use in connection between two electronic components and a connection device provided on a first electronic component. The connection device includes two metal layers which have mutually different coefficients of thermal expansion, and a plurality of side wall pieces that are provided on the metal layers so as to form a connecting space for a second electronic component.Type: GrantFiled: July 12, 1999Date of Patent: August 28, 2001Assignee: NEC CorporationInventor: Takashi Yokoyama
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Patent number: 6281450Abstract: A substrate for mounting a semiconductor chip having bumps using an adhesive thereon, said substrate being, for instance, provided with an insulating coating having an opening in the semiconductor chip mounting area so that the wiring conductors will not be exposed to the substrate surface near the boundary of the semiconductor chip mounting area, is improved in connection reliability and has high mass productivity.Type: GrantFiled: December 27, 1999Date of Patent: August 28, 2001Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoyuki Urasaki, Yasusi Simada, Yoshiyuki Tsuru, Akishi Nakaso, Itsuo Watanabe
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Patent number: 6259038Abstract: A semiconductor chip mounting circuit board includes a substrate, a wiring circuit formed on a substrate, a conducting pad electrically connected to an electrode of a semiconductor chip which is to be mounted on the substrate. An insulating resist layer is formed on the substrate to cover the wiring circuit and the resist layer has an opening to expose therein the conducting pad. A conducting bump is formed on the conducting pad exposed in the opening. A resist layer has a measuring opening which exposes a reference surface. A height of the conducting bump can be measured by an optical means using the measuring opening.Type: GrantFiled: July 21, 1999Date of Patent: July 10, 2001Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Naoyuki Koizumi, Kenkichi Arai
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Patent number: 6252175Abstract: An electronic assembly comprising an electronic substrate and a plurality of conductive interconnection elements. The substrate has a first side having a plurality of terminals. Each interconnection element has a base secured to a respective one of the terminals, a contact region distant from the electronic substrate, and an elongate freestanding section which can bend when pressure is applied to the contact region.Type: GrantFiled: September 16, 1999Date of Patent: June 26, 2001Inventor: Igor Y. Khandros
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Patent number: 6225702Abstract: A semiconductor device manufactured as a ball grid array, chip scale package, or other surface mounting package wherein shorting between a power supply terminal and a ground terminal can be prevented. At least one solder ball functioning as a signal electrode is disposed between a solder ball functioning as a power supply electrode and a solder ball functioning as a ground electrode on the mounting surface of the package.Type: GrantFiled: February 4, 1998Date of Patent: May 1, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hisashi Nakamura