Abstract: A semiconductor device package comprises an integrated circuit chip (10), a substrate (16), an encapsulant (30), and an organic coupling agent or underfill material (12) disposed between the integrated circuit chip and the first side of the substrate. The chip has a plurality of interconnection pads (14) disposed on an active surface of the chip at some minimum spacing "X." Each of the interconnect pads also has electrically conducting bumps (26) on them. The substrate has a circuit pattern (20) on a first side and an array of solder pads (23) spaced a certain distance apart on an opposite side of the substrate. The distance between these pads is greater than the minimum distance (X) between the interconnect pads on the IC. The circuit pattern is electrically connected to the array of solder pads by plated through holes (22). The length and width of the circuit carrying substrate is substantially greater than the length and width of the integrated circuit chip.

Abstract: An assembly for mounting a plurality of electrical components having terminals with leads onto a surface of a printed circuit board is disclosed. The assembly includes a substantially planar configured electrically insulated body member having top to bottom surfaces. Cavities extend through the body member and are dimensioned for receiving an electrical component and holding the component laterally by the walls defining the cavity. An elastomer element with conductive portions is positioned adjacent to the bottom surface of the cavities and receives the leads of electrical components. A lid is connected to the body member and movable from an open position for allowing insertion and removal of electrical components to and from the cavities, and a closed position where the lid covers the cavities.

Abstract: An integrated circuit assembly that prevents silver migration by providing conductive rims around oxidizable silver contacts that contact a substrate. Typically the silver contacts are supported by respective metal pads on the substrate with a contact potential existing at each contact-pad junction. In many applications an electrical circuit transmits electrical signals via the contacts to produce potential differences between the contacts and create electrical fields at their surfaces. The conductive rims have a work function that is sufficiently small to reduce the electric fields and contact potentials so as to inhibit the ionization of the oxidized contacts' surfaces and prevent silver migration across the metal pads and the substrate.

Abstract: A hybrid integrated circuit of the invention is formed of an insulation substrate, a thick film conductor printed and sintered on the insulation substrate, and a terminal conductor and a circuit part connected to the first thick film conductor. A first electrically conductive metal plate is brazed on the first thick film conductor and connects the circuit part and the first terminal. Electric current between the circuit part and the first terminal mostly flows through the metal plate.

Abstract: Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability.

Abstract: An element joining pad for a semiconductor device mounting board includes a thick-film metalized layer, a barrier layer, and a Ni plating layer. The thick-film metalized layer is selectively formed on a low-temperature sintered board and consists of one of a metal and an alloy which can be sintered at 500.degree. C. or more and 1,200.degree. C. or less. The barrier layer is formed on the thick-film metalized layer and constituted by one of a Rh plating layer and a Ru plating layer. The Ni plating layer is formed on the barrier layer.

Abstract: A package for mounting I/C chips onto a circuit board is provided. The chip has a surface array of input/output pads on one side which forms a footprint. A carrier is formed of an organic dielectric material having opposite surfaces. A first set of bonding pads is formed on one surface of the chip carrier and arranged to correspond with the chip footprint. A first set of solder ball connections connects the input/output pads on the chip to the first set of bonding pads on the chip carrier. A second set of bonding pads is formed on the other surface of the chip carrier forming a second set of bonding pads. Electrically conducting vias extend through the chip carrier connecting the first set of bonding pads to the second set of bonding pads. An organic circuit board having a coefficient of thermal expansion similar to the chip carrier having electrical connector sites is provided, the sites are arranged in a pattern corresponding to the pattern of the second bonding pads on the chip carrier.

Abstract: A large number of pads, to which component leads are to be soldered, are formed on an insulating substrate so as to constitute a pad array. Colder layers are precoated on the pads. Each of the pads has a component lead mounting portion where a component lead is to be mounted, and a component lead non-mounting portion where no component lead is to be mounted. The component lead non-mounting portion includes a wide part having a width greater than that of the component lead mounting portion.

Abstract: An electrical contact and method for making an electrical contact allows a flat contact (404) to be formed early in the process of making an electronic device. The flat contact (404) is level with the remainder of the substrate (116) in which it is formed. The flat contact (404) does not interfere with any required subsequent process steps. The flat contact can be reflowed to form a ball contact (302) which protrudes above the top of the substrate (120) to which it is attached.

Abstract: Electric elements such as a resistance chip, a capacitor chip, a semiconductor device package, and a connector are mounted on a printed circuit board by using at least two methods selected from the re-flow method using cream solder, the chip-on board method using bonding wires, the outer lead bonding method, and the thermal pressing method using heat-seal. The printed circuit board is provided with lands having surface layers of a non-electrolysis Ni--Au plate, a soft Au plate and an electrolysis solder plate, each corresponding to a selected mounting method.

Abstract: An electromagnetically shielded self-molding package for an electronic component comprises a pair of bags having an electrically conductive coating therebetween and disposed about the component and having a polymerizable resin completely filling the space between the bags and the component.

Abstract: A multilayer substrate is constituted by laminating a plurality of sheet substrates, the respective sheet substrates are constituted by forming conductive layers of a refractory metal such as tungsten (W) on ceramic green sheets composed mainly of an alumina ceramic, and the ceramic green sheets are laminated and sintered to constitute the multilayer substrate. Conductive material layers are formed on the surface of the multilayer substrate so as to be selectively connected to the conductive layers, and copper-plated layers are formed on the conductive material layers. Thick film conductor layers are formed on the copper-plated layers, to constitute terminal conductors, and, a thick film resistor layer for example is connected to the terminal conductors.

Abstract: A process for reflow mounting an electronic component includes coating a terminal electrode on a mounting board with a second solder having a second melting point higher than a reflow temperature, placing the mounting board with the electronic component on a mounting land on a conveyor which may be brought into contact with the second solder on the terminal electrode, and heating the mounting board to the reflow temperature. The terminal electrode may be coated with a solder repelling material at a selected dividing area effective for dividing the terminal electrode into a plurality of sections substantially isolated from each other in terms of solder flow. Alternatively, a mounting jig may be used for supporting the mounting board without bringing the second solder on the terminal electrode into contact with the mounting jig.

Abstract: An opening 11 is formed in a region of a circuit board 10 opposite to a vibration region E of a piezoelectric element 5. The piezoelectric element 5 is mounted on the circuit board 10, and electrode connection portions 9 of the piezoelectric element 5 are connected with and fixed to the circuit board by a solder. In succession, soldered connection portions kept away from the vibration region E of the piezoelectric element 5 are filled with a bonding agent 8. Thereupon, an excess bonding agent 8 with which the soldered connection portions are filled is eliminated by the opening 11, and hence is prevented from invading the vibration region E of the piezoelectric element 5. Further, any stress exerted on the circuit board 10 is dispersed because of its being mostly received by the bonding agent 8, and hence any stress exerted on the piezoelectric element 5 is reduced.

Abstract: A plurality of pads are formed on a circuit board body at a pitch of 0.5 mm or less. The pads are formed such that a projecting height H of a pad from the board body surface and a width W of the pad satisfy a relation 2H<W, that a pad array is formed in which a width of each of the pads located at two ends of the pad array is larger than that of a pad located therebetween, and that the pad width W and a pad-to-pad distance D satisfy a relation W>D. A solder layer, obtained by a substitution reaction between a powder of a metal having the highest ionization tendency among metals constituting the solder layer or a powder of an alloy thereof and a salt formed by bonding the other metal or metals in the solder layer to an organic acid, is formed on each pad.

Abstract: Pads for surface-mount components are formed in elongated rectangular openings in a circuit board directly from stripped portions of insulated hookup wire, thus eliminating additional interconnecting hardware parts and dependency on printed circuitry. For each pad, the wire is formed into a U shape by pressing the wire into the opening from a wiring side the circuit board with a press-driven mandrel shaped to place side portions of the loop at ends of the opening, and a solid, spring-loaded or adhesive filler inserted into the opening between the side wire portion to anchor the loop in place. The bridge portion of the loop, forming the pad, may be positioned so as to be recessed slightly below the circuit board surface so as to capture component leads in the depressed cavity with solder barriers between pads. Alternatively the pad may be located flush with the circuit board or slightly protruding, the location being determined by the travel of the press-driven mandrel.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a copper sheet and a thermally conductive polyimide material insulating layer to which is also bonded a layer of a b-stage epoxy resin. The ground plane assembly is then bonded to the lead frame by placing the b-stage epoxy layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage epoxy resin to the lead frame without oxidizing it. An integrated circuit die is then attached to the composite assembly with an epoxy adhesive and the die attached assembly is then cured in a nonoxidizing atmosphere in an oven at approximately 150.degree. C.