Shaped Lead On Components Patents (Class 361/773)
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Patent number: 5786985Abstract: A semiconductor device is adapted to be mounted on a circuit substrate in an approximate vertical position. The semiconductor device includes a semiconductor chip, a stage having a first surface and a second surface opposite to the first surface, where the semiconductor chip is mounted on the first surface, a resin package encapsulating the semiconductor chip, where the resin package has upper and lower surfaces and side surfaces, a plurality of leads respectively having one end electrically connected to the semiconductor chip and another end extending downwardly from the lower surface of the resin package, and an upper extension, provided on the stage, extending upwardly from the upper surface of the resin package.Type: GrantFiled: November 15, 1996Date of Patent: July 28, 1998Assignee: Fujitsu LimitedInventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto, Katsuhiro Hayashida, Mitsutaka Sato, Hiroshi Yoshimura, Tadashi Uno, Kosuke Otokita, Tetsuya Fujisawa
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Patent number: 5786989Abstract: A mounting structure for mounting a printed circuit board on a frame of an electronic device. The mounting structure comprises a body, a lead, and a threaded portion. The threaded portion is formed on the body, and receives a screw. The printed circuit board is secured to a frame of an electronic device using the mounting structure. Specifically, the mounting structure is secured to the frame using the screw. The lead is soldered to lands on a mounting surface of the printed circuit board by a process for mounting electronic parts (e.g. an IC or LSI package) on the mounting surface of the electronic device.Type: GrantFiled: January 25, 1996Date of Patent: July 28, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shin Kawabe
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Patent number: 5764486Abstract: An electrical interconnection between a flip chip and a substrate. The interconnection includes a substrate having conductive pads to which wire bumps are attached. Each wire bump includes an elastically deformable stub section attached to the ball section, and a pointed tip. The pointed tip pierces a soft conductive layer located on a conductive pads of a flip chip. The elastic deformation of the stub section provides for consistent electrical connections between the flip chip and the substrate when the flip chip and the substrate are non-planar. An adhesive is located between the flip chip and the substrate and encompasses the wire bumps.Type: GrantFiled: October 10, 1996Date of Patent: June 9, 1998Assignee: Hewlett Packard CompanyInventor: Rajendra D. Pendse
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Patent number: 5754408Abstract: Integrated circuit (IC) packages having leads projecting in the vertical direction are provided with male and female locking elements of snap fasteners that allow a pair of IC packages to be stacked into a module so as to align the leads of one package with the leads of another package. The leads of the packages are soldered to a PCB that carries the external conductors to be connected with the inner circuits of the packages. The male locking element on one of the IC packages is tightly engaged with the female locking element on another IC package to prevent the soldered leads of one package from touching the leads of another package. Multiple modules are positioned on the PCB to double the packaging density of the PCB.Type: GrantFiled: November 29, 1995Date of Patent: May 19, 1998Assignee: Mitsubishi Semiconductor America, Inc.Inventor: Nour Eddine Derouiche
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Patent number: 5751556Abstract: A method and apparatus for reducing warpage of an assembly substrate and providing registration between a surface mount technology (SMT) component and the assembly substrate. The SMT component includes mounting pins extending from the component and capable of engaging corresponding apertures in the assembly substrate. Each mounting pin is registrable with a corresponding aperture in the assembly substrate. The mounting pins are capable of providing an interference fit between the SMT component and the assembly substrate.Type: GrantFiled: March 29, 1996Date of Patent: May 12, 1998Assignee: Intel CorporationInventors: Peter O. Butler, Ricardo E. Suarez-Gartner
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Patent number: 5751203Abstract: In an inductor including a magnetic core on a top surface of a terminal table, a plurality of L-shaped conductors are inserted into the terminal table so that two ends of each of the L-shaped conductors are projecting from a side surface of the terminal table. The plurality of L-shaped conductors each have at least one stepped portion. One of the two ends which is on a higher level than the stepped portion acts as a winding terminal around which the wire is wound, and the other end which is on a lower level than the stepped portion acts as a mounting terminal used for mounting of the inductor. The winding terminal is projecting from a higher level of the side surface of the terminal table than the mounting terminal.Type: GrantFiled: July 20, 1995Date of Patent: May 12, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yutaka Tsutsumi, Haruhiko Kuwata, Makoto Shinada, Hiroshi Momoi, Shinji Nakamura
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Patent number: 5729440Abstract: The method for soldering a chip to a substrate to form a module and then soldering the module to a circuit board includes selecting a three level hierarchy of solders by the temperature required to melt. By this method, a module can be soldered to and de-soldered from a circuit board without affecting adversely the solder between the chip and the substrate. The package formed by this method is free of faults that are caused frequently during both manufacture and service.Type: GrantFiled: January 16, 1997Date of Patent: March 17, 1998Assignee: International Business Machines CorporationInventors: Miguel Angel Jimarez, Amit Kumar Sarkhel, Lawrence Harold White
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Patent number: 5726862Abstract: A leaded component (10) is provided with first and second leads (14 & 16). The leads are formed with stopping deviations (26 & 28) which prevent the leads from being inserted into a circuit board (38) beyond the stopping deviations. The leads may also be provided with retaining deviations (34 & 36) which function to retain the component on the circuit board. Further, the stopping deviations may be formed so as to indicate the polarity of a component, and finally, the stopping deviations may be provided with mounting portions (50 & 52) so that the leaded component may be surface mounted on a circuit board (54).Type: GrantFiled: February 2, 1996Date of Patent: March 10, 1998Assignee: Motorola, Inc.Inventors: Due Huynh, Thomas P. Kirby, Micheal M. Austin, John E. Herrmann
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Patent number: 5723903Abstract: Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wares are sealed by a resin molding. The thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.Type: GrantFiled: June 7, 1995Date of Patent: March 3, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Masachika Masuda, Tamaki Wada
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Patent number: 5706177Abstract: A multi-terminal surface-mounted electronic device with contact surfaces placed entirely or partly around several sides, as well as to a method for manufacturing it. The parts according to the invention allow assembly on a circuit board such as p.c.b. and foil in forward, backward and sideward direction. Previous multi-terminal surface-mounted electronic devices could as a rule be mounted in one direction only. For all other directions such as backwards and sidewards costly special constructions or fundamental changes to the circuit board (printed-circuit board, foil) were necessary. In accordance with the invention, an electronic component is located in a housing and both the electronic component and the housing are joined to a base strip. The base strip provides the terminals whose contact surfaces are so formed that they can embrace the entire housing either completely or partially.Type: GrantFiled: December 8, 1995Date of Patent: January 6, 1998Assignee: Temic Telefunken microelectronic GmbHInventors: Heinz Nather, Peter Muhleck
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Patent number: 5701234Abstract: A surface mount component which can be mounted to a surface of a printed circuit board having a plurality of bonding pads connected to circuitry provided on the printed circuit board, which includes a puck having first and second wiring patterns, and a plurality of electrical connectors, a first set of electrical connectors being connected to the first wiring pattern, and a second set of the electrical connectors connected to the second wiring pattern. During the process of manufacturing a product which incorporates the printed circuit board, a production line worker can mount the puck to the surface of the printed circuit board in a selected one of a plurality of different possible positions, with at least selected ones of the first and second sets of electrical connectors being connected to respective ones of said bonding pads, to thereby achieve a selected one of a plurality of different selectable circuit configurations.Type: GrantFiled: December 6, 1995Date of Patent: December 23, 1997Assignee: Pacesetter, Inc.Inventor: Kenneth L. Wong
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Patent number: 5684677Abstract: An electronic circuit device comprising a printed wiring board having a major surface and pads provided on the major surface of the printed wiring board, a plurality of electrodes provided partly on at least one major surface of the leadless component and partly on sides of the leadless component, a plurality of bumps provided on the pads, providing a gap between the major surface of the printed wiring board and the major surface of the leadless component, and electrically connecting those parts of the electrodes which are provided on the major surface of the leadless component to the pads, and a plurality of electrically conductive members integral with the bumps, extending from the bumps to those parts of the electrodes which are provided on the sides of the leadless component.Type: GrantFiled: July 29, 1996Date of Patent: November 4, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuro Uchida, Takashi Yebisuya, Miki Mori, Masayuki Saito, Takasi Togasaki, Yukio Kizaki
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Patent number: 5684675Abstract: A semiconductor device unit includes a holder having a plurality of holding parts, and a plurality of semiconductor devices held by the holding parts of the holder. Each of the semiconductor devices has a generally parallelepiped shape with top and bottom surfaces and at least one side surface provided with leads which are exposed whereby the semiconductor device unit stands by itself on the leads.Type: GrantFiled: June 1, 1994Date of Patent: November 4, 1997Assignee: Fujitsu, Ltd.Inventors: Norio Taniguchi, Junichi Kasai, Kazuto Tsuji, Michio Sono, Masanori Yoshimoto
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Patent number: 5657206Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.Type: GrantFiled: January 19, 1995Date of Patent: August 12, 1997Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5654878Abstract: An improved connector terminal has a profile which facilitates insertion into engagement holes on a circuit board and increases resistance to deformation. The terminals may be part of an assembly which includes a series of terminals arranged in a spaced-apart array. Each has a solder tail portion defined by a straight edge (11) proximate to the centerline (9) and a slanted edge (12) which diagonally extends from the other side and which traverses the centerline (9) to intersect with the straight edge (11) to thereby form an acute angle at the tip (E) of the terminal near the centerline (9) to provide comparable positioning allowances on the opposite sides of the centerline (9) to facilitate mounting of the terminals on a circuit board. The acute angle point is advantageous to the optical measurement of terminal intervals for the quality control.Type: GrantFiled: June 12, 1995Date of Patent: August 5, 1997Assignee: Molex IncorporatedInventors: Masami Sasao, Hideyuki Hirata
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Patent number: 5644476Abstract: The invention relates to a method of manufacturing a flexible fastening member (19) comprising a foil (1) for fastening an object (15) thereto, characterized by making at least two generally U-shaped incisions (5) which are spaced apart, which define a central portion (23) between them, and which are directed oppositely to another, the open ends of the U-shapes facing away from another so as to create two mutually opposed tags (11), and by bending the foil (1) along two parallel bending lines (13), each line being situated at the open end of a U-shaped incision (5) so as to obtain a generally U-shaped member (19) whose base is said central portion (23), and to obtain the tags (11) as extensions of the legs (25) of said U-shaped member and situated at one side of the plane (20) defined by the central portion (23), the legs (25) being situated at the other side of said plane (20).Type: GrantFiled: October 13, 1994Date of Patent: July 1, 1997Assignee: U.S. Philips CorporationInventors: Johannus W. Weekamp, Johannes Brandsma
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Patent number: 5631806Abstract: The portion of the lead which is soldered between electrical components in a circuit module includes one or more radially extending slits. Once heated, the fluid solder is drawn into the slits by capillary action. Trapped air escapes, eliminating air pockets or gaps. The result is a stronger joint and a reduction in solder overflow.Type: GrantFiled: July 31, 1995Date of Patent: May 20, 1997Inventors: Robert Fried, Kuo J. Tseng, Hsi Y. Hsiao
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Patent number: 5621619Abstract: A resistor network is disclosed which is suited for surface mount which does not incorporate wire terminations. The network is fabricated entirely from cermet, ceramic, and solder, yet will absorb thermal stresses normally associated with circuitry energization when properly mounted upon a substrate. This is accomplished by controlling the formation of solder bumps and simultaneously controlling the mounted distance between those bumps and a wiring substrate upon which the network is mounted. Additionally, the network may be formed to be either a SIP or DIP configuration, depending upon whether an additional groove is incorporated into the termination side of the substrate. Two alternative embodiments are also disclosed which incorporate various features of the invention.Type: GrantFiled: May 19, 1995Date of Patent: April 15, 1997Assignee: CTS CorporationInventors: Lewis L. Seffernick, Neal F. Thomas
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Patent number: 5615086Abstract: Apparatus for cooling a plurality of electrical components mounted to a circuit board includes a base plate mounted in proximate relation to component sites on the circuit board at which electrical components are mounted. The base plate includes alignment elements that engage a alignment plate. The electrical components are carried by the alignment plate so that when the alignment plate is installed on the base plate, engaging the alignment elements, the electrical components are registered to and installed at corresponding component sites in a manner that aligns electrical leads of the components to printed circuit pads at the component sites. The base plate and alignment plate are sealed, and a coolant circulated therethrough.Type: GrantFiled: May 17, 1994Date of Patent: March 25, 1997Assignee: Tandem Computers IncorporatedInventors: Tom W. Collins, William J. Avery, John S. Suy, David M. Tichane
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Patent number: 5612855Abstract: An adapter (1, FIG. 1) is provided for the connection of an optoelectronic component such as an LED (light emitting diode) (2) to a circuit board (8) that lies in a case (34), wherein the adaptor positions the LED close to a window (32) in the top wall (30) of the case. The adapter has a pair of passages (4, 5) for holding conductors (11, 12) that connect terminals of the LED to SMD (surface mount device) contacts (6) that connect to the circuit board. The adapter holds the LED high enough above the circuit board, for the upper face (36) of the LED to lie in or close to the level of the window, so light from the LED can be readily seen from outside the case.Type: GrantFiled: June 12, 1995Date of Patent: March 18, 1997Assignee: Rudolf Schadow GmbHInventors: Alfred Heeb, Klaus Wisskirchen
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Patent number: 5592365Abstract: There is provided a display panel assembly structure capable of achieving a highly reliable connection even when fine-pitch electrode terminals are employed. A second electrode terminal is embedded in a flexible printed circuit board, and protrudes slightly from the flexible printed circuit board within a range of 0 to 2.times.10.sup.-3 mm. By embedding the second electrode terminal in the flexible printed circuit board, an apparent thickness of the second electrode terminal is reduced while keeping the rigidity of the second electrode terminal to thereby improve etching accuracy of a top surface thereof. With the reduction of the protrusion amount of the second electrode terminal, a ratio of a thickness of an anisotropic conductive film to a diameter of a conductive particle can be made to be approximately "1".Type: GrantFiled: December 20, 1994Date of Patent: January 7, 1997Assignee: Sharp Kabushiki KaishaInventors: Takayuki Sugimoto, Yasunobu Tagusa, Hisao Kawaguchi
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Patent number: 5587885Abstract: To facilitate the registered connection between a laminated multi chip module and an associated multi-tiered circuit board, spaced series of vias are formed transversely through the circuit board and module substrates between their opposite first and second sides. Gold plated BGA leads, offset from the module substrate vias, are formed on the first module substrate side on multi-layer plating structures disposed thereon and extending along the module via interior side surfaces. A spaced series of relatively shallow, circularly cross-sectioned socket areas, offset from the circuit board vias, are also formed on the first side of the circuit board. The sockets have diameters slightly larger that those of the generally ball-shaped BGA leads of the multi chip module, and are positioned on the same centerline pattern as the leads.Type: GrantFiled: July 15, 1994Date of Patent: December 24, 1996Assignee: Dell USA, L.P.Inventor: N. Deepak Swamy
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Patent number: 5586009Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: April 9, 1996Date of Patent: December 17, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5570273Abstract: A molded integrated circuit package system of the type suitable for surface mounting is disclosed. The system includes a chip package having leads along its sides that are of the surface-mountable type, and having a plurality of connectors at its ends. A module is provided which contains components that are sensitive to solder temperatures or the chemicals used in the soldering process; examples of such components include batteries and quartz crystal resonators. The components may be disposed directly over the chip package or, in order to reduce the height of the package system, one or both of the components may be disposed outside of the outline of the chip package. The module has connectors extending therefrom that mate with the connectors on the chip package, such that the module may be removably connected to the chip package after the surface mounting of the chip package to a circuit board.Type: GrantFiled: April 8, 1994Date of Patent: October 29, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Harry M. Siegel, Tom Q. Lao, Krishnan Kelappan, Michael J. Hundt
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Patent number: 5568363Abstract: A surface mount component comprising an IC chip, and a plurality of leads extending outward from the body of the chip. The leads are interconnected by an insulating frame at their outer ends. Each of the leads is provided in the vicinity of the portion thereof joined to the frame with an outer lead portion to be electrically connected to a wiring board. The frame is integrally connected to the chip body by bridges. When the component is mounted on the surface of the wiring board, the outer lead portion of each lead is bonded to the board by a solder layer without separating off the frame.Type: GrantFiled: April 10, 1995Date of Patent: October 22, 1996Inventor: Akira Kitahara
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Patent number: 5561594Abstract: An electrical assembly comprises an electrical component having an array of contact bumps. The component is mounted on a multilayer printed circuit board having a plurality of conducting pins located in holes in the board and having pointed ends projecting above the board and making electrical contact with the bumps on the component.Type: GrantFiled: January 11, 1995Date of Patent: October 1, 1996Assignee: SGS-Thomson Microelectronics Ltd.Inventor: Elwyn P. M. Wakefield
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Patent number: 5557503Abstract: A circuit card having module strain relief and heat sink support is provided. The circuit card comprises a printed circuit board having a front and a back, a module mounted to the front of the printed circuit board, and a stiffening structure mounted to the back of the printed circuit card directly opposite from the module to provide rigidity to the printed circuit board. The module has a plurality of electrical leads making electrical connection with the printed circuit board and anchoring the module to the printed circuit board. The stiffening structure is coextensive with the plurality of electrical leads along the printed circuit board, and is of sufficient thickness and strength to resist flexure of an area of the printed circuit board in contact with the stiffening structure in response to shock and vibration applied to the module.Type: GrantFiled: May 12, 1995Date of Patent: September 17, 1996Assignee: International Business Machines CorporationInventors: Phillip Isaacs, Miles Swain
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Patent number: 5548486Abstract: An electrical connection pin blank having at least one compliant section is affixed to a first circuit board by compressive deformation in such a way that the compliant section of the pin blank projects outwardly from the surface of the first circuit board. The end of the pin projecting from the first circuit board is then inserted into a corresponding opening in a second circuit board and the two boards brought together until the second circuit board is firmly affixed to the complaint section of the pin by compliant pin connection.Type: GrantFiled: January 21, 1994Date of Patent: August 20, 1996Assignee: International Business Machines CorporationInventors: Stephen J. Kman, John A. Stubecki, William R. Sondej
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Patent number: 5541812Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: September 11, 1995Date of Patent: July 30, 1996Inventor: Carmen D. Burns
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Patent number: 5528458Abstract: An integrated circuit device is disclosed that comprises a bare integrated circuit chip, having an integrated circuit section and pad sections, said chip being mounted on an insulated surface of a substrate, and an electro-conductive circuit pattern wiring formed on said insulating surface along the periphery of said chip. Tape automated bonding wiring is used to electrically connect the pad sections of the chip to an end of the circuit pattern wiring. Terminals are electrically connected to the other end of the circuit pattern wiring for use in electrically connecting the integrated circuit device to electronic equipment.Type: GrantFiled: November 18, 1994Date of Patent: June 18, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeo Yasuho, Hayami Matunaga, Masao Iwata, Hitonobu Furukawa
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Module for electrically connecting conductor wires to circuits of flat surfaces such as solar panels
Patent number: 5513075Abstract: A connector module (10,100,200) having at least one electrical terminal (24,116,206) therein, adapted to be sealingly mounted to a mounting surface upon being placed thereagainst at a connection site (30,112,204), and simultaneously form electrical connections of each terminal with a circuit (38,152,214) thereat, with the terminal adapted to be thereafter terminated to a discrete conductor wire (60,138,210,212) to interconnect the circuit with the wire. Upstanding lead members (40,160,216) are electrically connected to the circuits and are received into pin-receiving holes (50,172) along the module's bottom surface and become engaged with respective terminals. Each terminal is terminated to such a wire upon actuation of an actuator (26,118). A base section (14,104) of the module forms a seal with the mounting surface around the connection site (30,112,204). Such module can easily be mounted to a solar panel (32,110) or circuit board (202).Type: GrantFiled: March 2, 1994Date of Patent: April 30, 1996Assignee: The Whitaker CorporationInventors: Harry M. Capper, Sam Denovich, James W. Robertson -
Patent number: 5508888Abstract: A mechanical component peripheral lead protector covers fine pitch component leads in such a manner that nothing can come into contact with them. The lead protector is disposed above the component having the leads. It can be made of aluminum, conductive plastic or any other non ESD (electric static discharge) generating material. It can be glued, snapped, bolted or riveted to the associated PC board or glued to the top of the component, depending upon the application in which it is being used. The attachment method should be one which enables it to be removed and replaced when necessary. The center of the lead protector can be provided with an aperture so that the legends on the top of the component will be exposed.Type: GrantFiled: May 9, 1994Date of Patent: April 16, 1996Assignee: AT&T Global Information Solutions CompanyInventor: Terry Craps
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Patent number: 5506447Abstract: A hybrid integrated circuit of the invention is formed of an insulation substrate, a thick film conductor printed and sintered on the insulation substrate, and a terminal conductor and a circuit part connected to the first thick film conductor. A first electrically conductive metal plate is brazed on the first thick film conductor and connects the circuit part and the first terminal. Electric current between the circuit part and the first terminal mostly flows through the metal plate.Type: GrantFiled: June 7, 1994Date of Patent: April 9, 1996Assignee: Fuji Electric Co., Ltd.Inventor: Tadayoshi Murakami
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Patent number: 5493476Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: May 22, 1995Date of Patent: February 20, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5490040Abstract: An electrical device for logic circuits having a package comprising a combination of controlled collapse electrical interconnections, such as solder balls and pin through-hole conductors, wherein the conductors are disposed outside the perimeter of an inter-array of solder balls, which when a maximum number of solder balls are disposed, the array is circular in shape, so as to provide an increased footprint for the electrical device beyond that, otherwise maximum footprint for solder balls alone, which footprint is otherwise limited in size due to failures which occur in solder balls when solder balls are exposed to thermal and mechanical stress levels at extended distances from the neutral or zero stress point of the array.Type: GrantFiled: December 22, 1993Date of Patent: February 6, 1996Assignee: International Business Machines CorporationInventors: Gene J. Gaudenzi, Joseph M. Mosley, Vito J. Tuozzolo, John C. Milliken
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Patent number: 5461539Abstract: An electronic component is provided which comprises a resin package for enclosing inside parts. The package has a heat sensitive surface portion provided with a heat sensitive material which irreversibly discolors at a temperature higher than the soldering temperature for the electronic component. The component may be a solid tantalum capacitor, solid aluminum capacitor, diode or transistor which generates heat under abnormal operating conditions.Type: GrantFiled: February 10, 1995Date of Patent: October 24, 1995Assignee: Rohm Co., Ltd.Inventors: Chojiro Kuriyama, Eisaku Tanaka
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Patent number: 5460319Abstract: A lead for achieving solder joining with great vibration strength includes an upper lead portion having a clip and a lower lead portion having a thin tip for insertion into an electrode in a lower substrate and an oblong through hole in the body of the lower lead portion for inducing capillarity of soldering flux.Type: GrantFiled: June 22, 1993Date of Patent: October 24, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hazime Kato
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Patent number: 5459641Abstract: A polar electronic component is provided which comprises a polar element, a first lead electrically connected to a first pole of the polar element, a second lead electrically connected to a second pole of the polar element, and an insulating package enclosing the polar element together with part of the first and second leads. The first lead has two terminal legs which are bent toward the underside of the package and transversely spaced from each other by an interval. The second lead has a terminal leg which is bent toward the underside of the package and extends into the spacing between the two terminal legs of the first lead in longitudinally overlapping relation.Type: GrantFiled: February 14, 1995Date of Patent: October 17, 1995Assignee: Rohm Co. Ltd.Inventor: Chojiro Kuriyama
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Patent number: 5450289Abstract: An arrangement for vertically mounting a semiconductor device to a substrate, e.g., a printed circuit board (PCB), in which a plurality of sequentially arranged external leads of the semiconductor device include at least three different sets of non-consecutive ones of the external leads which have laterally outwardly extending foot portions lying in respective, vertically spaced-apart planes, and in which the foot portions of first and second ones of the sets of non-consecutive external leads are respectively secured to respective first and second steps formed in one of a plurality of walls defining a cavity in the PCB, and a third set of the non-consecutive external leads are secured to a portion of a major surface of the PCB adjacent the cavity.Type: GrantFiled: March 7, 1994Date of Patent: September 12, 1995Assignee: Samsung Electronics Co., Ltd.Inventors: Yooung D. Kweon, Min C. An
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Patent number: 5446623Abstract: A surface mounting type polar electronic component is provided which comprises a polar element electrically connected to a positive lead and a negative lead, and a package enclosing the polar element together with part of the respective leads, the package having a mounting face. The leads have respective contact ends bent substantially in parallel to the mounting face of the package for contact with corresponding electrode pads of a circuit board. One of the leads has a projection extending beyond the contact end of said one lead for insertion into an insertion hole formed at a relevant one of the electrode pads.Type: GrantFiled: August 23, 1994Date of Patent: August 29, 1995Assignee: Rohm Co. Ltd.Inventor: Yasuo Kanetake
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Patent number: 5446245Abstract: A flexible circuit wiring board having protruding, closely spaced leads, which are intended to be attached to a circuit device, is fabricated by forming a conductor pattern on a first surface of an insulating substrate, adhereing a protection layer to the conductor pattern and employing a laser to selectively etch away the substrate. The etching process leaves a reinforcing coating of the protective layer on the leads at least in the portions thereof which lie at the boundary of the area from which the substrate has been removed.Type: GrantFiled: May 31, 1994Date of Patent: August 29, 1995Assignee: Nippon Mektron, Ltd.Inventors: Takeshi Iwayama, Atsushi Miyagawa, Masaichi Inaba
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Patent number: 5440452Abstract: A surface mount component comprising an IC chip, and a plurality of leads extending outward from the body of the chip. The leads are interconnected by an insulating frame at their outer ends. Each of the leads is provided in the vicinity of the portion thereof joined to the frame with an outer lead portion to be electrically connected to a wiring board. The frame is integrally connected to the chip body by bridges. When the component is mounted on the surface of the wiring board, the outer lead portion of each lead is bonded to the board by a solder layer without separating off the frame.Type: GrantFiled: May 12, 1993Date of Patent: August 8, 1995Assignee: Akira KitaharaInventor: Akira Kitahara
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Patent number: 5432678Abstract: A mounting device (170) of a semiconductor integrated circuit (202) allows edge mounting on surface of a printed circuit board (250). The mounting device includes a top portion (150) to provide for cooling and protection of the semiconductor chip while a side portion (140) provides for cooling and positioning on the printed circuit board.Type: GrantFiled: May 12, 1994Date of Patent: July 11, 1995Assignee: Texas Instruments IncorporatedInventors: Ernest Russell, Daniel Baudouin, James S. Wallace
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Patent number: 5420756Abstract: TCP (tape carrier package) type semiconductor memory elements, each having a thickness less than that of the conventional package, are provided on the front and rear surface of a print circuit board in a stacking manner. Close to the semiconductor memory elements stacked, provided are TCP type semiconductor memory elements stacked one on another. Each TCP type semiconductor memory element has outer leads on its one side surface. The outer leads having the same function are arranged in a straight line on the front or rear surface of the print substrate. The outer leads arranged in the straight line are connected with each other via a straight wiring pattern.Type: GrantFiled: June 16, 1993Date of Patent: May 30, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Akio Katsumata, Kimihiro Ikebe
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Patent number: 5400220Abstract: To facilitate the registered connection between a ball grid array package and an associated multi-tiered circuit board, a spaced series of vias are formed transversely through the board substrate between its opposite first and second sides. A spaced series of relatively shallow, circularly cross-sectioned socket areas, offset from the vias, are also formed on the first side of the circuit board. The sockets have diameters slightly larger that those of the generally ball-shaped leads of the BGA package, and are positioned on the same centerline pattern as the leads. After the vias and sockets are formed, a multi-layer metallic coating is deposited on their interiors and around their open ends on the first board side, with the coating being extended across the first board side between associated socket and via pairs.Type: GrantFiled: May 18, 1994Date of Patent: March 21, 1995Assignee: Dell USA, L.P.Inventor: Deepak Swamy
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Patent number: 5392193Abstract: A transistor mounting device (102) includes a recess area (112) for allowing a transistor (114)to be secured to the transistor mounting device (102) by turning the transistor a certain amount. Once the transistor (114) is secured into position to the transistor mounting device (102), a set of transistor pads (402) provide support and alignment to the transistor fins (116).Type: GrantFiled: May 31, 1994Date of Patent: February 21, 1995Assignee: Motorola, Inc.Inventors: William H. Robertson, Jr., Chot Q. Pham, Philip C. Warder, James L. Stephens
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Patent number: 5389743Abstract: A ceramic circuit card (10) for a missile utilizing a "rivet" design and a method for making the same wherein thick-film copper I/O pads (15) are fabricated on a first dielectric layer (13) and on the upper surface of conducting material (20) in vias (14) formed in the dielectric layer (13). A first conductor layer (11) is printed directly on an alumina ceramic layer (12). The dielectric layer (13) is then printed on the first conductor layer (11) and on the alumina ceramic layer (12). During operation, each I/O pad (15) has attached to it a flex harness (21) for connecting the card (10) to a printed wiring board (22) on which the card (10) is mounted. The ceramic circuit card (10) is further comprised of additional dielectric and conductor layers in an alternating stacked arrangement. The top conductor layer is used to connect the circuit card to other electrical components.Type: GrantFiled: December 21, 1992Date of Patent: February 14, 1995Assignee: Hughes Aircraft CompanyInventors: Charles E. Simila, Mradul Mehrotra
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Patent number: 5386344Abstract: A flex circuit card with an elastomeric cable connector assembly is provided for transmitting high speed signals between two or more printed circuit boards in a high performance computer system. The flex circuit card connects a cable assembly to a printed circuit board. A conductor trace in the flex circuit card extends into an elastomeric end and terminates with a ball shaped contact which is angled to wipe against mating pads on the printed circuit card for making electrical contact. The cable assembly uses multiple wires attached to a plurality of elastomeric connectors. At least one elastomeric connector is attached to each end of the cable assembly and each elastomeric connector has a plurality of contacts which are used to mate with a plurality of pads on the surface of the printed circuit board. The elastomeric connector described in the present invention provides a high density, cable-to-board interconnection that is perpendicular to the surface of the printed circuit board.Type: GrantFiled: January 26, 1993Date of Patent: January 31, 1995Assignee: International Business Machines CorporationInventors: Brian S. Beaman, Fuad E. Doany, Thomas J. Dudek, Alphonso P. Lanzetta, Da-Yuan Shih, William J. Tkazyik, George F. Walker
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Patent number: 5383094Abstract: A specially designed electronic component is surface mounted on a printed circuit board substrate member having a spaced series of electrically conductive circuitry connection portions disposed on a side surface thereof. The electronic component has a body portion with a spaced series of elongated metal lead members fixedly secured thereto and projecting outwardly therefrom. Longitudinal portions of the lead members are soldered to the circuitry connection portions. Side surface areas of these longitudinal portions are clad with a second metal material having a coefficient of thermal expansion substantially different than that of the underlying longitudinal lead member portions. During fabrication of the circuit board a solder paste material is deposited on the circuitry connection portions and the lead member longitudinal portions are placed in a closely adjacent, aligned relationship with the circuitry connection portions.Type: GrantFiled: October 28, 1993Date of Patent: January 17, 1995Assignee: Dell USA, L.P.Inventor: Howard S. Estes
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Patent number: 5381307Abstract: A mounting pad arrangement (FIG. 5) improves reliability of placement of a surface mount component. A first pad array is disposed throughout an area on the surface (308) of a substrate (202), the area having four outside corners. The first pad array includes contact pads (502) arranged in a first linear grid pattern, and eight aligning pads (504,506,510,514,518), larger than the contact pads (502). Two aligning pads (504,506,510,514,518) are near each of the four outside corners. Each aligning pad (504,506,510,514,518) is positioned off center with respect to the first linear grid pattern such that a tangential line (608,610,612,614) can be drawn between an innermost point of the aligning pad (504,506,510,514,518) and corresponding innermost points of the contact pads (502) that are collinear on the first linear grid pattern. A second pad array (406) is disposed on the surface mount component and arranged in a second linear grid pattern that aligns with the first linear grid pattern.Type: GrantFiled: September 29, 1993Date of Patent: January 10, 1995Assignee: Motorola, Inc.Inventors: Allen D. Hertz, David A. Tribbey, Kenneth R. Thompson