Flexible Connecting Lead Patents (Class 361/776)
  • Patent number: 8054634
    Abstract: There is provided a camera module package including: a housing having an optical system; a board bonded to a bottom end of the housing and mounting an image sensor on a top surface thereof; a contact part integrally formed in the housing to electrically connect a sensor bonding pad of the image sensor with a board bonding pad of the board each other when the housing is engaged with the board. In the camera module package, a process of bonding the housing and the board together is performed at the same time as a process of electrically connecting the image sensor and the board to each other. This simplifies an assembly process and enhances productivity. Also, the camera module package is fundamentally free from contamination of external contact terminals caused by an overflowing bonding material when the board and the housing are bonded together.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Tae Jun Seo
  • Patent number: 8014165
    Abstract: A connector for mounting to a panel is provided that includes a housing that has a front edge configured to be located proximate an opening in the panel. The connector also includes a tab that extends from the front edge of the housing where the tab is oriented to engage an outer surface of the panel. A spring member also extends from the front edge of the housing and is positioned to engage an inner surface of the panel. The spring member is flexible toward and away from the tab.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: September 6, 2011
    Assignee: Tyco Electronics Corporation
    Inventors: Richard Elof Hamner, Matthew Richard McAlonis
  • Patent number: 7994425
    Abstract: A flexible wiring cable includes a first wiring assembly connected to a load, a second wiring assembly connected to the first wiring assembly and extending toward an external signal source, and a circuit element mounted on the first wiring assembly to drive the load. The second wiring assembly is connected to the first wiring assembly at a position between the mounted circuit element and a connection point with the load. Thus, the heat of the circuit element is also transferred to the second wiring assembly, so that the effect of the heat on the load is reduced.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 9, 2011
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Tomoyuki Kubo
  • Patent number: 7952888
    Abstract: An object of the present invention is to provide a wiring module that enables dense mounting and a reduction in wiring distance. The wiring module in accordance with the present invention includes a base material, a plurality of electronic circuit parts, insulating portions, and conductive portions connected to the electronic circuit parts, the plurality of electronic circuit parts, the insulating portions, and the conductive portions being integrally held on the base material. Wires are composed of a stack of the conductive portions and extend in a direction crossing a surface of the base material and in a direction crossing a direction perpendicular to the base material surface to electrically connect the plurality of electronic circuit parts together.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: May 31, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhito Yamaguchi, Yuji Tsuruoka, Takashi Mori, Masao Furukawa, Seiichi Kamiya
  • Patent number: 7947908
    Abstract: An electronic device is provided. The electronic device includes: a circuit board having a surface on which a hollow is formed; an electronic component placed into the hollow; a pattern wiring which is formed on a bottom surface of the hollow and whose tip is provided at a position corresponding to a signal electrode of the electronic component; a signal wire connecting a tip of the pattern wiring and the signal electrode of the electronic component; two in-hollow ground patterns formed so as to sandwich the tip of the pattern wiring therebetween on the bottom surface of the hollow; and two or more ground wires that connect two ground electrodes provided on the electronic component so as to sandwich the signal electrode therebetween to the corresponding in-hollow ground patterns, respectively.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: May 24, 2011
    Assignee: Advantest Corporation
    Inventors: Shoichi Mizuno, Hiroaki Takeuchi, Shuji Nojima
  • Patent number: 7889513
    Abstract: A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihiko Shimanuki
  • Publication number: 20110019378
    Abstract: Composite microelectronic contacts are provided in embodiments. These may include one or more arrays of isolated conductive tines coupled to and by isolation carriers. These carriers may serve to space the conductive tines apart and to couple the isolated tines together after the tines are no longer ganged together. The isolation carriers may comprise injection molded polymers as well as stamped materials. The isolation carriers may also contain locking tabs and recesses and seating plane stops.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 27, 2011
    Inventors: Russell S. Aoki, Tod A. Byquist
  • Patent number: 7839657
    Abstract: A circuit board assembly includes a mother board and a daughter board. The daughter board is defined by a plurality of frangible connections to the mother board and is disposed on a common plane with the mother board. After all the electronic devices are installed to the mother board and the daughter board on a common plane the frangible connections are broken to allow the daughter board to be moved to a desired position relative to the mother board. The electrical conductors that connect the daughter board to the mother board are semi-rigid to provide movement while maintaining a desired position of the daughter board relative to the mother board.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: November 23, 2010
    Assignee: Continental Automotive Systems US, Inc.
    Inventor: Thomas H. Nodine
  • Patent number: 7834424
    Abstract: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: November 16, 2010
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Peter Peumans, Kevin Huang, Fu-Kuo Chang
  • Patent number: 7773388
    Abstract: The present invention is to provide a printed wiring board in which malconnection or disconnection caused by a difference between coefficients of thermal expansion of a semiconductor chip and a printed wiring board can be decreased even when a highly-integrated semiconductor apparatus is mounted thereon and an electronic device using the same. An electronic device (4) according to the present invention includes a printed wiring board (1) with a component mounting pin (18) and a surface-mounting type semiconductor apparatus (2) with an electrode pad (3), wherein the component mounting pin (18) has elasticity and is urged against the electrode pad (3) to maintain electric connection.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: August 10, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Kawanishi
  • Patent number: 7742313
    Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: June 22, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mung Suan Heng, Kok Chua Tan, Vince Chan Seng Leong, Mark S. Johnson
  • Patent number: 7732713
    Abstract: A robust mechanical structure is provided to prevent small foundation structures formed on a substrate from detaching from the substrate surface. The strengthened structure is formed by plating a foundation metal layer on a seed layer and then embedding the plated foundation structure in an adhesive polymer material, such as epoxy. Components, such as spring probes, can then be constructed on the plated foundation. The adhesive polymer material better assures the adhesion of the metal foundation structure to the substrate surface by counteracting forces applied to an element, such as a spring probe, attached to the plated foundation.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: June 8, 2010
    Assignee: FormFactor, Inc.
    Inventors: Gary W. Grube, Gaetan L. Mathieu, Benjamin N. Eldridge, Chadwick D. Sofield
  • Patent number: 7728233
    Abstract: In the case of connecting a flexible substrate to a counterpart substrate by soldering, the area of a dead space on the counterpart substrate due to being covered with the flexible substrate is reduced to reduce the outside dimension of the counterpart substrate. Solder lands 61 and 62 on the flexible substrate 5 are soldered to solder lands 21 and 22 on the counterpart substrate 1. The flexible substrate 5 is divided into two branching pieces 71 and 72 by an incision 7 or a slit 8 formed in such a manner as to extend from an intermediate part in the arrangement direction R of circuit patterns to the leading end of the flexible substrate. The space between the solder lands 61 and 62 on the respective pieces 71 and 72 is made equal to the space between the two spaced-apart solder lands 21 and 22 on the counterpart substrate 1 by placing the pieces 71 and 72 formed by dividing the flexible substrate 5 on one another.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: June 1, 2010
    Assignee: Funai Electric Co., Ltd.
    Inventor: Tetsuo Nishidate
  • Patent number: 7652890
    Abstract: A wired circuit board includes a wiring formation portion, a terminal formation portion, and a middle portion formed therebetween. The wiring formation portion includes a first conductive layer formed on a first insulating layer, and a second conductive layer formed on a second insulating layer so as to overlap the first conductive layer in a thickness direction. The terminal formation portion includes the first and second conductive layers formed in parallel in the same plane. The middle portion includes the first conductive layer formed on the first insulating layer, and the second conductive layer formed on a portion of the second insulating layer extending from the wiring formation portion to a mid-point between the wiring formation portion and the terminal formation portion, and formed on a portion of the first insulating layer extending from the mid-point to the terminal formation portion.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: January 26, 2010
    Assignee: Nitto Denko Corporation
    Inventors: Tetsuya Ohsawa, Katsutoshi Kamei
  • Patent number: 7652895
    Abstract: The invention relates to an electric insulating body (2) provided with a conductor pattern (1) and an electronic device (10) comprising such a body (2) and at least one electronic element (30). According to the invention, the body (2) has first and second faces (2A, 2B) in between of which an angle of less than 180 degrees is defined, wherein the conductor pattern (1) of the body (2) extends over both faces (2A, 2B), which body (2) carries both the conductor pattern (1) and the electronic element (30). The conductor pattern (1) comprises strip-shaped regions (1A) and regions (1B) with a larger width than the strip-shaped regions (1A), which regions (1B) are suitable for electrically contacting the electronic element (30). The electronic element (30) is, for example, a camera. The device (10) with such a camera is particularly suitable for use in a mobile communication apparatus.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: January 26, 2010
    Assignee: TPO Displays Corp.
    Inventors: Fransiscus Gerardus Coenradus Verweg, Johannus Wilhelmus Weekamp
  • Patent number: 7629691
    Abstract: A flexible conductor formed on a flexible substrate. In one embodiment, a semiconductor device is disclosed. The semiconductor device comprises a periodic structure of islands and at least one conductor. The at least one conductor comprises a series of repeating geometric features affixed to the periodic structure of islands. The geometric features of the conductor are adapted to stretch the conductor rather than break the conductor when the substrate is bent.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: December 8, 2009
    Assignee: Honeywell International Inc.
    Inventors: Jerry A. Roush, John F. Schmidt, Sonia R. Dodd
  • Publication number: 20090273911
    Abstract: According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected.
    Type: Application
    Filed: May 5, 2008
    Publication date: November 5, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Justin Potok Bandholz, Thomas Dixon Pahel, Jr., Pravin Patel, Philip Louis Weinstein
  • Patent number: 7542304
    Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: June 2, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Russell Rapport, James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Jeff Buchle
  • Patent number: 7518882
    Abstract: In respect to an electrical connection between a control circuit board 20 and bus bars 14 interbonded together, it is an object to enhance stability in quality and reliability in connection. As a solution for achieving the object, the control circuit board 20 is provided with a conductor segment 26 to be electrically connected to a specific one of the bus bars 14 on the opposite side of a rear surface thereof bonded to the bus bars 14, and a through-hole 24 penetrating a main body thereof at a position adjacent to the conductor segment 26 so as to expose the specific bus bar 14 therethrough. Further, an electrically-connecting member 70 is disposed to bridge over the through-hole 24 and the conductor segment 26, and soldered onto the conductor segment 26 and the bus bar portion located in the through-hole 24.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: April 14, 2009
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd.
    Inventors: Toshiki Shimizu, Kouichi Takagi, Fumiaki Mizuno
  • Publication number: 20090067144
    Abstract: An integrated circuit connector is extendable for a variety of applications. In connection with various embodiments, an electrical connector has first and second ends connected to respective circuit nodes in an integrated circuit device. The connector is bundled between the circuit nodes (e.g., substantially all of the connector is located between nodes), and is extended from such a bundled state in which the first and second connected ends are separated by a first proximate distance. The connector is applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance by at least two orders of magnitude.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 12, 2009
    Inventors: Giulia Lanzara, Fu-Kuo Chang
  • Patent number: 7485951
    Abstract: An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. The present invention may be employed to stack similar or dissimilar integrated circuits and may be used to create modularized systems. In a preferred embodiment, a die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer such as a molded plastic, for example, is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: February 3, 2009
    Assignee: Entorian Technologies, LP
    Inventors: David L. Roper, Curtis Hart, James Wilder, Phill Bradley, James G. Cady, Jeff Buchle, James Douglas Wehrly, Jr.
  • Patent number: 7429786
    Abstract: A semiconductor package subassembly includes a die affixed to, and electrically interconnected with, a die attach side of a first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the first package with the first side of the second substrate facing the die attach side of the first package substrate, and supported by a spacer or a spacer assembly. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 30, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Marcos Karnezos, Flynn Carson
  • Publication number: 20080192967
    Abstract: The invention is to increase the degree of miniaturization, in particular of amplifier circuit boards of hearing aids. An SMD component and an electronic component of a circuit arrangement are to be electrically connected to each other by a wire bond connection. The circuit arrangement comprises a printed circuit board and an integrated circuit mounted on the printed circuit board. One or more further integrated circuits are disposed between the said integrated circuit and the printed circuit board. An SMD component is mounted directly on the integrated circuit. Alternatively, the SMD component is mounted directly on the printed circuit board and electrically connected to one of a stack of integrated circuits. The SMD component is electrically connected to the integrated circuit by means of bond wires. Space can be saved on the printed circuit board as a result of the stack wise arrangement.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 14, 2008
    Inventors: Chor Fan Chan, Meng Kiang Lim
  • Publication number: 20080192451
    Abstract: A strain-resistant electrical connection and a method of making the same is provided. An antenna (36, 38) or other conductive lead is connected to a circuit (32) in a manner that makes the connection more resistant to mechanical stresses such as movement or rotation of the antenna (36, 38) or conductive lead relative to the circuit (32). The antenna (36, 38) or conductive lead is at least partially coiled to provide additional ability to withstand mechanical stresses. The antenna (36, 38) or conductive lead may be encase along with is connected circuit in an elastomeric material.
    Type: Application
    Filed: March 9, 2005
    Publication date: August 14, 2008
    Inventors: Jay C. Sinnett, Cameron E. Smith, John David Adamson
  • Patent number: 7400514
    Abstract: The invention relates to electronic sensors comprising an electromechanical microsensor cell such as a micro-accelerometer, and it more particularly relates to the way in which the microsensor cell per se is mounted in a package that furthermore comprises a printed circuit board carrying the electronic processing circuits associated with the microsensor cell. In order to establish a non-rigid electrical connection between a conductive terminal of the board and a connection pin of the cell, a narrow strip-shaped conductive connection cut by chemical machining from a thin and flexible metal sheet (CuBe) is soldered. The strip comprises at least one circle-arc segment extending over one half-turn or three-fourths of a turn. Its resilience permits very low stiffness in all directions and therefore prevents any transmission of vibrations or shocks to the cell. The manufacture of the connections may be collective for all the connections of a sensor and for successive sensors manufactured serially.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: July 15, 2008
    Assignee: Thales
    Inventors: Philippe Guichard, Jean-Louis Le Corre, Jean-Marie Odermath, Jérôme Inglese
  • Publication number: 20080153344
    Abstract: A surface mount poke in connector is disclosed for mounting upon a surface of a printed circuit board, and is particularly applicable for printed circuit boards supporting LEDs. The connector has a securing means for engaging an inserted wire lead without the use of solder.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: TYCO ELECTRONICS
    Inventors: Sheldon Lynn HORST, Christopher G. DAILY
  • Publication number: 20080137317
    Abstract: A method and structure for producing an angled RF connection between a first element and a second element using a flexible substrate is provided. The method includes laminating a flexible substrate onto the first element; bending the flexible substrate such that a bonding pad on the flexible substrate is in a similar plane as a bonding pad on the second element; and creating the angled RF connection by wire bonding the bonding pad on the flexible substrate and the bonding pad on the second element. The structure includes a flexible substrate that is laminated onto a first element as an outer layer, flexible substrate having at least one bonding pad, and the flexible substrate able to bend in an angle that places the bonding pad in a same plane as a bonding pad on a second element.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Inventors: Robert T. Worl, Bruce L. Blaser, Peter T. Heisen, Julio A. Navarro, Douglas A. Pietila, Scott A. Raby, Jimmy S. Takeuchi
  • Patent number: 7375432
    Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventor: Erik W. Jensen
  • Patent number: 7361983
    Abstract: In a semiconductor device (1), semiconductor elements (2) and (3) are mounted on a lead frame (5) having leads (4). The semiconductor elements (2) and (3) are connected with the leads (4) by metallic wires (6) and (7). The semiconductor device (1) also has a heat sink (8). The members (2) to (8) are sealed with a plastic package (10). The leads (4) are exposed outward. Each of the end leads (4a) to (4d) has a wide first lead portion, a narrow second lead portion, a third lead portion to be inserted into an external substrate, and a protruding gap-controlling portion (9) for keeping the gap between the semiconductor device (1) and the external substrate constant. Because the heat resistance from the leads (4) to the plastic package (10) increases, the temperature-rise property of the lead is improved so that the solderability is improved.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: April 22, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Hayashi, Hisashi Kawafuji, Junichi Murai, Goro Izuta
  • Patent number: 7342182
    Abstract: A printed board suitable for having a LSI surface-mounted thereto and improves high-speed transfer characteristic while maintaining the circumference of a pad formed on the printed board. The pad is a connector pad consisting of a conductor pattern, and the area of the conductor pattern forming the pad is smaller than an area determined based on the circumference of the conductor pattern that forms the pad.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: March 11, 2008
    Assignee: Fujitsu Limited
    Inventor: Akiyoshi Saito
  • Patent number: 7339797
    Abstract: The present invention describes a pre-fabricated chip mount and a method for making the pre-fabricated mount. The mount includes a mount body and a protective ring attached to the body by a plurality of tabs. The mount also includes a plurality of inner leads in electrical communication with the wires of at least one leadframe and a receiving area for an integrated circuit chip. The present invention also describes chips mounted on the pre-fabricated mount and methods for mounting, wire-bonding and encapsulating the chip in the mount. The mounts of the present invention can also be adapted to accommodate multiple chips and multi-level bonding schemes to the chips.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: March 4, 2008
    Inventor: Robert A. Martin
  • Patent number: 7301106
    Abstract: In a laser beam printer, an elastic conductive member is disposed between a rotating axis of a transfer roller and a land portion of a power supply circuit board and the transfer roller is electrically connected to the power supply circuit board through the elastic conductive member. A front end portion of the elastic conductive member is pressed onto the land portion by its elastic force to come into contact with a solder pad formed on the surface of the land portion for electrical connection. A resist film is partially formed on the surface of the land portion and the solder pad is formed on the region on the land portion that is not covered with the resist film. Thus, a large contact area between the front end portion of the elastic conductive member and the solder pad is ensured so as to address a high voltage applied to the transfer roller. As a result, the transfer roller, etc. can be electrically connected to the power supply circuit board with certainty without increasing the number of components.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: November 27, 2007
    Assignee: Funai Electric Co., Ltd.
    Inventor: Shotaro Senga
  • Patent number: 7248480
    Abstract: A semiconductor element comprises a capacitance variable section and an inductor section. In the capacitance variable section, a variable capacitance diode equipped with first and second control electrodes is provided on an insulative substrate. The inductor section is formed on the capacitance variable section formed with the variable capacitance diode. The inductor section is formed in an insulating layer provided on the variable capacitance diode. A first input/output electrode, a second input/output electrode, and first and second control input/output electrodes are provided in exposed form on the upper side of the insulating layer provided on the capacitance variable section.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: July 24, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tadashi Chiba
  • Patent number: 7242085
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: July 10, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 7215555
    Abstract: An integrated bus bar structure plate in which a plurality of bus bars are arranged on substantially the one plain face to form an electric power circuit, wherein after the bus bar structure plate having a whole shape in which a plurality of types of electric power circuits are formed by selecting any of the connection parts of the bus bars is separated is adhered to the control circuit board whereby, for example, a desired electric power circuit is formed among the connection parts of bus bars.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: May 8, 2007
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Kouichi Takagi
  • Patent number: 7154046
    Abstract: A molecularly flexible dielectric electronic substrate for receiving an electronic device has a modulus of elasticity less tan about 500,000 psi. The molecularly flexible dielectric substrate comprises one or more sheets or layers of a molecularly flexible dielectric adhesive having a modulus of elasticity less than about 500,000 psi and having patterned metal foil electrical conductors thereon. The molecularly flexible dielectric adhesive may have a low glass transition temperature and the ability to withstand soldering.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: December 26, 2006
    Assignee: Amerasia International Technology, Inc.
    Inventor: Kevin Kwong-Tai Chung
  • Patent number: 7132736
    Abstract: Devices and methods of fabrication thereof are disclosed. A representative device includes a complaint wafer-level package having one or more lead packages. A representative lead package includes a substrate having a plurality of die pads disposed thereon and a plurality of leads attached to the plurality of die pads. In addition, the lead package includes a plurality of pillars made of a low modulus material. Each pillar is disposed between the substrate and at least one lead, and each lead is disposed upon one of the pillars that compliantly support the lead.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 7, 2006
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, James D. Meindl, Chirag S. Patel
  • Patent number: 7095621
    Abstract: A leadless optical electronic package includes a lead frame having a die-attach pad and a plurality of leadless connection pads encapsulated in and extending through an encapsulation defining a planar mounting surface that can be soldered directly to a circuit board. The die-attach pad and connection pads define internal surfaces that remain partially exposed through the encapsulation. The internal surfaces are for attaching an electronic die and making electrical connections between the die and the connection pads. A die mounted on the die-attach pad is cooled more effectively and efficiently than dice in prior optical electronic packages. The leadless connection pads reduce the footprint and height of the package compared with prior optical electronic packages. The encapsulation is adapted for receiving a cover having a cover glass to allow light to pass though the cover and illuminate the die. The cover is adapted to receive an optics component for projecting light through the cover glass onto the die.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: August 22, 2006
    Assignee: Avago Technologies Sensor IP (Singapore) Pte. Ltd.
    Inventors: Lee Saimun, Gurbir Singh, Chin Yee Loong
  • Patent number: 7088002
    Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventor: Erik W. Jensen
  • Patent number: 7061088
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: June 13, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7057269
    Abstract: A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a ball grid array package. Also, a method for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: June 6, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7053477
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 30, 2006
    Assignee: ChipPAC, Inc.
    Inventors: Marcos Karnezos, Flynn Carson
  • Patent number: 7049691
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the upper and lower substrates are interconnected by wire bonding; and further in which at least one of the packages includes a stacked die package, or includes an additional stacked package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, in which one or both of the upper and lower packages is a stacked die package or in which one of the packages includes an additional stacked package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 23, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7045887
    Abstract: A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-up configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 16, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7035116
    Abstract: A memory system has a circuit board provided with a first slot connector into which a first memory module is inserted. A second slot connector is provided into which a second memory module is inserted. The first and the second memory modules are connected via a flexible bridge. The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge provides a signal bus between the memory modules.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: April 25, 2006
    Assignee: Infineon Technologies AG
    Inventor: Maksim Kuzmenka
  • Patent number: 7002225
    Abstract: An apparatus in one example includes a compliant component for supporting an electrical interface component that serves to electrically and mechanically couple a die with a separate layer. In one example, the compliant component, upon relative movement between the die and the separate layer, serves to promote a decrease in stress in one or more of the die and the separate layer. The apparatus in another example includes a compliant component for supporting an electrical interface component that serves to create an electrical connection between a die and a separate layer. The compliant component, upon relative movement between the die and the separate layer, serves to promote maintenance of the electrical connection.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: February 21, 2006
    Assignee: Northrup Grumman Corporation
    Inventor: Robert E. Stewart
  • Patent number: 6953987
    Abstract: A composite integrated circuit is formed by being molded with a mold resin, including a seat member of a lead frame, a substrate attached on the seat member of the lead frame, a heater element, and a temperature-restricted element. Here, the heater element and the temperature-restricted element are mounted on the substrate. The seat member of the lead frame includes a hollow member that is located under an intermediate area between the heater element and the temperature-restricted element.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: October 11, 2005
    Assignee: Denso Corporation
    Inventors: Koji Numazaki, Mitsuhiro Saitou
  • Patent number: 6927982
    Abstract: In a method of connecting a device to a support, in which method the device comprises at least a first terminal region, and in which method the support comprises at least a second terminal region, electrically conductive, flexible microparticles are initially produced on the first terminal region and/or on the second terminal region. Subsequently the terminal regions are connected via the electrically conductive, flexible microparticles.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: August 9, 2005
    Assignee: Infineon Technologies AG
    Inventor: Egon Mergenthaler
  • Patent number: 6922344
    Abstract: The device has a package with a base plate, and at least two terminal pins perpendicularly protruding from the base plate of the package. At least one of the terminal pins is a high-frequency terminal pin that transmits a high-frequency signal. The device has a flexible conductor arrangement with a plurality of interconnects. The conductor arrangement provides an electrical connection between the terminal pins of the package and electrical contacts of a printed circuit board. The conductor arrangement has contact regions for electrically connecting the interconnects to a terminal pin and to a contact of a printed circuit board. At least the region of the conductor arrangement that provides a connection to high-frequency terminal pin lies in a plane aligned substantially perpendicular to the plane of the base plate.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: July 26, 2005
    Assignee: Infineon Technologies AG
    Inventors: Frank Meyer-Güldner, Daniel Reznik
  • Patent number: 6882040
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: April 19, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya