Flexible Connecting Lead Patents (Class 361/776)
  • Patent number: 6882169
    Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed there in at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Kazuhiro Tashiro, Makoto Haseyama
  • Patent number: 6879033
    Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: April 12, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Futoshi Hosoya
  • Patent number: 6825422
    Abstract: An apparatus and method providing improved interconnection elements and tip structures for effecting pressure connections between terminals of electronic components is described. The tip structure of the present invention has a sharpened blade oriented on the upper surface of the tip structure such that the length of the blade is substantially parallel to the direction of horizontal movement of the tip structure as the tip structure deflects across the terminal of an electronic component. In this manner, the sharpened substantially parallel oriented blade slices cleanly through any non-conductive layer(s) on the surface of the terminal and provides a reliable electrical connection between the interconnection element and the terminal of the electrical component.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: November 30, 2004
    Assignee: Formfactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Alec Madsen, Gaetan L. Mathieu
  • Patent number: 6818840
    Abstract: Spring contact elements are attached to terminals of an electronic component, which may be a semiconductor die. The spring contact elements may comprise a flexible precursor element. The precursor element may be over coated with a resilient material. The spring contact elements may be elongate and attached to the terminals at one end. The other end of the spring contacts may be spaced away from the electronic component.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: November 16, 2004
    Assignee: FormFactor, Inc.
    Inventor: Igor Y. Khandros
  • Patent number: 6819570
    Abstract: In a circuit board of the present invention, a lead frame includes an electrode for mounting an electronic component. The lead frame is encapsulated in a resin portion. The lead frame includes a step portion exposed from a surface of the resin portion so that the electrode is formed. Accordingly, not only lead type electronic components but also surface mount type electronic components can be mounted on the surface of the circuit board. Therefore, because the electronic components can be concentrated, the lead frame circuit board can be miniaturized.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: November 16, 2004
    Assignee: Anden Co., Ltd.
    Inventors: Hideyuki Ohtani, Mutuo Taniguchi
  • Patent number: 6784378
    Abstract: Electronic packages having compliant off-chip interconnects and methods of fabricating compliant off-chip interconnects are disclosed. A representative electronic package includes a substrate and a free-standing compliant off-chip interconnect. The free-standing compliant off-chip interconnect includes a first free-standing arcuate structure that is substantially parallel to the substrate. In addition, the method of fabricating free-standing arcuate structure compliant off-chip interconnects includes: depositing an arcuate structure compliant off-chip interconnect material; and forming the free-standing arcuate structure compliant off-chip interconnect.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: August 31, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Qi Zhu, Lunya Ma, Suresh K. Sitaraman
  • Patent number: 6778406
    Abstract: Resilient contact structures provide electrical interconnection between a semiconductor die and another electronic component. Multilayered packaging may be formed on the semiconductor die, and the resilient contact structures may be formed on portions of one or more of the layers. Heat dissipating structures may be provided on the die.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: August 17, 2004
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 6778407
    Abstract: A portable data carrier includes a card-shaped body having a recess for receiving a chip module. The chip module includes at least one semiconductor chip on a first main side of a chip carrier connected to the card-shaped body, and a metallization layer disposed on a second main side of the chip carrier and having contact lugs. The chip carrier has desired bending points which, upon the occurrence of bending stresses, reduce forces on the semiconductor chip and wire connections.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: August 17, 2004
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Fischer, Manfred Fries, Frank Püschner, Annemarie Seidl
  • Patent number: 6773848
    Abstract: The application describes a cell unit which includes at least two flat electrochemical cells (1′, 1″, 1′″) and a circuit board (5), the cells being folded onto one or both sides of the circuit board whereby the circuitry on the circuit board is protected. Preferably, the cells and the circuit board have the same lengths and widths. The cells may be provided on two or more edges of the circuit board and optionally two cells are connected at the same edges on the board.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: August 10, 2004
    Assignee: Danionics A/S
    Inventors: Uffe Nortoft, Michael Thorby Jorgensen, Ole Stig Nissen
  • Patent number: 6765159
    Abstract: A switch to be mounted on a design element in the passenger room of a motor vehicle includes a haptic element that functions as a mechanical operater and a visual element. Electrical and/or electronic switch elements are mounted on a flexible conductor element and optionally further electrical and electronic components. A zone of the flexible conductor element which carries the switch elements and an allocated zone of the haptic element are configured such that the corresponding zones can be positioned and fixated in relation to one another and do not establish a permanent electrical connection.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: July 20, 2004
    Assignee: Brose Fahrzeugteile GmbH &Co.
    Inventors: Joerg Uebelein, Carsten Abert, Bernd Rexhaeuser
  • Patent number: 6762485
    Abstract: A conductive plastic lead frame and method of manufacturing, the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Jerrold L. King
  • Patent number: 6750546
    Abstract: A leadframe includes at least one peripheral lead secured to a paddle. A paddle solder bump pad and a peripheral solder bump pad are respectively situated on the at least one peripheral lead and the paddle. A first recess is adjacent to the paddle solder bump pad and a second recess is adjacent to the peripheral solder bump pad. A semiconductor die having at least first and second solder bumps is situated on the leadframe such that the first solder bump is soldered to the paddle solder bump pad while the second solder bump is soldered to the peripheral solder bump pad. The first and second recesses adjacent to respectively the paddle solder bump pad and the peripheral solder bump pad prevent solder from flowing out of the solder bump pad areas during solder reflow process. In this manner, the potential shorting of adjacent solder bump pads is prevented.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: June 15, 2004
    Assignee: Skyworks Solutions, Inc.
    Inventors: Robbie U. Villanueva, Mahyar S. Dadkhah, Hassan S. Hashemi
  • Patent number: 6743039
    Abstract: A ball grid array connector having an insulative housing with a plurality of contacts in electrical connection with corresponding solder balls that protrude from a surface of the housing. The solder balls form a soldering region for attachment to a circuit board. The housing has a center of gravity biased from a center of the soldering region, and a positional compensation member is attached to the housing and the circuit board. The positional compensation member prevents the housing from becoming inclined with respect to the circuit board when the solder balls are attached to the circuit board and prevents the housing from becoming inclined with respect to an electronic part when the electronic part is mounted to the housing on a side opposite from the circuit board.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 1, 2004
    Assignee: Tyco Electronics EC K.K.
    Inventors: Hiroshi Shirai, Akira Kubo
  • Publication number: 20040078967
    Abstract: A Z-axis electrical contact may be formed using a resinous deposit containing conductive particles which may align along surface regions to form an electrical conduction path over the resinous material. If the resinous material is thermoplastic, the material may be heated to mechanically bond to contact surfaces. Advantageously, the resinous material may be formed by forcing a resinous matrix containing conductive particles through an annular opening in a stencil. The resulting member allows surfaces to be contacted which may be irregular or may be covered by native oxide layers.
    Type: Application
    Filed: October 20, 2003
    Publication date: April 29, 2004
    Inventors: Tongbi Jiang, Edward A. Schrock
  • Patent number: 6717819
    Abstract: A solderable flexible adhesive interposer having solderable contacts includes low-modulus-of-elasticity (i.e. molecularly flexible) conductive adhesive vias to which contacts of an electronic device, such as a semiconductor chip or die or other component, are connected. The flexible adhesive interposer substrate includes a sheet or layer of a molecularly flexible dielectric adhesive having via holes therein through which the flexible conductive adhesive vias reside. A thin layer of solderable metal, preferably a plating of gold or nickel-gold, on at least one exposed surface of the flexible conductive adhesive vias provides the solderable contacts connecting electrically to the conductive vias. The electronic device may be covered by a lid or by an encapsulant attached to the flexible adhesive interposer substrate and/or the electronic device.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: April 6, 2004
    Assignee: Amerasia International Technology, Inc.
    Inventor: Kevin Kwong-Tai Chung
  • Patent number: 6717822
    Abstract: An edge stiffener added to a lead-frame based circuit module provides protection of the peripheral flange of the circuit module during handling and manufacturing processes. The edge stiffener may be coupled to leads of the lead-frame for providing electrical contacts at the periphery of the circuit module or may be form widened portions of a tie bar that is connected to the lead frame by leads extending through gaps between the ends of the edge stiffener portions. Singulation of the circuit module will result in edge stiffener portions that are not coupled to the lead frame, but are secured within the encapsulant.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: April 6, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: Jeffrey Alan Miks, Markus Karl Liebhard
  • Patent number: 6713836
    Abstract: In a leadframe packaging structure, a leadframe includes a plurality of first leads, a plurality of second leads, and a die pad. The first leads define a chip-bonding region in which is arranged the die pad. The second leads extend and terminate into a plurality of contact pads in the chip-bonding region. An adhesive tape further is bonded on bottom surfaces of the contact pads. A chip is bonded on the die pad. At least a passive device is mounted between and electrically connects the contact pads. A plurality of bonding wires respectively connect the chip, the passive device, and the first and second leads. An encapsulant material encapsulates the chip, the passive device, and the bonding wires.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: March 30, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Tsung Liu, Kang-Wei Ma
  • Patent number: 6713849
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: March 30, 2004
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 6707689
    Abstract: There is disclosed a junction box including a junction box main body, a connector portion, and a cable portion which connects the junction box main body to the connector portion. Terminal connecting portions are formed to extend from opposite side edges of a strip portion of a flexible printed circuit constituting the cable portion in a short direction of the strip portion, and are connected to first to third connecting terminals. The third connecting terminal is connected to a desired connecting terminal connecting portion of a circuit distribution wiring circuit of a joint connector, electricity is conducted through a plurality of circuit portions in a desired circuit mode, and a wiring design freedom degree is enhanced.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: March 16, 2004
    Assignee: Fujikura, Ltd.
    Inventors: Atsushi Momota, Ichiro Terunuma, Hideyuki Kosugi, Nobumasa Misaki
  • Patent number: 6704210
    Abstract: A bioprosthesis sealing film strip is attached to a surgical stapler by passing a jaw of the stapler through openings formed in the ends of the strip. Following stapling the strip is released by making a cut from the opening to the edge of the strip. Alternatively, one end of the strip may be releasably secured to pins formed on the jaw.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: March 9, 2004
    Assignee: Medtronic, Inc.
    Inventor: David J. Myers
  • Patent number: 6684499
    Abstract: Methods are disclosed for fabricating spring structures in which a passive, conductive coating is deposited onto the spring structure before release. A release layer is deposited on a substrate and then a spring metal layer is formed thereon. A first mask is used to form a spring metal finger from these layers. A second mask defines a window exposing a tip of the finger. The release layer under the tip is etched through the window, and then a passive-conductive coating material (which may also have spring characteristics) is deposited on the tip. The second mask and residual coating material are then lifted off, and a third (release) mask is formed that is used to release a free end of the spring metal finger. The release mask is then stripped. When the passive-conductive coating includes spring characteristics, the stress variations of the coating help to lift the free end if the finger during release.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: February 3, 2004
    Assignee: Xerox Corporation
    Inventors: Linda T. Romano, David K. Fork, Harold Ackler
  • Patent number: 6683789
    Abstract: An electronic control module (20) comprising a housing (30), a printed circuit board (40), and a rigidizer (50). The housing (30) has an opening or window (34) for a removable connector (22). The printed circuit board (40) has a first side (42), a second side (44), and a plurality of contact pads (46). The first side (42) of the board (40) is used to retain components and circuitry. The plurality of contact pads (46) is positioned on the first side (42) of the printed circuit board (40). The rigidizer (50) is attached to the second side (44) of the printed circuit board (40) and provides structural backing for the printed circuit board (40) to compensate for any pressure induced to the first side (42) of the printed circuit board (40) by the removable connector (22). The window (34) in the housing (30) is positioned adjacent to the plurality of contact pads (46) on the first side (42) of the printed circuit board (40) to provide a single opening to each of the contact pads (46).
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: January 27, 2004
    Assignee: Motorola, Inc.
    Inventors: Romy Sheynis, Mark D. Gunderson, Stanton Rak
  • Patent number: 6617510
    Abstract: A metallic or an electrical trace having a terminus and a stress relief bend formed in the trace adjacent the terminus. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and extend from the flexible substrate or may be encapsulated by the flexible substrate. The electrical circuit and the flexible circuit each have a generally planar portion extending in the X and Y axis, with the stress relief bend projecting into the Z axis. This allows electrical traces to be spaced with a very narrow pitch because the stress relief bend does not consume any valuable real estate on the flexible circuit or the substrate to which the electrical trace is applied.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: September 9, 2003
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris M. Schreiber, Bao Le, Eric Dean Jensen
  • Publication number: 20030156397
    Abstract: A covering device for the interior of a motor vehicle protects an occupant from coming in contact with the supply lines installed in the vehicle, electric lines being situated as film conductors between two layers of the covering device. This permits simple assembly of a cockpit module in particular in a motor vehicle.
    Type: Application
    Filed: March 27, 2003
    Publication date: August 21, 2003
    Inventors: Reinhold Preissl, Volker Burkhardt, Kiriakos Karampatziakis, Heribert Uhl, Klaus Winitzki, Hermann Glas, Rupert Auer
  • Patent number: 6580165
    Abstract: A flip-chip with a solder pre-plated leadframe that includes locating holes. The leadframe does not include a die attach pad. Two of the leads include a locating or alignment hole for receiving a solder bump of the bumped die. The remaining leads include die contact areas for placement of the die thereon with the solder bumps contacting the die contact areas. The leads with the die contact areas are downset. The downset is approximately 4 mm.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: June 17, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Inderjit Singh
  • Patent number: 6577015
    Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: June 10, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 6573459
    Abstract: Flexible leads for making electrical connection in microelectronic components includes two metallic layers. The structural or core layer of the lead is formed having a hardness greater than the hardness of the second layer. The relative hardness between the first and second layers is achieved by controlling the grain size during deposition of the respective layers from an electroless or electroplating bath.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: June 3, 2003
    Assignee: Tessera, Inc.
    Inventors: David R. Baker, Hung-Ming Wang
  • Patent number: 6574120
    Abstract: A portable relay base is composed of an upper cover and a lower cover being oppositely joined to each other. The portable relay base at a lateral side thereof at least provides an outlet unit composed of two contact poles and/or one ground pole and at a proper position thereof provides an opening. The portable relay further comprises a power line carrier, a power line, and a circuit board. The power line carrier has a shape of disk and fits with the lower cover axially. An automatic positioning/wire collecting apparatus is provided in the power line carrier and a central hollow reel is provided at a top thereof with at least two concentric spacing rings in accordance with the number of poles of the power. The power line is a lead wire coiling around the reel as a bundle with an end thereof extending an electricity taking plug outside the opening and another end thereof having at least two conductive pieces. Both of the ends are fixedly attached to the spacing rings.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: June 3, 2003
    Inventor: Jonie Chou
  • Patent number: 6570101
    Abstract: A microelectronic lead element includes an elongated first leg having a surface releasably attached to a substrate. The first leg has a tip end and a base end. An elongated second leg includes a surface releasably attached to a substrate, the second leg having a tip end and a base end. The base end of the first leg is arranged adjacent the base end of the second leg. A body of conductive material is adapted for electrically connecting the base ends of the first and second legs together. The first and second legs extend away from their respective base ends and said body of conductive material in a common direction. Movement of the tip ends relative to each other in a vertical direction relative to the substrate causes flexure of the first and second legs in opposite directions upon release from the substrate.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: May 27, 2003
    Assignee: Tessera, Inc.
    Inventors: Thomas Di Stefano, John W. Smith
  • Patent number: 6558169
    Abstract: An apparatus includes a socket and a housing. The socket and the housing can define an interior region for receiving an integrated circuit package. The housing includes a conductive member with a first portion exposed adjacent a bottom surface of the housing and a second portion at a side surface adjacent the interior region. The first portion can be electrically in contact with a printed circuit board. The second portion can be electrically in contact with a conductive member at a side surface of the integrated circuit package.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: May 6, 2003
    Assignee: Intel Corporation
    Inventors: David G. Figueroa, Yuan-Liang Li, Hong Xie
  • Publication number: 20030076665
    Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.
    Type: Application
    Filed: November 22, 2002
    Publication date: April 24, 2003
    Inventors: Salman Akram, Warren M. Farnworth, Alan G. Wood, J. Michael Brooks, Eugene H. Cloud
  • Patent number: 6545227
    Abstract: An integrated circuit device includes a semiconductor chip, a circuit board and a layer of bonding material. The semiconductor chip has a metal plated surface on a first side and has a predetermined thickness. A first conductive layer formed of electrically conductive material is bonded to a first side of a first dielectric layer and defines a plurality of conducting elements. A second conductive layer defining a first electrical ground plane and formed of electrically conductive material is bonded to a second side of the first dielectric layer opposite the first conductive layer. The circuit board has a pocket formed therein, passing through the first conductive layer and through the first dielectric layer. The pocket is closed on the second side by the second conductive layer. A portion of the second conductive layer is exposed at a bottom of the pocket. The pocket is of substantially the same size and shape as the semiconductor chip.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: April 8, 2003
    Assignee: MCE/KDI Corporation
    Inventor: Lawrence H. Silverman
  • Patent number: 6542376
    Abstract: Disclosed is an electronics packaging system, which provides for a high density assembly of groups of similar solid state part packages. The system provides a novel method for interconnecting the signal paths, structurally assembling and supporting the parts, and removing heat generated within the components. The system approach disclosed typically starts at the level of assembling pre-packaged parts into modules, and permeates through to the printed circuit board and box levels of assembly. The system is applicable, but not limited to, solid state memory device packaging, which typically consists of many similar parts interconnected in a matrix bus type configuration. The assembly of a building block of numerous memory components allows for the modular construction of large amounts of solid state memory.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 1, 2003
    Assignee: L-3 Communications Corporation
    Inventor: Edwin George Watson
  • Patent number: 6538214
    Abstract: An interposer includes a substrate having opposing surfaces. Conductive terminals are disposed on both surfaces, and conductive terminals on one surface are electrically connected to conductive terminals on the opposing surface. Elongate, springable, conducive interconnect elements are fixed to conductive terminals on both surfaces.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: March 25, 2003
    Assignee: FormFactor, Inc.
    Inventor: Igor Y. Khandros
  • Patent number: 6535393
    Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: March 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Alan G. Wood, J. Michael Brooks, Eugene H. Cloud
  • Patent number: 6531662
    Abstract: A circuit substrate (10) comprises a first substrate split (11) formed with a predetermined wiring pattern (16) and a second substrate split (12) formed with a predetermined wiring pattern (17). The substrate splits are electrically and/or mechanically joined together, and the circuit substrate is bent at the joint. The joint is provided by a bendable joint member (13) including a plurality of leads (14) disposed in parallel and held by a thin piece of base film (20) integrally therewith. The joint member is attached to interconnect the first and the second substrate splits (11, 12).
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: March 11, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Nakamura
  • Publication number: 20030025192
    Abstract: An electrically conductive article such as a sheet having holes therein is coated with a dielectric polymer using a multi-stage electrophoretic deposition process. A coating of uncured polymer is deposited electrophoretically and then cured. After the first polymer is cured, the part is subject to a further electrophoretic deposition process and further curing. Use of a second electrophoretic deposition step allows effective coating of parts having small holes without plugging the holes. The coated parts may be used as microelectronic connection components such as chip carriers used in packaging semiconductor chips.
    Type: Application
    Filed: September 25, 2002
    Publication date: February 6, 2003
    Applicant: Tessera, Inc.
    Inventor: Belgacem Haba
  • Patent number: 6510058
    Abstract: Isolated planar conductive structures on separated layers of a PCB provide the normally-open, common, and normally-closed components of an electromechanical relay circuit to minimize inductive area. The isolated planar configuration reduces coupling of relay contact-noise currents to nearby sensitive circuits, and minimizes coupling EMI energy from nearby logic or microprocessor circuits to the relay contact circuits.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: January 21, 2003
    Assignee: Sensormatic Electronics Corporation
    Inventor: Raymond Kozakiewicz
  • Patent number: 6495773
    Abstract: A wire bonding method includes a first bonding process for forming a first ball-shaped part in a wire and bonding the first ball-shaped part to a first connected member; a ball-shaped part forming process for guiding the wire away from a position where the wire is bonded to an inner lead so as to form a predetermined loop, and a second bonding process for forming a second ball-shaped part in a predetermined position in the wire; and a second bonding process for bonding the second ball-shaped part to a semiconductor element pad that serves as a second connected member.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: December 17, 2002
    Assignee: Fujitsu Limited
    Inventors: Ryuji Nomoto, Kazuto Tsuji, Mitsutaka Sato, Junichi Kasai
  • Patent number: 6469907
    Abstract: Packaging for power circuitry. A circuit board and a power lead frame are packaged together in a module. In addition to providing electrical connections to power circuitry, the lead frame is employed to fix or partially fix the location of the circuit board in the package. For this purpose, one of the power lead frame and the circuit board includes a male portion and the other of the power lead frame and the circuit board includes a complementary female portion for mechanically coupling the circuit board and the lead frame.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: October 22, 2002
    Assignee: Team Pacific, Corporation
    Inventors: Alex Faveluke, Walt Noll
  • Patent number: 6469255
    Abstract: There is provided a composite wiring board that occupies a small space and is low in price and a manufacturing method thereof; the composite wiring board comprises at least two rigid wiring boards on end faces of which connection portions are formed, in which each of the rigid wiring boards is arranged so that each of the connection portions is situated on a plane and each of corresponding connection portions is connected with each other in the plane.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: October 22, 2002
    Assignee: Sony Corporation
    Inventors: Yoshio Watanabe, Toru Takebe, Mayumi Kosemura
  • Publication number: 20020145032
    Abstract: Interconnection elements for electronic components, exhibiting desirable mechanical characteristic (such as resiliency, for making pressure contacts) are formed by using a shaping tool (512) to shape an elongate core element (502) of a soft material (such as gold or soft copper wire) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped core element with a hard material (such as nickel and its alloys), to impart to desired spring (resilient) characteristic to the resulting composite interconnection element. A final overcoat of a material having superior electrical qualities (e.g., electrical conductivity and/or solderability) may be applied to the composite interconnection element.
    Type: Application
    Filed: December 29, 2000
    Publication date: October 10, 2002
    Applicant: FORMFACTOR INC
    Inventors: Igor Y. Khandros, Thomas H. Dozier, Gary W. Grube, Gaetan L. Mathieu
  • Patent number: 6448508
    Abstract: An electrical component is provided with a flexible strip (10) of connection conductors (11-16), which comprises two conductors (11, 16) for testing continuity, which are connected by the component and extending along the edges of the strip (10).
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: September 10, 2002
    Assignee: Sagem SA
    Inventor: Yves Lequenne
  • Patent number: 6448507
    Abstract: Damage to and short circuiting of bond fingers on a substrate due to die-attach resin bleed is prevented, thereby increasing yield and improving reliability. Embodiments include forming a trough in a solder mask on a substrate between the bond fingers and semiconductor chip to prevent the die-attach resin from reaching the bond fingers.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Edwin Fontecha, Viswanath Valluri, Donald Bottarini
  • Patent number: 6445594
    Abstract: A lower semiconductor element is mounted facing down on an insulating circuit board, and an upper semiconductor element is stacked facing up on the lower semiconductor element. Openings are provided in the insulating circuit board at a location facing the element electrodes of the lower semiconductor element, and the element electrodes of the lower semiconductor element are connected to the board electrodes on the lower surface of the insulating circuit board through the openings. Also, the element electrodes of the upper semiconductor element are connected to the board electrodes on the upper surface of the insulating circuit board. Thus, a high-density semiconductor device is provided by stacking a plurality of semiconductor elements.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: September 3, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Nakagawa, Michitaka Kimura
  • Patent number: 6420661
    Abstract: A connector element for connecting microelectronic elements includes a dielectric sheet having pairs of elongated, flexible leads in registry on opposite surfaces of the sheet. The leads are connected at their terminal ends which are in registry with each other. The terminal ends are offset from the tip ends in a horizontal direction. The tip ends are releasably attached to the surfaces of the dielectric sheet. The tip ends may be connected to microelectronic elements, which may be displaced relative to each other in a vertical direction.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: July 16, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas Di Stefano, John W. Smith
  • Publication number: 20020080588
    Abstract: A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are “stacked up” so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed.
    Type: Application
    Filed: December 27, 2001
    Publication date: June 27, 2002
    Applicant: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Publication number: 20020067181
    Abstract: A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are “stacked up” so that the orientation of the space transformer, hence the orientation of the tips of the probe elements, can be adjusted without changing the orientation of the probe card. Suitable mechanisms for adjusting the orientation of the space transformer, and for determining what adjustments to make, are disclosed.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 6, 2002
    Applicant: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 6399896
    Abstract: Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Frank J. Downes, Jr., Donald S. Farquhar, Robert M. Japp, William J. Rudik
  • Patent number: 6399889
    Abstract: A head interconnect circuit for connecting transducer elements of a data head to drive circuitry including an alignment finger on a lead tip for aligning leads relative to connectors or solder pads for electrically connecting heads to drive circuitry. A method for connecting a head interconnect circuit to a printed circuit supported on an head actuator including aligning an alignment finger on the lead tip with a printed surface of a drive circuit for soldering leads on the lead tip to solder pads or connectors on the drive circuit.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: June 4, 2002
    Assignee: Seagate Technology LLC
    Inventors: Kurt J. Korkowski, Kenneth R. Fastner, Adam K. Himes, Gregory P. Myers, Andrew R. Motzko